| 964dfee1 | 16-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add BL32 SP_min secure monitor
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
S
stm32mp1: Add BL32 SP_min secure monitor
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
show more ...
|
| 10a511ce | 24-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add DDR support and its security with TZC400
The DDR driver is under dual license, BSD and GPLv2.
The configuration parameters are taken from device tree.
Signed-off-by: Yann Gautier <yan
stm32mp1: Add DDR support and its security with TZC400
The DDR driver is under dual license, BSD and GPLv2.
The configuration parameters are taken from device tree.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
show more ...
|
| e4f559ff | 16-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add PMIC support
If a PMIC companion chip is present on board, it has to be configured
for regulators supplies.
This check is done with board DT configuration.
Signed-off-by: Yann Gautier
stm32mp1: Add PMIC support
If a PMIC companion chip is present on board, it has to be configured
for regulators supplies.
This check is done with board DT configuration.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
show more ...
|
| 278c34df | 05-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add console support
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com> |
| e58a53fb | 20-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: save boot information in backup registers
This will be used by BL33 to get boot device and instance.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathie
stm32mp1: save boot information in backup registers
This will be used by BL33 to get boot device and instance.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
show more ...
|
| 6a339a49 | 13-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add GPIO support
The management of pinctrl nodes of device tree is also added.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed
stm32mp1: Add GPIO support
The management of pinctrl nodes of device tree is also added.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
show more ...
|
| 7839a050 | 24-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add clock and reset support
The clock driver is under dual license, BSD and GPLv2.
The clock driver uses device tree, so a minimal support for this is added.
The required files for driver
stm32mp1: Add clock and reset support
The clock driver is under dual license, BSD and GPLv2.
The clock driver uses device tree, so a minimal support for this is added.
The required files for driver and DTS files are in include/dt-bindings/.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
show more ...
|
| 4353bb20 | 16-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
Introduce STMicroelectronics STM32MP1 platform
STM32MP1 is a microprocessor designed by STMicroelectronics,
based on a dual Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.
Introduce STMicroelectronics STM32MP1 platform
STM32MP1 is a microprocessor designed by STMicroelectronics,
based on a dual Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.
STM32MP1 uses BL2 compiled with BL2_AT_EL3.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
show more ...
|
| d323af9e | 06-Jul-2018 |
Daniel Boulby <daniel.boulby@arm.com> |
Rework page table setup for varying number of mem regions
Change arm_setup_page_tables() to take a variable number of memory
regions. Remove coherent memory region from BL1, BL2 and BL2U as
their co
Rework page table setup for varying number of mem regions
Change arm_setup_page_tables() to take a variable number of memory
regions. Remove coherent memory region from BL1, BL2 and BL2U as
their coherent memory region doesn't contain anything and
therefore has a size of 0. Add check to ensure this
doesn't change without us knowing.
Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
show more ...
|
| cffb0034 | 24-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1488 from b49020/integration
synquacer: Enable optional OP-TEE support |
| 790e6c5b | 24-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1485 from jeenu-arm/ras
Double-fault and fatal error handling support |
| 6cb2a397 | 19-Jul-2018 |
Sumit Garg <sumit.garg@linaro.org> |
synquacer: Enable optional OP-TEE support
OP-TEE loading is optional on Developerbox controlled via SCP
firmware. To check if OP-TEE is loaded or not, we use DRAM1 region
info passed by SCP firmware
synquacer: Enable optional OP-TEE support
OP-TEE loading is optional on Developerbox controlled via SCP
firmware. To check if OP-TEE is loaded or not, we use DRAM1 region
info passed by SCP firmware.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
show more ...
|
| ecd62429 | 19-Jul-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
Arm platforms: Fix type mismatch for arm_pm_idle_states
This also gets rid of MISRA violations for Rule 8.3 and 8.4.
Change-Id: I45bba011b16f90953dd4b260fcd58381f978eedc
Signed-off-by: Jeenu Viswam
Arm platforms: Fix type mismatch for arm_pm_idle_states
This also gets rid of MISRA violations for Rule 8.3 and 8.4.
Change-Id: I45bba011b16f90953dd4b260fcd58381f978eedc
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| 2bc3dba9 | 18-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
PSCI: Fix MISRA defects in platform code
Fix violations of MISRA C-2012 Rules 10.1, 10.3, 13.3, 14.4, 17.7 and
17.8.
Change-Id: I6c9725e428b5752f1d80684ec29cb6c52a5c0c2d
Signed-off-by: Antonio Nino
PSCI: Fix MISRA defects in platform code
Fix violations of MISRA C-2012 Rules 10.1, 10.3, 13.3, 14.4, 17.7 and
17.8.
Change-Id: I6c9725e428b5752f1d80684ec29cb6c52a5c0c2d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| 99eb5ae8 | 18-Jul-2018 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
hikey: include TBB in BL1
BL1 is used in recovery mode on HiKey. The TBB implementation
on HiKey is in BL2. It means that user need to build ATF BL2
with TBB and ATF BL1 with non-TBB. It's inconveni
hikey: include TBB in BL1
BL1 is used in recovery mode on HiKey. The TBB implementation
on HiKey is in BL2. It means that user need to build ATF BL2
with TBB and ATF BL1 with non-TBB. It's inconvenient.
So include TBB in BL1, too.
Signed-off-by: Teddy Reed <teddy@prosauce.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
show more ...
|
| 1083b2b3 | 20-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
PSCI: Fix types of definitions
Also change header guards to fix defects of MISRA C-2012 Rule 21.1.
Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
PSCI: Fix types of definitions
Also change header guards to fix defects of MISRA C-2012 Rule 21.1.
Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| ba0248b5 | 19-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6
Marvell support for Armada 8K SoC family |
| 992a3536 | 19-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1483 from antonio-nino-diaz-arm/an/rpi3-psci
rpi3: PSCI and Linux boot improvements |
| e4686fd8 | 19-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1449 from theopolis/hikey-tbb
hikey: Add experimental TBB support |
| 8ff0dfa7 | 19-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1482 from sandrine-bailleux-arm/sb/fix-hcptr
Misc arch.h fixes and cleanup |
| eaeaa4d0 | 06-Jul-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
RAS: Introduce handler for EL3 EAs
External Aborts while executing in EL3 is fatal in nature. This patch
allows for the platform to define a handler for External Aborts received
while executing in E
RAS: Introduce handler for EL3 EAs
External Aborts while executing in EL3 is fatal in nature. This patch
allows for the platform to define a handler for External Aborts received
while executing in EL3. A default implementation is added which falls
back to platform unhandled exception.
Change-Id: I466f2c8113a33870f2c7d2d8f2bf20437d9fd354
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| d5a23af5 | 17-May-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
RAS: Introduce handler for Double Faults
Double fault is when the PE receives another error whilst one is being
handled. To detect double fault condition, a per-CPU flag is introduced
to track the s
RAS: Introduce handler for Double Faults
Double fault is when the PE receives another error whilst one is being
handled. To detect double fault condition, a per-CPU flag is introduced
to track the status of error handling. The flag is checked/modified
while temporarily masking external aborts on the PE.
This patch routes double faults to a separate platform-defined handler.
Change-Id: I70e9b7ba4c817273c55a0af978d9755ff32cc702
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| b56dc2a9 | 17-May-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
RAS: Introduce handler for Uncontainable errors
Uncontainable errors are the most severe form of errors, which typically
mean that the system state can't be trusted any more. This further means
that
RAS: Introduce handler for Uncontainable errors
Uncontainable errors are the most severe form of errors, which typically
mean that the system state can't be trusted any more. This further means
that normal error recovery process can't be followed, and an orderly
shutdown of the system is often desirable.
This patch allows for the platform to define a handler for Uncontainable
errors received. Due to the nature of Uncontainable error, the handler
is expected to initiate an orderly shutdown of the system, and therefore
is not expected to return. A default implementation is added which falls
back to platform unhandled exception.
Also fix ras_arch.h header guards.
Change-Id: I072e336a391a0b382e77e627eb9e40729d488b55
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| 34ec7ec3 | 07-Jun-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: Add board support for A8K platform
Add support for A8K platform boards
Change-Id: Ife025d930d2ab6cabbc13bbe19b2273cc1c938c8
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-
plat: marvell: Add board support for A8K platform
Add support for A8K platform boards
Change-Id: Ife025d930d2ab6cabbc13bbe19b2273cc1c938c8
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| 486f868b | 07-Jun-2018 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: Add common ARMADA platform components
Add common Marvell ARMADA platform components.
This patch also includes common components for Marvell
ARMADA 8K platforms.
Change-Id: I42192fdc6
plat: marvell: Add common ARMADA platform components
Add common Marvell ARMADA platform components.
This patch also includes common components for Marvell
ARMADA 8K platforms.
Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|