| 58192800 | 25-Jun-2018 |
Nariman Poushin <nariman.poushin@linaro.org> |
plat/arm: css: Set MT bit in incoming mpidr arugments
Change-Id: I278d6876508800abff7aa2480910306a24de5378
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org> |
| a41d1b2c | 01-Aug-2018 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
plat/sgi: switch to using scmi
The Arm SGI platforms can switch to using SCMI. So enable support for
SCMI and remove portions of code that would be unused after switching
to SCMI.
Change-Id: Ifd9e1
plat/sgi: switch to using scmi
The Arm SGI platforms can switch to using SCMI. So enable support for
SCMI and remove portions of code that would be unused after switching
to SCMI.
Change-Id: Ifd9e1c944745f703da5f970b5daf1be2b07ed14e
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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| 8e1cc449 | 02-Aug-2018 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
sgi: disable CPU power down bit in reset handler
On SGI platforms, the 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1'
register requires an explicit write to clear it for hotplug and
idle to function correc
sgi: disable CPU power down bit in reset handler
On SGI platforms, the 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1'
register requires an explicit write to clear it for hotplug and
idle to function correctly. The reset value of this bit is zero
but it still requires this explicit clear to zero. This indicates
that this could be a model related issue but for now this issue can
be fixed be clearing the CORE_PWRDN_EN in the platform specific
reset handler function.
Change-Id: I4222930daa9a3abacdace6b7c3f4a5472ac0cb19
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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| fec36484 | 08-May-2018 |
Roberto Vargas <roberto.vargas@arm.com> |
Create a library file for libfdt
TF Makefile was linking all the objects files generated for the
fdt library instead of creating a static library that could be
used in the linking stage.
Change-Id:
Create a library file for libfdt
TF Makefile was linking all the objects files generated for the
fdt library instead of creating a static library that could be
used in the linking stage.
Change-Id: If3705bba188ec39e1fbf2322a7f2a9a941e1b90d
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| f68bc8a1 | 03-Aug-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1506 from danielboulby-arm/db/SeparateCodeAndROData
Fix build for SEPARATE_CODE_AND_RODATA=0 |
| 2ecaafd2 | 16-Jul-2018 |
Daniel Boulby <daniel.boulby@arm.com> |
Fix build for SEPARATE_CODE_AND_RODATA=0
TF won't build since no memory region is specified
for when SEPARATE_CODE_AND_RODATA=0 it still relies on
the ARM_MAP_BL_RO_DATA region which is never define
Fix build for SEPARATE_CODE_AND_RODATA=0
TF won't build since no memory region is specified
for when SEPARATE_CODE_AND_RODATA=0 it still relies on
the ARM_MAP_BL_RO_DATA region which is never defined for
this case. Create memory region combining code and RO data for
when the build flag SEPARATE_CODE_AND_RODATA=0 to fix this
Change-Id: I6c129eb0833497710cce55e76b8908ce03e0a638
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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| 72bc6318 | 30-Jul-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1498 from glneo/cache-early-fixes
Early cache enable and coherency fixes |
| 2ee596c4 | 30-Jul-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1493 from antonio-nino-diaz-arm/an/xlat-misra
Fix MISRA defects in xlat tables lib and SP805 driver |
| e7b9886c | 24-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9
xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.
Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| eef90a77 | 27-Jul-2018 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1497 from SNG-ARM/master
RAS changes for SGI575 platform |
| 128dad9a | 27-Jul-2018 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1494 from hzhuang1/pcie_pin
Hikey960: configure pins for PCIe controller |
| 16bec9c2 | 16-Jul-2018 |
Kaihua Zhong <zhongkaihua@huawei.com> |
Hikey960: configure pins for PCIe controller
GPIO_089 connects to PCIE_PERST_N. It needs to be configured as
output low.
Signed-off-by: Kaihua Zhong <zhongkaihua@huawei.com>
Signed-off-by: Xiaowei
Hikey960: configure pins for PCIe controller
GPIO_089 connects to PCIE_PERST_N. It needs to be configured as
output low.
Signed-off-by: Kaihua Zhong <zhongkaihua@huawei.com>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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| 903f13d3 | 26-Jul-2018 |
Andrew F. Davis <afd@ti.com> |
ti: k3: common: Only enable caches early
We can enter and exit coherency without any software operations,
but HW_ASSISTED_COHERENCY has stronger implications that are
causing issues. Until these can
ti: k3: common: Only enable caches early
We can enter and exit coherency without any software operations,
but HW_ASSISTED_COHERENCY has stronger implications that are
causing issues. Until these can be resolved, only use the weaker
WARMBOOT_ENABLE_DCACHE_EARLY flag.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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| f29d1828 | 16-May-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
RAS: SGI: Add flags needed to build components for RAS feature
Add the various flags that are required to build the components needed
to enable the RAS feature on SGI575 platform. By default, all fl
RAS: SGI: Add flags needed to build components for RAS feature
Add the various flags that are required to build the components needed
to enable the RAS feature on SGI575 platform. By default, all flags
are set to 0, disabling building of all corresponding components.
Change-Id: I7f8536fba895043ef6e397cc33ac9126cb572132
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| 167dae4d | 16-May-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
RAS: SGI575: Add platform specific RAS changes
Add platform specific changes needed to add support for the RAS
feature on SGI575 platform, including adding a mapping for the
CPER buffer being used o
RAS: SGI575: Add platform specific RAS changes
Add platform specific changes needed to add support for the RAS
feature on SGI575 platform, including adding a mapping for the
CPER buffer being used on SGI575 platform.
Change-Id: I01a982e283609b5c48661307906346fa2738a43b
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| 485fc954 | 16-May-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
RAS: SGI: Add platform handler for RAS interrupts
Add a platform specific handler for RAS interrupts and configure the
platform RAS interrupts for EL3 handling. The interrupt handler passes
control
RAS: SGI: Add platform handler for RAS interrupts
Add a platform specific handler for RAS interrupts and configure the
platform RAS interrupts for EL3 handling. The interrupt handler passes
control to StandaloneMM code executing in S-EL0, which populates the
CPER buffer with relevant error information. The handler subsequently
invokes the SDEI client which processes the information in the error
information in the CPER buffer. The helper functions
plat_sgi_get_ras_ev_map and plat_sgi_get_ras_ev_map_size would be
defined for sgi platforms in the subsequent patch, which adds sgi575
specific RAS changes.
Change-Id: I490f16c15d9917ac40bdc0441659b92380108d63
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| d9523919 | 16-May-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
SPM: SGI: Map memory allocated for secure partitions
The secure partition manager reserves chunks of memory which are used
for the S-EL0 StandaloneMM image and the buffers required for
communication
SPM: SGI: Map memory allocated for secure partitions
The secure partition manager reserves chunks of memory which are used
for the S-EL0 StandaloneMM image and the buffers required for
communication between the Non-Secure world with the StandaloneMM
image. Add the memory chunks to relevant arrays for mapping the
regions of memory with corresponding attributes.
Change-Id: If371d1afee0a50ca7cacd55e16aeaca949d5062b
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| 2e4a509d | 16-May-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
ARM platforms: Allow board specific definition of SP stack base
The SGI platforms need to allocate memory for CPER buffers. These
platform buffers would be placed between the shared reserved memory
ARM platforms: Allow board specific definition of SP stack base
The SGI platforms need to allocate memory for CPER buffers. These
platform buffers would be placed between the shared reserved memory
and the per cpu stack memory, thus the need to redefine stack base
pointer for these platforms. This patch allows each board in ARM
platform to define the PLAT_SP_IMAGE_STACK_BASE.
Change-Id: Ib5465448b860ab7ab0f645f7cb278a67acce7be9
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| d9cc9372 | 16-May-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
SGI: Include arm_spm_def.h in platform_def.h
Include arm_spm_def.h in the platform_def.h file. Without this
inclusion, we get build errors like
In file included from services/std_svc/spm/sp_setup.c
SGI: Include arm_spm_def.h in platform_def.h
Include arm_spm_def.h in the platform_def.h file. Without this
inclusion, we get build errors like
In file included from services/std_svc/spm/sp_setup.c:12:0:
services/std_svc/spm/sp_setup.c: In function 'spm_sp_setup':
services/std_svc/spm/sp_setup.c:61:57: error: 'PLAT_SPM_BUF_BASE'
undeclared (first use in this function)
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, PLAT_SPM_BUF_BASE);
Now that the platform_def.h includes arm_spm_def.h, remove inclusion
of platform_def.h in arm_spm_def.h to remove the circular dependency.
Change-Id: I5225c8ca33fd8d288849524395e436c3d56daf17
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| 46b69e3d | 10-Mar-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
Include board_arm_def.h through the platform's header
The board_arm_def.h header file needs to be included via the platform
definition header. Not doing so, results in a redefinition error of
PLAT_A
Include board_arm_def.h through the platform's header
The board_arm_def.h header file needs to be included via the platform
definition header. Not doing so, results in a redefinition error of
PLAT_ARM_MAX_BL31_SIZE macro, if defined in the platform definition
file.
Change-Id: I1d178f6e8a6a41461e7fbcab9f6813a2faa2d82b
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| 60e062fb | 25-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra
Fix several MISRA defects in PSCI library |
| d87d524e | 25-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1466 from Yann-lms/stm32mp1
Add STMicroelectronics STM32MP1 platform support |
| cad25f14 | 25-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1491 from jeenu-arm/misra-fix
Arm platforms: Fix type mismatch for arm_pm_idle_states |
| f94523ed | 25-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1472 from danielboulby-arm/db/Reclaim
Rework page table setup for varying number of mem regions |
| f74cbc93 | 16-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Link BL2, BL32 and DTB in one binary
platform.mk is updated to have compilation rules for DTB, stm32image tool,
and the concatenation of the 3 binaries.
A new linker script and an assembly
stm32mp1: Link BL2, BL32 and DTB in one binary
platform.mk is updated to have compilation rules for DTB, stm32image tool,
and the concatenation of the 3 binaries.
A new linker script and an assembly file are added to manage this.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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