stm32mp1: rename stpmu1 to stpmic1

This is the correct name of the IP.
Rename stm32mp1_pmic files to stm32mp_pmic.

Change-Id: I238a7d1f9a1d099daf7788dc9ebbd3146ba2f15f
Signed-off-by: Yann Gautier <

stm32mp1: rename stpmu1 to stpmic1

This is the correct name of the IP.
Rename stm32mp1_pmic files to stm32mp_pmic.

Change-Id: I238a7d1f9a1d099daf7788dc9ebbd3146ba2f15f
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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drivers: st: move i2c driver in its own folder

The driver could be used for other devices than PMIC.

Change-Id: I4569e7c0028e52e1ff2fe9d38f11de11e95d1897
Signed-off-by: Yann Gautier <yann.gautier@s

drivers: st: move i2c driver in its own folder

The driver could be used for other devices than PMIC.

Change-Id: I4569e7c0028e52e1ff2fe9d38f11de11e95d1897
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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warp7: Define DTB overlay address in memory map

This patch defines the expected DTB overlay address in the memory map for
this platform. Its important that all points in the boot process agree on
th

warp7: Define DTB overlay address in memory map

This patch defines the expected DTB overlay address in the memory map for
this platform. Its important that all points in the boot process agree on
this memory map even if not all elements utilize it.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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warp7: io_storage: Remove DTB from FIP

Recently upstreamed changes to OP-TEE mean that it is possible for OP-TEE
to provide a DTB overlay directly to subsequent boot stages thus negating
the require

warp7: io_storage: Remove DTB from FIP

Recently upstreamed changes to OP-TEE mean that it is possible for OP-TEE
to provide a DTB overlay directly to subsequent boot stages thus negating
the requirement to bundle a DTB in the FIP.

This patch switches off the dependency on the DTB in the FIP descriptor
instead we will provide the necessary data as an overlay from OP-TEE.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx: add i.MX8 SoCs build info SIP(silicon provider) service support

This patch adds NXP i.MX8 SoCs' build info SIP support for easy debug.
With this function enabled, TF-A's commit hash can be show

imx: add i.MX8 SoCs build info SIP(silicon provider) service support

This patch adds NXP i.MX8 SoCs' build info SIP support for easy debug.
With this function enabled, TF-A's commit hash can be showed in u-boot
debug console when booting up, when there is any issue which could be
related to TF-A, users can use the commit hash value to easily identify
which commit introduces the issue.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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imx: add i.MX8 SoCs thermal alarm SIP(silicon provider) service support

For NXP's i.MX8 SoCs with system controller inside, thermal sensors
are maintained by SCFW, Linux needs to call SMC to trap to

imx: add i.MX8 SoCs thermal alarm SIP(silicon provider) service support

For NXP's i.MX8 SoCs with system controller inside, thermal sensors
are maintained by SCFW, Linux needs to call SMC to trap to TF-A for
thermal alarm operation etc. by calling SCFW API.

This patch adds temperature alarm SIP service support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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imx: add i.MX8 SoCs OTP SIP(silicon provider) service support

For NXP's i.MX8 SoCs with system controller inside, OTP is
maintained by SCFW, Linux needs to call SMC to trap to TF-A
for OTP read/writ

imx: add i.MX8 SoCs OTP SIP(silicon provider) service support

For NXP's i.MX8 SoCs with system controller inside, OTP is
maintained by SCFW, Linux needs to call SMC to trap to TF-A
for OTP read/write etc. operations by calling SCFW API.

This patch adds OTP SIP service support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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imx: support for i.MX8 SoCs misc IPC

NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of misc functions like temperature alarm, dma etc., other
Cortex-A clusters can send out co

imx: support for i.MX8 SoCs misc IPC

NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of misc functions like temperature alarm, dma etc., other
Cortex-A clusters can send out command via MU (Message Unit) to
system controller for misc operation etc..

This patch adds misc IPC(inter-processor communication) support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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imx: add wakeup source SIP runtime service support

On i.MX8QM/i.MX8QX with system controller inside, the wakeup
source is managed in SCFW(system controller firmware), if the
wakeup source is belonge

imx: add wakeup source SIP runtime service support

On i.MX8QM/i.MX8QX with system controller inside, the wakeup
source is managed in SCFW(system controller firmware), if the
wakeup source is belonged to system controller partition, then
before Linux suspend, the wakeup source should be set to
SC_PM_WAKE_SRC_SCU, and if the wakeup source is belonged to
Cortex-A partition, the wakeup source should be set to
SC_PM_WAKE_SRC_IRQSTEER, so need to add wakeup source SIP runtime
service to get Linux kernel's wakeup source and set the correct
wakeup source for system controller.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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Merge pull request #1760 from igoropaniuk/rpi3_preloaded_dtb_fix

rpi3: fix RPI3_PRELOADED_DTB_BASE usage

Merge pull request #1754 from Anson-Huang/master

Add i.MX8 SoC SRTC/cpu-freq SIP runtime service support

imx: add cpu-freq SIP runtime service support

On i.MX8QM/i.MX8QX with system controller inside, the CPU's clock
rate is managed by SCFW(system controller firmware) and can ONLY be
changed from secur

imx: add cpu-freq SIP runtime service support

On i.MX8QM/i.MX8QX with system controller inside, the CPU's clock
rate is managed by SCFW(system controller firmware) and can ONLY be
changed from secure world, so SIP runtime service is needed for
setting CPU's clock rate, this patch adds cpu-freq SIP runtime service
support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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imx: add imx8qm/imx8qx SRTC SIP runtime service support

On i.MX8QM/i.MX8QX with system controller inside, the SRTC is
managed by SCFW(system controller firmware) and some functions
like setting SRTC

imx: add imx8qm/imx8qx SRTC SIP runtime service support

On i.MX8QM/i.MX8QX with system controller inside, the SRTC is
managed by SCFW(system controller firmware) and some functions
like setting SRTC's time etc. can ONLY be requested from secure
world, so SIP runtime service is needed for such kind of operations,
this patch adds SRTC SIP runtime service support for i.MX8QM and
i.MX8QX.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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Support for NXP's i.MX8 SoCs timer IPC

NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters lik

Support for NXP's i.MX8 SoCs timer IPC

NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters like Cortex-A35 can send out command
via MU (Message Unit) to system controller for timer operation.

This patch adds timer IPC(inter-processor communication) support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

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rpi3: fix RPI3_PRELOADED_DTB_BASE usage

In case if `RPI3_PRELOADED_DTB_BASE` isn't defined explicitly with
proper pre-loaded DTB address, `add_define` macro defined in
`make_helpers/build_macros.mk`

rpi3: fix RPI3_PRELOADED_DTB_BASE usage

In case if `RPI3_PRELOADED_DTB_BASE` isn't defined explicitly with
proper pre-loaded DTB address, `add_define` macro defined in
`make_helpers/build_macros.mk` still supplies this definition to the
compiler like `-DRPI3_PRELOADED_DTB_BASE`, and it's obviously is set to
default value 1.

This simply leads to the wrong `MAP_NS_DTB` region definition (base_va
is set `0x1` instead of `0x00010000`) in `plat/rpi3/rpi3_common.c`:

Which causes aligment check to fail in `mmap_add_region_check()`:
VERBOSE: base_pa: 0x00000001, base_va: 0x00000001, size: 0x00010000
...
ERROR: mmap_add_region_check() failed. error -22

Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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Tegra186: mce: remove unused type conversions

This patch removes unused type conversions as all the relevant macros
now use U()/ULL(), making these explicit typecasts unnecessary.

Change-Id: I01fb5

Tegra186: mce: remove unused type conversions

This patch removes unused type conversions as all the relevant macros
now use U()/ULL(), making these explicit typecasts unnecessary.

Change-Id: I01fb534649db2aaf186406b1aef6897662b44fe3
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra210: Enable ECC reporting for B01 SKUs

This patch enables L2 error correction and parity protection
for Tegra210 on boot and exit from suspend. The previous bootloader
sets the boot parameter,

Tegra210: Enable ECC reporting for B01 SKUs

This patch enables L2 error correction and parity protection
for Tegra210 on boot and exit from suspend. The previous bootloader
sets the boot parameter, indicating ECC reporting, only for B01 SKUs.

Change-Id: I6927884d375a64c69e2f1e9aed85f95c5e3cb17c
Signed-off-by: Sam Payne <spayne@nvidia.com>

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Tegra210: skip the BTB invalidate workaround for B01 SKUs

This patch skips the BTB invalidate workaround for Tegra210-B01 chips, as
they have already been fixed in the hardware. To allow the .S file

Tegra210: skip the BTB invalidate workaround for B01 SKUs

This patch skips the BTB invalidate workaround for Tegra210-B01 chips, as
they have already been fixed in the hardware. To allow the .S file to
include macros, add proper guards to tegra_platform.h.

Change-Id: I0826d3c54faeffc9cb0709331f47cbdf25d4b653
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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Tegra186: memctrl_v2: Set MC clients ordering as per client needs

Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO)
based on the latest info received from HW team as a part

Tegra186: memctrl_v2: Set MC clients ordering as per client needs

Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO)
based on the latest info received from HW team as a part of BW issues debug.

SMMU Client config register are obsolete from T186. Clean up the unnecessary
register definitions and programming of these registers.
Cleanup unnecessary macros as well.

Change-Id: I0d28ae8842a33ed534f6a15bfca3c9926b3d46b2
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

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Tegra210: memmap all the IRAM memory banks

This patch memmaps all the IRAM memory banks during boot. The BPMP
firmware might place the channels in any of the IRAMs, so it is better
to map all the ba

Tegra210: memmap all the IRAM memory banks

This patch memmaps all the IRAM memory banks during boot. The BPMP
firmware might place the channels in any of the IRAMs, so it is better
to map all the banks to avoid surprises.

Change-Id: Ia009a65d227ee50fbb23e511ce509daf41b877ee
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: bpmp: fix check to see if Atomics block is powered on

This patch fixes the logic to check if Atomics hardware block is powered
on during boot

Reported by: Peter De Schrijver <pdeschrijver@nv

Tegra: bpmp: fix check to see if Atomics block is powered on

This patch fixes the logic to check if Atomics hardware block is powered
on during boot

Reported by: Peter De Schrijver <pdeschrijver@nvidia.com>

Change-Id: I4a6521bcee37225d1402321151c48fa631776b8a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: increase MAX_XLAT_TABLES and MAX_MMAP_REGIONS

This patch updates the macros to include the newly added IRAM
memory apertures.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id:

Tegra210: increase MAX_XLAT_TABLES and MAX_MMAP_REGIONS

This patch updates the macros to include the newly added IRAM
memory apertures.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I931daa310d738e8bf966f14e11d0631920e9bdde

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Tegra186: setup: fix defects flagged by MISRA scan

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

For

Tegra186: setup: fix defects flagged by MISRA scan

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Force operands of an operator to the same type category [Rule 10.4]

Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]

Change-Id: I4840c3122939f736113d61f1462af3bd7b0b5085
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra186: PM: fix MISRA defects in plat_psci_handlers.c

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Tegra186: PM: fix MISRA defects in plat_psci_handlers.c

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

convert object type to match the type of function parameters
[Rule 10.3]

Force operands of an operator to the same type category [Rule 10.4]

Fix implicit widening of composite assignment [Rule 10.6]

Change-Id: I5840a07f37beefc3326ac56d0b4a4701602bd8a8
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra186: mce: remove unwanted print messages

This patch removes unwanted error prints from the MCE command
handler, to reduce the code complexity for this function.

Tested with 'pmccabe'

Change-I

Tegra186: mce: remove unwanted print messages

This patch removes unwanted error prints from the MCE command
handler, to reduce the code complexity for this function.

Tested with 'pmccabe'

Change-Id: I375d289db1df9e119eeb1830210974457c8905a4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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