1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <denver.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 20 #include <mce.h> 21 #include <mce_private.h> 22 #include <t18x_ari.h> 23 #include <tegra_def.h> 24 #include <tegra_platform.h> 25 26 /* NVG functions handlers */ 27 static arch_mce_ops_t nvg_mce_ops = { 28 .enter_cstate = nvg_enter_cstate, 29 .update_cstate_info = nvg_update_cstate_info, 30 .update_crossover_time = nvg_update_crossover_time, 31 .read_cstate_stats = nvg_read_cstate_stats, 32 .write_cstate_stats = nvg_write_cstate_stats, 33 .call_enum_misc = ari_enumeration_misc, 34 .is_ccx_allowed = nvg_is_ccx_allowed, 35 .is_sc7_allowed = nvg_is_sc7_allowed, 36 .online_core = nvg_online_core, 37 .cc3_ctrl = nvg_cc3_ctrl, 38 .update_reset_vector = ari_reset_vector_update, 39 .roc_flush_cache = ari_roc_flush_cache, 40 .roc_flush_cache_trbits = ari_roc_flush_cache_trbits, 41 .roc_clean_cache = ari_roc_clean_cache, 42 .read_write_mca = ari_read_write_mca, 43 .update_ccplex_gsc = ari_update_ccplex_gsc, 44 .enter_ccplex_state = ari_enter_ccplex_state, 45 .read_write_uncore_perfmon = ari_read_write_uncore_perfmon, 46 .misc_ccplex = ari_misc_ccplex 47 }; 48 49 /* ARI functions handlers */ 50 static arch_mce_ops_t ari_mce_ops = { 51 .enter_cstate = ari_enter_cstate, 52 .update_cstate_info = ari_update_cstate_info, 53 .update_crossover_time = ari_update_crossover_time, 54 .read_cstate_stats = ari_read_cstate_stats, 55 .write_cstate_stats = ari_write_cstate_stats, 56 .call_enum_misc = ari_enumeration_misc, 57 .is_ccx_allowed = ari_is_ccx_allowed, 58 .is_sc7_allowed = ari_is_sc7_allowed, 59 .online_core = ari_online_core, 60 .cc3_ctrl = ari_cc3_ctrl, 61 .update_reset_vector = ari_reset_vector_update, 62 .roc_flush_cache = ari_roc_flush_cache, 63 .roc_flush_cache_trbits = ari_roc_flush_cache_trbits, 64 .roc_clean_cache = ari_roc_clean_cache, 65 .read_write_mca = ari_read_write_mca, 66 .update_ccplex_gsc = ari_update_ccplex_gsc, 67 .enter_ccplex_state = ari_enter_ccplex_state, 68 .read_write_uncore_perfmon = ari_read_write_uncore_perfmon, 69 .misc_ccplex = ari_misc_ccplex 70 }; 71 72 typedef struct { 73 uint32_t ari_base; 74 arch_mce_ops_t *ops; 75 } mce_config_t; 76 77 /* Table to hold the per-CPU ARI base address and function handlers */ 78 static mce_config_t mce_cfg_table[MCE_ARI_APERTURES_MAX] = { 79 { 80 /* A57 Core 0 */ 81 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_0_OFFSET, 82 .ops = &ari_mce_ops, 83 }, 84 { 85 /* A57 Core 1 */ 86 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_1_OFFSET, 87 .ops = &ari_mce_ops, 88 }, 89 { 90 /* A57 Core 2 */ 91 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_2_OFFSET, 92 .ops = &ari_mce_ops, 93 }, 94 { 95 /* A57 Core 3 */ 96 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_3_OFFSET, 97 .ops = &ari_mce_ops, 98 }, 99 { 100 /* D15 Core 0 */ 101 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_4_OFFSET, 102 .ops = &nvg_mce_ops, 103 }, 104 { 105 /* D15 Core 1 */ 106 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_5_OFFSET, 107 .ops = &nvg_mce_ops, 108 } 109 }; 110 111 static uint32_t mce_get_curr_cpu_ari_base(void) 112 { 113 uint64_t mpidr = read_mpidr(); 114 uint64_t cpuid = mpidr & (uint64_t)MPIDR_CPU_MASK; 115 uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; 116 117 /* 118 * T186 has 2 CPU clusters, one with Denver CPUs and the other with 119 * ARM CortexA-57 CPUs. Each cluster consists of 4 CPUs and the CPU 120 * numbers start from 0. In order to get the proper arch_mce_ops_t 121 * struct, we have to convert the Denver CPU ids to the corresponding 122 * indices in the mce_ops_table array. 123 */ 124 if (impl == DENVER_IMPL) { 125 cpuid |= 0x4U; 126 } 127 128 return mce_cfg_table[cpuid].ari_base; 129 } 130 131 static arch_mce_ops_t *mce_get_curr_cpu_ops(void) 132 { 133 uint64_t mpidr = read_mpidr(); 134 uint64_t cpuid = mpidr & (uint64_t)MPIDR_CPU_MASK; 135 uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & 136 (uint64_t)MIDR_IMPL_MASK; 137 138 /* 139 * T186 has 2 CPU clusters, one with Denver CPUs and the other with 140 * ARM CortexA-57 CPUs. Each cluster consists of 4 CPUs and the CPU 141 * numbers start from 0. In order to get the proper arch_mce_ops_t 142 * struct, we have to convert the Denver CPU ids to the corresponding 143 * indices in the mce_ops_table array. 144 */ 145 if (impl == DENVER_IMPL) { 146 cpuid |= 0x4U; 147 } 148 149 return mce_cfg_table[cpuid].ops; 150 } 151 152 /******************************************************************************* 153 * Common handler for all MCE commands 154 ******************************************************************************/ 155 int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, 156 uint64_t arg2) 157 { 158 const arch_mce_ops_t *ops; 159 gp_regs_t *gp_regs = get_gpregs_ctx(cm_get_context(NON_SECURE)); 160 uint32_t cpu_ari_base; 161 uint64_t ret64 = 0, arg3, arg4, arg5; 162 int32_t ret = 0; 163 164 assert(gp_regs != NULL); 165 166 /* get a pointer to the CPU's arch_mce_ops_t struct */ 167 ops = mce_get_curr_cpu_ops(); 168 169 /* get the CPU's ARI base address */ 170 cpu_ari_base = mce_get_curr_cpu_ari_base(); 171 172 switch (cmd) { 173 case MCE_CMD_ENTER_CSTATE: 174 ret = ops->enter_cstate(cpu_ari_base, arg0, arg1); 175 176 break; 177 178 case MCE_CMD_UPDATE_CSTATE_INFO: 179 /* 180 * get the parameters required for the update cstate info 181 * command 182 */ 183 arg3 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X4)); 184 arg4 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X5)); 185 arg5 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X6)); 186 187 ret = ops->update_cstate_info(cpu_ari_base, (uint32_t)arg0, 188 (uint32_t)arg1, (uint32_t)arg2, (uint8_t)arg3, 189 (uint32_t)arg4, (uint8_t)arg5); 190 191 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X4), (0)); 192 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X5), (0)); 193 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X6), (0)); 194 195 break; 196 197 case MCE_CMD_UPDATE_CROSSOVER_TIME: 198 ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1); 199 200 break; 201 202 case MCE_CMD_READ_CSTATE_STATS: 203 ret64 = ops->read_cstate_stats(cpu_ari_base, arg0); 204 205 /* update context to return cstate stats value */ 206 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64)); 207 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2), (ret64)); 208 209 break; 210 211 case MCE_CMD_WRITE_CSTATE_STATS: 212 ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1); 213 214 break; 215 216 case MCE_CMD_IS_CCX_ALLOWED: 217 ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1); 218 219 /* update context to return CCx status value */ 220 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), 221 (uint64_t)(ret)); 222 223 break; 224 225 case MCE_CMD_IS_SC7_ALLOWED: 226 ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1); 227 228 /* update context to return SC7 status value */ 229 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), 230 (uint64_t)(ret)); 231 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X3), 232 (uint64_t)(ret)); 233 234 break; 235 236 case MCE_CMD_ONLINE_CORE: 237 ret = ops->online_core(cpu_ari_base, arg0); 238 239 break; 240 241 case MCE_CMD_CC3_CTRL: 242 ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2); 243 244 break; 245 246 case MCE_CMD_ECHO_DATA: 247 ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_ECHO, 248 arg0); 249 250 /* update context to return if echo'd data matched source */ 251 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), 252 ((ret64 == arg0) ? 1ULL : 0ULL)); 253 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2), 254 ((ret64 == arg0) ? 1ULL : 0ULL)); 255 256 break; 257 258 case MCE_CMD_READ_VERSIONS: 259 ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION, 260 arg0); 261 262 /* 263 * version = minor(63:32) | major(31:0). Update context 264 * to return major and minor version number. 265 */ 266 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), 267 (ret64)); 268 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2), 269 (ret64 >> 32ULL)); 270 271 break; 272 273 case MCE_CMD_ENUM_FEATURES: 274 ret64 = ops->call_enum_misc(cpu_ari_base, 275 TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0); 276 277 /* update context to return features value */ 278 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64)); 279 280 break; 281 282 case MCE_CMD_ROC_FLUSH_CACHE_TRBITS: 283 ret = ops->roc_flush_cache_trbits(cpu_ari_base); 284 285 break; 286 287 case MCE_CMD_ROC_FLUSH_CACHE: 288 ret = ops->roc_flush_cache(cpu_ari_base); 289 290 break; 291 292 case MCE_CMD_ROC_CLEAN_CACHE: 293 ret = ops->roc_clean_cache(cpu_ari_base); 294 295 break; 296 297 case MCE_CMD_ENUM_READ_MCA: 298 ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); 299 300 /* update context to return MCA data/error */ 301 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64)); 302 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2), (arg1)); 303 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X3), (ret64)); 304 305 break; 306 307 case MCE_CMD_ENUM_WRITE_MCA: 308 ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); 309 310 /* update context to return MCA error */ 311 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64)); 312 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X3), (ret64)); 313 314 break; 315 316 #if ENABLE_CHIP_VERIFICATION_HARNESS 317 case MCE_CMD_ENABLE_LATIC: 318 /* 319 * This call is not for production use. The constant value, 320 * 0xFFFF0000, is specific to allowing for enabling LATIC on 321 * pre-production parts for the chip verification harness. 322 * 323 * Enabling LATIC allows S/W to read the MINI ISPs in the 324 * CCPLEX. The ISMs are used for various measurements relevant 325 * to particular locations in the Silicon. They are small 326 * counters which can be polled to determine how fast a 327 * particular location in the Silicon is. 328 */ 329 ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(), 330 0xFFFF0000); 331 332 break; 333 #endif 334 335 case MCE_CMD_UNCORE_PERFMON_REQ: 336 ret = ops->read_write_uncore_perfmon(cpu_ari_base, arg0, &arg1); 337 338 /* update context to return data */ 339 write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (arg1)); 340 break; 341 342 case MCE_CMD_MISC_CCPLEX: 343 ops->misc_ccplex(cpu_ari_base, arg0, arg1); 344 345 break; 346 347 default: 348 ERROR("unknown MCE command (%llu)\n", cmd); 349 ret = EINVAL; 350 break; 351 } 352 353 return ret; 354 } 355 356 /******************************************************************************* 357 * Handler to update the reset vector for CPUs 358 ******************************************************************************/ 359 int32_t mce_update_reset_vector(void) 360 { 361 const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); 362 363 ops->update_reset_vector(mce_get_curr_cpu_ari_base()); 364 365 return 0; 366 } 367 368 static int32_t mce_update_ccplex_gsc(tegra_ari_gsc_index_t gsc_idx) 369 { 370 const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); 371 372 ops->update_ccplex_gsc(mce_get_curr_cpu_ari_base(), gsc_idx); 373 374 return 0; 375 } 376 377 /******************************************************************************* 378 * Handler to update carveout values for Video Memory Carveout region 379 ******************************************************************************/ 380 int32_t mce_update_gsc_videomem(void) 381 { 382 return mce_update_ccplex_gsc(TEGRA_ARI_GSC_VPR_IDX); 383 } 384 385 /******************************************************************************* 386 * Handler to update carveout values for TZDRAM aperture 387 ******************************************************************************/ 388 int32_t mce_update_gsc_tzdram(void) 389 { 390 return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZ_DRAM_IDX); 391 } 392 393 /******************************************************************************* 394 * Handler to update carveout values for TZ SysRAM aperture 395 ******************************************************************************/ 396 int32_t mce_update_gsc_tzram(void) 397 { 398 return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZRAM); 399 } 400 401 /******************************************************************************* 402 * Handler to shutdown/reset the entire system 403 ******************************************************************************/ 404 __dead2 void mce_enter_ccplex_state(uint32_t state_idx) 405 { 406 const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); 407 408 /* sanity check state value */ 409 if ((state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) && 410 (state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT)) { 411 panic(); 412 } 413 414 ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(), state_idx); 415 416 /* wait till the CCPLEX powers down */ 417 for (;;) { 418 ; 419 } 420 421 } 422 423 /******************************************************************************* 424 * Handler to issue the UPDATE_CSTATE_INFO request 425 ******************************************************************************/ 426 void mce_update_cstate_info(const mce_cstate_info_t *cstate) 427 { 428 const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); 429 430 /* issue the UPDATE_CSTATE_INFO request */ 431 ops->update_cstate_info(mce_get_curr_cpu_ari_base(), cstate->cluster, 432 cstate->ccplex, cstate->system, cstate->system_state_force, 433 cstate->wake_mask, cstate->update_wake_mask); 434 } 435 436 /******************************************************************************* 437 * Handler to read the MCE firmware version and check if it is compatible 438 * with interface header the BL3-1 was compiled against 439 ******************************************************************************/ 440 void mce_verify_firmware_version(void) 441 { 442 const arch_mce_ops_t *ops; 443 uint32_t cpu_ari_base; 444 uint64_t version; 445 uint32_t major, minor; 446 447 /* 448 * MCE firmware is not supported on simulation platforms. 449 */ 450 if (tegra_platform_is_emulation()) { 451 452 INFO("MCE firmware is not supported\n"); 453 454 } else { 455 /* get a pointer to the CPU's arch_mce_ops_t struct */ 456 ops = mce_get_curr_cpu_ops(); 457 458 /* get the CPU's ARI base address */ 459 cpu_ari_base = mce_get_curr_cpu_ari_base(); 460 461 /* 462 * Read the MCE firmware version and extract the major and minor 463 * version fields 464 */ 465 version = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION, 0); 466 major = (uint32_t)version; 467 minor = (uint32_t)(version >> 32); 468 469 INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor, 470 TEGRA_ARI_VERSION_MAJOR, TEGRA_ARI_VERSION_MINOR); 471 472 /* 473 * Verify that the MCE firmware version and the interface header 474 * match 475 */ 476 if (major != TEGRA_ARI_VERSION_MAJOR) { 477 ERROR("ARI major version mismatch\n"); 478 panic(); 479 } 480 481 if (minor < TEGRA_ARI_VERSION_MINOR) { 482 ERROR("ARI minor version mismatch\n"); 483 panic(); 484 } 485 } 486 } 487