refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos(

refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos() no longer needs to be called
within the driver, helping with performance a bit.

Change-Id: I0b0d1d36d20d67c41c8c9dc14ade11bda6d4a6af
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "hm/evlog" into integration

* changes:
refactor(measured-boot): refine event log lib docs
refactor(fvp): explicitly handle event log errors
feat(measured-boot): make e

Merge changes from topic "hm/evlog" into integration

* changes:
refactor(measured-boot): refine event log lib docs
refactor(fvp): explicitly handle event log errors
feat(measured-boot): make event log lib standalone

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Merge "fix(versal-net): enable PSCI reset2 interface" into integration

refactor(gic): promote most of the GIC driver to common code

More often than not, Arm based systems include some revision of a GIC.
There are two ways of adding support for them in platform code - c

refactor(gic): promote most of the GIC driver to common code

More often than not, Arm based systems include some revision of a GIC.
There are two ways of adding support for them in platform code - calling
the top-level helpers from plat/arm/common/arm_gicvX.c or by using the
driver directly. Both of these methods allow for a high degree of
customisation - most functions are defined to be weak and there are no
calls to any of them in generic code.

As it turns out, requirements around those GICs are largely the same.
Platforms that use arm_gicvX.c use the helpers identically among each
other. Platforms that use the driver directly tend to end up with calls
that look a lot like the arm_gicvX.c helpers and the weakness of the
functions are never exercised.

All of this results in a lot of code duplication to do what is
essentially the same thing. Even though it's not a lot of code, when
multiplied among many platforms it becomes significant and makes
refactoring it quite difficult. It's also bug prone since the steps are
a little convoluted and things are likely to work even with subtle
errors (see 50009f61177421118f42d6a000611ba0e613d54b).

So promote as much of the GIC to be called from common code. Do the
setup in bl31_main() and have every PSCI method do the state management
directly instead of delegating it to the platform hooks. We can base
this implementation on arm_gicvX.c since they already offer logical
names and have worked quite well so far with minimal changes.

The main benefit of doing this is reduced code duplication. If we assume
that, outside of some platform setup, GIC management is identical, then
a platform can add support by telling the build system, regardless of
GIC revision. The other benefit is performance - BL31 and PSCI already
know the core_pos and they can pass it as an argument instead of having
to call plat_my_core_pos(). Now, the only platform specific GIC actions
necessary are the saving and restoring of context on entering and
exiting a power domain. The PSCI library does not keep track of this so
it is unable perform it itself. The routines themselves are also
provided.

For compatibility all of this is hidden behind a build flag. Platforms
are encouraged to adopt this driver, but it would not be practical to
convert and validate every GIC based platform.

This patch renames the functions in question to follow the
gic_<function>() convention. This allows the names to be version
agnostic.

Finally, drop the weak definitions - they are unused, likely to remain
so, and can be added back if the need arises.

Change-Id: I5b5267f4b72f633fb1096400ec8e4b208694135f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor: make arm_gicv2.c and arm_gicv3.c common

These files were meant to be platform specific, but they are generic
enough that a range of platforms find them useful. However, refactoring
them is

refactor: make arm_gicv2.c and arm_gicv3.c common

These files were meant to be platform specific, but they are generic
enough that a range of platforms find them useful. However, refactoring
them is difficult as their use is platform specific. So copy them to a
generic place and redirect platforms to them.

The new copies will remain for compatibility for platforms that don't
want to or can't take up upcoming refactors and the old copies can be
drastically refactored to make them more widely applicable.

Change-Id: I056c8710cdda4d8a81b324d392762c29e02cdae1
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(fvp): use more arm generic code for gicv3

The arm generic implementation for the GIC is quite comprehensive and
the fvp's requirements don't diverge too much. Despite that, they
completely

refactor(fvp): use more arm generic code for gicv3

The arm generic implementation for the GIC is quite comprehensive and
the fvp's requirements don't diverge too much. Despite that, they
completely override a lot of code that is effectively reused. Use the
generic implementation instead to make it easier to follow and override
as little code as possible.

Change-Id: I3474aa970d7fbb91d75c0be6a255bc0da734f860
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes Id942c20c,Idd286bea,I8917a26e,Iec8c3477,If3c25dcd, ... into integration

* changes:
feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED
perf(cpufeat): centralise PAuth key saving

Merge changes Id942c20c,Idd286bea,I8917a26e,Iec8c3477,If3c25dcd, ... into integration

* changes:
feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED
perf(cpufeat): centralise PAuth key saving
refactor(cpufeat): convert FEAT_PAuth setup to C
refactor(cpufeat): prepare FEAT_PAuth for FEATURE_DETECTION
chore(cpufeat): remove PAuth presence checks
feat(cpufeat): enable FEAT_BTI to FEAT_STATE_CHECKED

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feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED

FEAT_PAuth is the second to last feature to be a boolean choice - it's
either unconditionally compiled in and must be present in hardware or
it

feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED

FEAT_PAuth is the second to last feature to be a boolean choice - it's
either unconditionally compiled in and must be present in hardware or
it's not compiled in. FEAT_PAuth is architected to be backwards
compatible - a subset of the branch guarding instructions (pacia/autia)
execute as NOPs when PAuth is not present. That subset is used with
`-mbranch-protection=standard` and -march pre-8.3. This patch adds the
necessary logic to also check accesses of the non-backward compatible
registers and allow a fully checked implementation.

Note that a checked support requires -march to be pre 8.3, as otherwise
the compiler will include branch protection instructions that are not
NOPs without PAuth (eg retaa) which cannot be checked.

Change-Id: Id942c20cae9d15d25b3d72b8161333642574ddaa
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(rd1ae): rename legacy MPAM build option" into integration

Merge changes from topic "sm/rpkm" into integration

* changes:
docs(rmmd): document the EL3-RMM IDE KM Interface
feat(trp): test el3-rmm ide km interface
feat(rmmd): el3-rmm ide key management

Merge changes from topic "sm/rpkm" into integration

* changes:
docs(rmmd): document the EL3-RMM IDE KM Interface
feat(trp): test el3-rmm ide km interface
feat(rmmd): el3-rmm ide key management interface

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refactor(fvp): explicitly handle event log errors

Following the patch that introduced errno returns in the event log APIs,
ensure that errors are properly handled within FVP instead of being
ignored

refactor(fvp): explicitly handle event log errors

Following the patch that introduced errno returns in the event log APIs,
ensure that errors are properly handled within FVP instead of being
ignored.

Change-Id: I5e736b81d9a17ff10dbab6e65bc6506b71c7c9bd
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(xilinx): resolve misra rule 2.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.2.3:
- A project should not contain unused type declarations.
- Fix:
- Removed unuse

fix(xilinx): resolve misra rule 2.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.2.3:
- A project should not contain unused type declarations.
- Fix:
- Removed unused code.

Change-Id: Ica5982fe83485da79ac18d45b44e66f5f37fb6e7
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 2.7 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.2.7:
- There should be no unused parameters in functions.
- Fix:
- Type casted unuse

fix(xilinx): resolve misra rule 2.7 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.2.7:
- There should be no unused parameters in functions.
- Fix:
- Type casted unused parameters to void.

Change-Id: I940109631dbabfbd960c1bc7b183cf865ff312c9
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 8.6 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.6:
- An identifier with external linkage shall have exactly one external
definit

fix(xilinx): resolve misra rule 8.6 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.6:
- An identifier with external linkage shall have exactly one external
definition.
- Fix:
- Removed redundant function declarations since it is not defined.

Change-Id: If003efbfa08ee6ff4f545605ef34dfd16f33b664
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 11.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.11.3:
- A cast shall not be performed between a pointer to object type and a
poin

fix(xilinx): resolve misra rule 11.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.11.3:
- A cast shall not be performed between a pointer to object type and a
pointer to a different object type.
- Fix:
- Removed unnecessary cast of pointers.

Change-Id: Iba5dbec0784dcaa86e3a00bd213cbc2711d12029
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 2.2 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.2.2:
- There shall be no dead code.
- Fix:
- Moved code to macro protected section.

fix(xilinx): resolve misra rule 2.2 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.2.2:
- There shall be no dead code.
- Fix:
- Moved code to macro protected section.

Change-Id: I58b340aa452b67ba765dfe33ff7eb64a4eac8624
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 15.7 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.15.7:
- All if...else if constructs shall be terminated with an else statement.
- Fix

fix(xilinx): resolve misra rule 15.7 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.15.7:
- All if...else if constructs shall be terminated with an else statement.
- Fix:
- Convert the final else if into an else statement to comply with
MISRA guidelines

Change-Id: I1f54d955958538529a10f146a506ce2a3474f8d7
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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chore(tc): remove TC2 platform variant

Remove TC2 platform support which was deprecated in the last release.

Change-Id: Ibf4a94a0168151ebc66eaca044a143c51e974a1f
Signed-off-by: Manish V Badarkhe <M

chore(tc): remove TC2 platform variant

Remove TC2 platform support which was deprecated in the last release.

Change-Id: Ibf4a94a0168151ebc66eaca044a143c51e974a1f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "xlnx_versal2_ipi" into integration

* changes:
feat(versal2): add bufferless IPI Support
chore(versal2): use BIT_32() macro

Merge changes from topic "hm/handoff-aarch32" into integration

* changes:
feat(fvp): support AArch32 booting with handoff
feat(arm): support AArch32 booting with handoff

fix(rd1ae): rename legacy MPAM build option

ENABLE_MPAM_FOR_LOWER_ELS was renamed to ENABLE_FEAT_MPAM a while ago,
but the rd1ae platform Makefile still carries the old name, probably due
to the ups

fix(rd1ae): rename legacy MPAM build option

ENABLE_MPAM_FOR_LOWER_ELS was renamed to ENABLE_FEAT_MPAM a while ago,
but the rd1ae platform Makefile still carries the old name, probably due
to the upstreaming overlapping with the rename.

Replace the old build option with the proper name, to make sure that
MPAM support gets compiled in without runtime checks.

Change-Id: If082e7250a7a3d12c7cbef5126303da1ee07a3af
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(versal2): enable system reset" into integration

Merge "feat(psci): remove cpu context init by index" into integration

refactor(s32g274a): replace mov/movk with mov_imm

Replace pairs of mov and movk instructions with the mov_imm macro to
align with the rest of the infrastructure and avoid code duplication.

Change-I

refactor(s32g274a): replace mov/movk with mov_imm

Replace pairs of mov and movk instructions with the mov_imm macro to
align with the rest of the infrastructure and avoid code duplication.

Change-Id: I3c091eb8ff111c7bc030b32ad5948cbfaea3b35c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(psci): remove cpu context init by index

Currently, the calling core (meaning the core which received the call to
CPU_ON or the powerdown path of CPU_SUSPEND on the same core) is in
charge of in

feat(psci): remove cpu context init by index

Currently, the calling core (meaning the core which received the call to
CPU_ON or the powerdown path of CPU_SUSPEND on the same core) is in
charge of initialising the context for the waking core (the warmboot
entrypoint for both). This is convenient because the calling core can
write the context while in coherency and the waking core will only need
the context after its entered coherency. This avoids any cache
maintenance and makes communication simple.

However, this has 3 main problems:
a) asymmetric feature support is problematic - the calling core has no
way of knowing the feature set of the waking core. If the two
diverge, the architectural feature discovery via ID registers breaks
down. We've thus far "fixed" this on a case by case basis which
doesn't scale and introduces redundancy.

b) powerdown abandon (pabandon) introduces a contradiction - the calling
core has to initialise the context for when the core wakes up, but
should the core not powerdown it needs its old context intact. The only
way to work around this is by keeping two copies of context which
incurs a runtime and memory overhead.

c) cm_prepare_el3_exit[_ns]() doesn't have access to the entrypoint but needs
it to make initialisation decisions. We can infer some of this from
registers that have already been written but this is awkwardly
limiting for what we can do. This also necessitates the split from
the context initialisation.

We can solve all three by a making a core be in full ownership of its
own context. The calling core then only writes entrypoint information
and nothing else. The waking core then initialises its own context as it
sees fit with full knowledge of the whole picture.

The only tricky bit is cache coherency - the waking core has to be able
to coherently observe its new entrypoint. Calling cores will write to
the shared region with coherent caches on. If we make sure to read the
context only after the waking core has entered coherency, then we can
avoid cache operations and let hardware handle everything.

We can skip the spsr check for FEAT_TCR2 as it doesn't make a
difference. We can also skip enabling it twice from generic code.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I86e7fe8b698191fc3b469e5ced1fd010f8754b0e

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