rockchip: Streamline and complete UARTn_BASE macros.

In order to set the UART base during bootup in common code of
plat/rockchip, we need to streamline the way the UART base addresses
are defined an

rockchip: Streamline and complete UARTn_BASE macros.

In order to set the UART base during bootup in common code of
plat/rockchip, we need to streamline the way the UART base addresses
are defined and add the missing definitions and mappings.

This patch does so by following the pattern UARTn_BASE, which is
already in use on RK3399 and RK3328. The numbering itself is derived
from the upstream Linux DTS files of the individual SoCs.

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: I341a1996f4ceed5f82a2f6687d4dead9d7cc5c1f

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Merge "ti: k3: common: Remove MSMC port definitions" into integration

Merge changes from topic "lm/stack_protector" into integration

* changes:
juno: Add security sources for tsp-juno
Add support for default stack-protector flag

juno: Add security sources for tsp-juno

Security sources are required if stack-protector is enabled.

Change-Id: Ia0071f60cf03d48b200fd1facbe50bd9e2f8f282
Signed-off-by: Louis Mayencourt <louis.maye

juno: Add security sources for tsp-juno

Security sources are required if stack-protector is enabled.

Change-Id: Ia0071f60cf03d48b200fd1facbe50bd9e2f8f282
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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ti: k3: common: Remove MSMC port definitions

The MSMC port defines were added to help in the case when some ports
are not connected and have no cores attached. We can get the same
functionality by d

ti: k3: common: Remove MSMC port definitions

The MSMC port defines were added to help in the case when some ports
are not connected and have no cores attached. We can get the same
functionality by defined the number of cores on that port to zero.
This simplifies several code paths, do this here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I3247fe37af7b86c3227e647b4f617fab70c8ee8a

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Merge "rockchip: only include libfdt in non-coreboot cases" into integration

Merge "hikey: Add define for UART2" into integration

Merge changes from topic "k3-coherency" into integration

* changes:
ti: k3: common: Mark sections for AM65x coherency workaround
ti: k3: common: Allow USE_COHERENT_MEM for K3
ti: k3: common: F

Merge changes from topic "k3-coherency" into integration

* changes:
ti: k3: common: Mark sections for AM65x coherency workaround
ti: k3: common: Allow USE_COHERENT_MEM for K3
ti: k3: common: Fix RO data area size calculation
ti: k3: common: Remove unused STUB macro

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Merge "plat: allwinner: common: use r_wdog instead of wdog" into integration

Merge changes Ie7766e80,Ia74dbc36 into integration

* changes:
plat: marvell: do not rely on argument passed via smc
plat: marvell: sip: make sure that comphy init will use correct address

rockchip: only include libfdt in non-coreboot cases

While mainline u-boot always expects to submit the devicetree
as platform param, coreboot always uses the existing parameter
structure. As libfdt

rockchip: only include libfdt in non-coreboot cases

While mainline u-boot always expects to submit the devicetree
as platform param, coreboot always uses the existing parameter
structure. As libfdt is somewhat big, it makes sense to limit
its inclusion to where necessary and thus only to non-coreboot
builds.

libfdt itself will get build in all cases, but only the non-
coreboot build will actually reference and thus include it.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I4c5bc28405a14e6070917e48a526bfe77bab2fb7

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ti: k3: common: Mark sections for AM65x coherency workaround

These sections of code are only needed for the coherency workaround
used for AM65x, if this workaround is not needed then this code
is no

ti: k3: common: Mark sections for AM65x coherency workaround

These sections of code are only needed for the coherency workaround
used for AM65x, if this workaround is not needed then this code
is not either. Mark it off to keep it separated from the rest of
the PSCI implementation.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I113ca6a2a1f7881814ab0a64e5bac57139bc03ef

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ti: k3: common: Allow USE_COHERENT_MEM for K3

To make the USE_COHERENT_MEM option work we need to add an entry for the
area to our memory map table. Also fixup the alignment here.

Signed-off-by: An

ti: k3: common: Allow USE_COHERENT_MEM for K3

To make the USE_COHERENT_MEM option work we need to add an entry for the
area to our memory map table. Also fixup the alignment here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I1c05477a97646ac73846a711bc38d3746628d847

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ti: k3: common: Fix RO data area size calculation

The size of the RO data area was calculated by subtracting the area end
address from itself and not the base address due to a typo. Fix this
here.

ti: k3: common: Fix RO data area size calculation

The size of the RO data area was calculated by subtracting the area end
address from itself and not the base address due to a typo. Fix this
here.

Note, this was noticed at a glance thanks to the new aligned formating
of this table.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I994022ac9fc95dc5e37a420714da76081c61cce7

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ti: k3: common: Remove unused STUB macro

This macro was used when many of these functions were stubbed out,
the macro is not used anymore, remove it.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Cha

ti: k3: common: Remove unused STUB macro

This macro was used when many of these functions were stubbed out,
the macro is not used anymore, remove it.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ida33f92fe3810a89e6e51faf6e93c1d2ada1a2ee

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hikey: Add define for UART2

Change-Id: I54869151bfc434df66933bd418c70cca9c3d0861
Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>

Merge "rk3399: m0: Fix compiler warnings." into integration

rockchip: add support for rk3288

The rk3288 is a 4-core Cortex-A12 SoC and shares a lot of features
with later SoCs.

Working features are general non-secure mode (the gic needs special
love for tha

rockchip: add support for rk3288

The rk3288 is a 4-core Cortex-A12 SoC and shares a lot of features
with later SoCs.

Working features are general non-secure mode (the gic needs special
love for that), psci-based smp bringing cpu cores online and also
taking them offline again, psci-based suspend (the simpler variant
also included in the linux kernel, deeper suspend following later)
and I was also already able to test HYP-mode and was able to boot
a virtual kernel using kvm.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ibaaa583b2e78197591a91d254339706fe732476a

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rockchip: add common aarch32 support

There are a number or ARMv7 Rockchip SoCs that are very similar in their
bringup routines to the existing arm64 SoCs, so there is quite a high
commonality possib

rockchip: add common aarch32 support

There are a number or ARMv7 Rockchip SoCs that are very similar in their
bringup routines to the existing arm64 SoCs, so there is quite a high
commonality possible here.

Things like virtualization also need psci and hyp-mode and instead of
trying to cram this into bootloaders like u-boot, barebox or coreboot
(all used in the field), re-use the existing infrastructure in TF-A
for this (both Rockchip plat support and armv7 support in general).

So add core support for aarch32 Rockchip SoCs, with actual soc support
following in a separate patch.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I298453985b5d8434934fc0c742fda719e994ba0b

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rockchip: rk3328: drop double declaration of entry_point storage

The cpuson_entry_point and cpuson_flags are already declared in
plat_private.h so there is no need to have it again declared in
the l

rockchip: rk3328: drop double declaration of entry_point storage

The cpuson_entry_point and cpuson_flags are already declared in
plat_private.h so there is no need to have it again declared in
the local pmu.h, especially as it may cause conflicts when the
other type changes.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I80ae0e23d22f67109ed96f8ac059973b6de2ce87

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rockchip: Allow socs with undefined wfe check bits

Some older socs like the rk3288 do not have the necessary registers
to check the wfi/wfe state of the cpu cores. Allow this case an "just"
do an ad

rockchip: Allow socs with undefined wfe check bits

Some older socs like the rk3288 do not have the necessary registers
to check the wfi/wfe state of the cpu cores. Allow this case an "just"
do an additional delay similar to how the Linux kernel handles smp
right now.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I0f67af388b06b8bfb4a9bac411b4900ac266a77a

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rockchip: move pmusram assembler code to a aarch64 subdir

The current code doing power-management from sram is highly
arm64-specific so should live in a corresponding subdirectory
and not in the com

rockchip: move pmusram assembler code to a aarch64 subdir

The current code doing power-management from sram is highly
arm64-specific so should live in a corresponding subdirectory
and not in the common area.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I3b79ac26f70fd189d4d930faa6251439a644c5d9

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rk3399: m0: Fix compiler warnings.

GCC complains for quite some versions, when compiling the M0 firmware
for Rockchip's rk3399 platform, about an invalid type of function 'main':

warning: return

rk3399: m0: Fix compiler warnings.

GCC complains for quite some versions, when compiling the M0 firmware
for Rockchip's rk3399 platform, about an invalid type of function 'main':

warning: return type of 'main' is not 'int' [-Wmain]

This patch addresses this, by renaming the function to 'm0_main'.

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: I10887f2bda6bdb48c5017044c264139004f7c785

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Merge changes from topic "av/console-register" into integration

* changes:
Console: Remove Arm console unregister on suspend
Console: Allow to register multiple times

Merge changes from topic "k3-sequence-fix" into integration

* changes:
ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID
ti: k3: drivers: ti_sci: Cleanup sequence ID usage
ti:

Merge changes from topic "k3-sequence-fix" into integration

* changes:
ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID
ti: k3: drivers: ti_sci: Cleanup sequence ID usage
ti: k3: drivers: sec_proxy: Use direction definitions
ti: k3: drivers: sec_proxy: Fix printf format specifiers

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