xref: /rk3399_ARM-atf/plat/ti/k3/common/k3_psci.c (revision 282514cff332090852e52bc7c56fdea53c1f7218)
1 /*
2  * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <stdbool.h>
9 
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <lib/el3_runtime/cpu_data.h>
13 #include <lib/psci/psci.h>
14 #include <plat/common/platform.h>
15 
16 #include <ti_sci_protocol.h>
17 #include <k3_gicv3.h>
18 #include <ti_sci.h>
19 
20 /* Need to flush psci internal locks before shutdown or their values are lost */
21 #include "../../../../lib/psci/psci_private.h"
22 
23 uintptr_t k3_sec_entrypoint;
24 
25 static void k3_cpu_standby(plat_local_state_t cpu_state)
26 {
27 	unsigned int scr;
28 
29 	scr = read_scr_el3();
30 	/* Enable the Non secure interrupt to wake the CPU */
31 	write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
32 	isb();
33 	/* dsb is good practice before using wfi to enter low power states */
34 	dsb();
35 	/* Enter standby state */
36 	wfi();
37 	/* Restore SCR */
38 	write_scr_el3(scr);
39 }
40 
41 static int k3_pwr_domain_on(u_register_t mpidr)
42 {
43 	int core_id, proc, device, ret;
44 
45 	core_id = plat_core_pos_by_mpidr(mpidr);
46 	if (core_id < 0) {
47 		ERROR("Could not get target core id: %d\n", core_id);
48 		return PSCI_E_INTERN_FAIL;
49 	}
50 
51 	proc = PLAT_PROC_START_ID + core_id;
52 	device = PLAT_PROC_DEVICE_START_ID + core_id;
53 
54 	ret = ti_sci_proc_request(proc);
55 	if (ret) {
56 		ERROR("Request for processor failed: %d\n", ret);
57 		return PSCI_E_INTERN_FAIL;
58 	}
59 
60 	ret = ti_sci_proc_set_boot_cfg(proc, k3_sec_entrypoint, 0, 0);
61 	if (ret) {
62 		ERROR("Request to set core boot address failed: %d\n", ret);
63 		return PSCI_E_INTERN_FAIL;
64 	}
65 
66 	ret = ti_sci_device_get(device);
67 	if (ret) {
68 		ERROR("Request to start core failed: %d\n", ret);
69 		return PSCI_E_INTERN_FAIL;
70 	}
71 
72 	return PSCI_E_SUCCESS;
73 }
74 
75 void k3_pwr_domain_off(const psci_power_state_t *target_state)
76 {
77 	int core_id, proc, device, ret;
78 
79 	/* Prevent interrupts from spuriously waking up this cpu */
80 	k3_gic_cpuif_disable();
81 
82 	core_id = plat_my_core_pos();
83 	proc = PLAT_PROC_START_ID + core_id;
84 	device = PLAT_PROC_DEVICE_START_ID + core_id;
85 
86 	/* Start by sending wait for WFI command */
87 	ret = ti_sci_proc_wait_boot_status_no_wait(proc,
88 			/*
89 			 * Wait maximum time to give us the best chance to get
90 			 * to WFI before this command timeouts
91 			 */
92 			UINT8_MAX, 100, UINT8_MAX, UINT8_MAX,
93 			/* Wait for WFI */
94 			PROC_BOOT_STATUS_FLAG_ARMV8_WFI, 0, 0, 0);
95 	if (ret) {
96 		ERROR("Sending wait for WFI failed (%d)\n", ret);
97 		return;
98 	}
99 
100 	/* Now queue up the core shutdown request */
101 	ret = ti_sci_device_put_no_wait(device);
102 	if (ret) {
103 		ERROR("Sending core shutdown message failed (%d)\n", ret);
104 		return;
105 	}
106 }
107 
108 void k3_pwr_domain_on_finish(const psci_power_state_t *target_state)
109 {
110 	/* TODO: Indicate to System firmware about completion */
111 
112 	k3_gic_pcpu_init();
113 	k3_gic_cpuif_enable();
114 }
115 
116 static void  __dead2 k3_pwr_domain_pwr_down_wfi(const psci_power_state_t
117 						  *target_state)
118 {
119 	flush_cpu_data(psci_svc_cpu_data);
120 	flush_dcache_range((uintptr_t) psci_locks, sizeof(psci_locks));
121 	psci_power_down_wfi();
122 }
123 
124 static void __dead2 k3_system_reset(void)
125 {
126 	/* Send the system reset request to system firmware */
127 	ti_sci_core_reboot();
128 
129 	while (true)
130 		wfi();
131 }
132 
133 static int k3_validate_power_state(unsigned int power_state,
134 				   psci_power_state_t *req_state)
135 {
136 	/* TODO: perform the proper validation */
137 
138 	return PSCI_E_SUCCESS;
139 }
140 
141 static int k3_validate_ns_entrypoint(uintptr_t entrypoint)
142 {
143 	/* TODO: perform the proper validation */
144 
145 	return PSCI_E_SUCCESS;
146 }
147 
148 static const plat_psci_ops_t k3_plat_psci_ops = {
149 	.cpu_standby = k3_cpu_standby,
150 	.pwr_domain_on = k3_pwr_domain_on,
151 	.pwr_domain_off = k3_pwr_domain_off,
152 	.pwr_domain_on_finish = k3_pwr_domain_on_finish,
153 	.pwr_domain_pwr_down_wfi = k3_pwr_domain_pwr_down_wfi,
154 	.system_reset = k3_system_reset,
155 	.validate_power_state = k3_validate_power_state,
156 	.validate_ns_entrypoint = k3_validate_ns_entrypoint
157 };
158 
159 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
160 			const plat_psci_ops_t **psci_ops)
161 {
162 	k3_sec_entrypoint = sec_entrypoint;
163 
164 	*psci_ops = &k3_plat_psci_ops;
165 
166 	return 0;
167 }
168