History log of /rk3399_ARM-atf/plat/ (Results 6326 – 6350 of 8950)
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4129340726-Jul-2019 Soby Mathew <soby.mathew@arm.com>

Merge changes from topic "advk-serror" into integration

* changes:
marvell/a3700: Prevent SError accessing PCIe link while it is down
marvell: Switch to xlat_tables_v2

df7a906f26-Jul-2019 Soby Mathew <soby.mathew@arm.com>

Merge changes from topic "jun-add-imx7-pico" into integration

* changes:
plat: imx7: Add PicoPi iMX7D basic support
plat: imx7: refactor code for reuse

8612643925-Jul-2019 Soby Mathew <soby.mathew@arm.com>

Merge changes from topic "gby/cryptocell-multi-vers" into integration

* changes:
cryptocell: add product version awareness support
cryptocell: move Cryptocell specific API into driver


/rk3399_ARM-atf/bl1/aarch32/bl1_context_mgmt.c
/rk3399_ARM-atf/bl1/aarch64/bl1_context_mgmt.c
/rk3399_ARM-atf/docs/components/romlib-design.rst
/rk3399_ARM-atf/drivers/auth/cryptocell/712/cryptocell_crypto.c
/rk3399_ARM-atf/drivers/auth/cryptocell/712/cryptocell_plat_helpers.c
/rk3399_ARM-atf/drivers/auth/cryptocell/cryptocell_crypto.mk
/rk3399_ARM-atf/include/arch/aarch32/arch.h
/rk3399_ARM-atf/include/arch/aarch64/arch.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/cc_pal_types.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/cc_sec_defs.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/crypto_driver.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/nvm.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/nvm_otp.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/rsa.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/sbrom_bsv_api.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/secureboot_base_func.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/712/util.h
/rk3399_ARM-atf/include/drivers/arm/cryptocell/cc_rotpk.h
/rk3399_ARM-atf/lib/romlib/Makefile
/rk3399_ARM-atf/lib/romlib/romlib_generator.py
/rk3399_ARM-atf/lib/romlib/templates/jmptbl_entry_function.S
/rk3399_ARM-atf/lib/romlib/templates/jmptbl_entry_function_bti.S
/rk3399_ARM-atf/lib/romlib/templates/jmptbl_entry_reserved.S
/rk3399_ARM-atf/lib/romlib/templates/jmptbl_entry_reserved_bti.S
/rk3399_ARM-atf/lib/romlib/templates/jmptbl_glob_var.S
/rk3399_ARM-atf/lib/romlib/templates/jmptbl_header.S
/rk3399_ARM-atf/lib/romlib/templates/wrapper.S
/rk3399_ARM-atf/lib/romlib/templates/wrapper_bti.S
arm/board/common/board_arm_trusted_boot.c
8a079e8825-Jul-2019 Ambroise Vincent <ambroise.vincent@arm.com>

rockchip: px30: Fix build error

"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"

This is treated as an error since commit 93c690eba8ca ("Ena

rockchip: px30: Fix build error

"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"

This is treated as an error since commit 93c690eba8ca ("Enable
-Wshift-overflow=2 to check for undefined shift behavior")

Only the actual errors are being tackled by this patch. It is up to the
platform to choose whether there needs to be further modifications to
the code.

Change-Id: I70860ae5f2a34d7c684bd491b76da50aa04f778e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

show more ...

425ace7d22-Jul-2019 Madhukar Pappireddy <madhukar.pappireddy@arm.com>

sgm775: Fix build fail for TSP support on sgm775

Fixed the path to a source file specified in tsp makefile
Created a platform specific tsp makefile

Change-Id: I89565127c67eff510e48e21fd450af4c3088c

sgm775: Fix build fail for TSP support on sgm775

Fixed the path to a source file specified in tsp makefile
Created a platform specific tsp makefile

Change-Id: I89565127c67eff510e48e21fd450af4c3088c2d4
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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36ec2bb014-May-2019 Gilad Ben-Yossef <gilad.benyossef@arm.com>

cryptocell: move Cryptocell specific API into driver

Code using Cryptocell specific APIs was used as part of the
arm common board ROT support, instead of being abstracted
in Cryptocell specific driv

cryptocell: move Cryptocell specific API into driver

Code using Cryptocell specific APIs was used as part of the
arm common board ROT support, instead of being abstracted
in Cryptocell specific driver code, creating two problems:
- Any none arm board that uses Cryptocell wuld need to
copy and paste the same code.
- Inability to cleanly support multiple versions of Cryptocell
API and products.

Move over Cryptocell specific API calls into the Cryptocell
driver, creating abstraction API where needed.

Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I9e03ddce90fcc47cfdc747098bece86dbd11c58e

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d38613df25-Jul-2019 Soby Mathew <soby.mathew@arm.com>

Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration

* changes:
plat/mediatek/mt81*: Use new bl31_params_parse() helper
plat/rockchip: Use new bl31_params_parse_

Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration

* changes:
plat/mediatek/mt81*: Use new bl31_params_parse() helper
plat/rockchip: Use new bl31_params_parse_helper()
Add helper to parse BL31 parameters (both versions)
Factor out cross-BL API into export headers suitable for 3rd party code
Use explicit-width data types in AAPCS parameter structs
plat/rockchip: Switch to use new common BL aux parameter library
Introduce lightweight BL platform parameter library

show more ...

cbdc72b531-May-2019 Julius Werner <jwerner@chromium.org>

plat/mediatek/mt81*: Use new bl31_params_parse() helper

The Mediatek MT8173/MT8183 SoCs are prime candidates for switching to
the new bl31_params_parse() helper, so switch them over. This will allow

plat/mediatek/mt81*: Use new bl31_params_parse() helper

The Mediatek MT8173/MT8183 SoCs are prime candidates for switching to
the new bl31_params_parse() helper, so switch them over. This will allow
BL2 implementations on these platforms to transparently switch over to
the version 2 parameter structure.

Change-Id: I0d17ba6c455102d325a06503d2078a76d12b5deb
Signed-off-by: Julius Werner <jwerner@chromium.org>

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3e02c74330-May-2019 Julius Werner <jwerner@chromium.org>

plat/rockchip: Use new bl31_params_parse_helper()

The Rockchip platform is a prime candidate for switching to the new
bl31_params_parse_helper(), so switch it over. This will allow BL2
implementatio

plat/rockchip: Use new bl31_params_parse_helper()

The Rockchip platform is a prime candidate for switching to the new
bl31_params_parse_helper(), so switch it over. This will allow BL2
implementations on this platform to transparently switch over to the
version 2 parameter structure.

Change-Id: I540741d2425c93f66c8697ce749a351eb2b3a7e8
Signed-off-by: Julius Werner <jwerner@chromium.org>

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8b6394c924-Jul-2019 Soby Mathew <soby.mathew@arm.com>

Merge "plat: imx8m: Add basic rdc module init driver" into integration

0cc1e68a24-Jul-2019 Soby Mathew <soby.mathew@arm.com>

Merge "rockchip: px30: support px30" into integration

3bd24e7223-Jul-2019 Ambroise Vincent <ambroise.vincent@arm.com>

intel: agilex: Fix build error

"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"

This is treated as an error since commit 93c690eba8ca ("Enab

intel: agilex: Fix build error

"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"

This is treated as an error since commit 93c690eba8ca ("Enable
-Wshift-overflow=2 to check for undefined shift behavior")

Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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57bf605729-May-2019 Julius Werner <jwerner@chromium.org>

Factor out cross-BL API into export headers suitable for 3rd party code

This patch adds a new include/export/ directory meant for inclusion in
third-party code. This is useful for cases where third-

Factor out cross-BL API into export headers suitable for 3rd party code

This patch adds a new include/export/ directory meant for inclusion in
third-party code. This is useful for cases where third-party code needs
to interact with TF-A interfaces and data structures (such as a custom
BL2-implementation like coreboot handing off to BL31). Directly
including headers from the TF-A repository avoids having to duplicate
all these definitions (and risk them going stale), but with the current
header structure this is not possible because handoff API definitions
are too deeply intertwined with other TF code/headers and chain-include
other headers that will not be available in the other environment.

The new approach aims to solve this by separating only the parts that
are really needed into these special headers that are self-contained and
will not chain-include other (non-export) headers. TF-A code should
never include them directly but should instead always include the
respective wrapper header, which will include the required prerequisites
(like <stdint.h>) before including the export header. Third-party code
can include the export headers via its own wrappers that make sure the
necessary definitions are available in whatever way that environment can
provide them.

Change-Id: Ifd769320ba51371439a8e5dd5b79c2516c3b43ab
Signed-off-by: Julius Werner <jwerner@chromium.org>

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9352be8824-Jul-2019 Julius Werner <jwerner@chromium.org>

Use explicit-width data types in AAPCS parameter structs

It's not a good idea to use u_register_t for the members of
aapcs64_params_t and aapcs32_params_t, since the width of that type
always depend

Use explicit-width data types in AAPCS parameter structs

It's not a good idea to use u_register_t for the members of
aapcs64_params_t and aapcs32_params_t, since the width of that type
always depends on the current execution environment. This would cause
problems if e.g. we used this structure to set up the entry point of an
AArch32 program from within an AArch64 program. (It doesn't seem like
any code is doing that today, but it's probably still a good idea to
write this defensively. Also, it helps with my next patch.)

Change-Id: I12c04a85611f2b6702589f3362bea3e6a7c9f776
Signed-off-by: Julius Werner <jwerner@chromium.org>

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c1185ffd25-May-2019 Julius Werner <jwerner@chromium.org>

plat/rockchip: Switch to use new common BL aux parameter library

This patch changes all Rockchip platforms to use the new common BL aux
parameter helpers. Since the parameter space is now cleanly sp

plat/rockchip: Switch to use new common BL aux parameter library

This patch changes all Rockchip platforms to use the new common BL aux
parameter helpers. Since the parameter space is now cleanly split in
generic and vendor-specific parameters and the COREBOOT_TABLE
parameter is now generic, the parameter type number for that parameter
has to change. Since it only affects coreboot which always builds TF as
a submodule and includes its headers directly to get these constants,
this should not cause any issues. In general, after this point, we
should avoid changing already assigned parameter type numbers whenever
possible.

Change-Id: Ic99ddd1e91ff5e5fe212fa30c793a0b8394c9dad
Signed-off-by: Julius Werner <jwerner@chromium.org>

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3d66079918-Jul-2019 Jacky Bai <ping.bai@nxp.com>

plat: imx8m: Add basic rdc module init driver

Add the basic support for RDC init/config driver,
this module driver can be enhanced more if necessary.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Cha

plat: imx8m: Add basic rdc module init driver

Add the basic support for RDC init/config driver,
this module driver can be enhanced more if necessary.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I290dc378d0d85671435f9de46d5aa790b4e006c8

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6ef6157e23-Jul-2019 Soby Mathew <soby.mathew@arm.com>

Merge "n1sdp: fix DMC ECC enablement sequence in N1SDP platform" into integration

4dc74ca323-Jul-2019 Soby Mathew <soby.mathew@arm.com>

Merge "arm: Shorten the Firmware Update (FWU) process" into integration

7428bbf422-Jul-2019 Manoj Kumar <manoj.kumar3@arm.com>

n1sdp: fix DMC ECC enablement sequence in N1SDP platform

The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.

This pa

n1sdp: fix DMC ECC enablement sequence in N1SDP platform

The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.

This patch fixes the sequence so that DMCs are set to CONFIG
state before writing to ERR0CTLR0 register and moved back to
READY state after writing.

Change-Id: I1252f3ae0991603bb29234029cddb5fbf869c1b2
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

show more ...

37b7003104-Jul-2019 Ambroise Vincent <ambroise.vincent@arm.com>

arm: Shorten the Firmware Update (FWU) process

The watchdog is configured with a default value of 256 seconds in order
to implement the Trusted Board Boot Requirements.

For the FVP and Juno platfor

arm: Shorten the Firmware Update (FWU) process

The watchdog is configured with a default value of 256 seconds in order
to implement the Trusted Board Boot Requirements.

For the FVP and Juno platforms, the FWU process relies on a watchdog
reset. In order to automate the test of FWU, the length of this process
needs to be as short as possible. Instead of waiting for those 4 minutes
to have a reset by the watchdog, tell it to reset immediately.

There are no side effects as the value of the watchdog's load register
resets to 0xFFFFFFFF.

Tested on Juno.

Change-Id: Ib1aea80ceddc18ff1e0813a5b98dd141ba8a3ff2
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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53f3751b23-Jul-2019 Soby Mathew <soby.mathew@arm.com>

Merge "Cortex_hercules: Introduce preliminary cpu support" into integration

b514ee8619-Jul-2019 Soby Mathew <soby.mathew@arm.com>

Merge "intel: Adds support for Agilex platform" into integration


/rk3399_ARM-atf/common/backtrace/backtrace.c
/rk3399_ARM-atf/docs/components/sdei.rst
/rk3399_ARM-atf/docs/conf.py
/rk3399_ARM-atf/docs/getting_started/porting-guide.rst
/rk3399_ARM-atf/docs/maintainers.rst
/rk3399_ARM-atf/docs/plat/intel-agilex.rst
/rk3399_ARM-atf/docs/requirements.txt
/rk3399_ARM-atf/docs/resources/diagrams/plantuml/io_arm_class_diagram.puml
/rk3399_ARM-atf/docs/resources/diagrams/plantuml/io_dev_init_and_check.puml
/rk3399_ARM-atf/docs/resources/diagrams/plantuml/io_dev_registration.puml
/rk3399_ARM-atf/docs/resources/diagrams/plantuml/io_framework_usage_overview.puml
/rk3399_ARM-atf/drivers/console/aarch32/skeleton_console.S
/rk3399_ARM-atf/drivers/console/aarch64/skeleton_console.S
/rk3399_ARM-atf/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
/rk3399_ARM-atf/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
/rk3399_ARM-atf/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
/rk3399_ARM-atf/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
/rk3399_ARM-atf/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
/rk3399_ARM-atf/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
/rk3399_ARM-atf/include/arch/aarch32/console_macros.S
intel/soc/agilex/aarch64/plat_helpers.S
intel/soc/agilex/aarch64/platform_common.c
intel/soc/agilex/bl2_plat_mem_params_desc.c
intel/soc/agilex/bl2_plat_setup.c
intel/soc/agilex/bl31_plat_setup.c
intel/soc/agilex/include/agilex_clock_manager.h
intel/soc/agilex/include/agilex_handoff.h
intel/soc/agilex/include/agilex_mailbox.h
intel/soc/agilex/include/agilex_memory_controller.h
intel/soc/agilex/include/agilex_noc.h
intel/soc/agilex/include/agilex_pinmux.h
intel/soc/agilex/include/agilex_private.h
intel/soc/agilex/include/agilex_reset_manager.h
intel/soc/agilex/include/agilex_system_manager.h
intel/soc/agilex/include/plat_macros.S
intel/soc/agilex/include/platform_def.h
intel/soc/agilex/include/socfpga_private.h
intel/soc/agilex/platform.mk
intel/soc/agilex/soc/agilex_clock_manager.c
intel/soc/agilex/soc/agilex_handoff.c
intel/soc/agilex/soc/agilex_mailbox.c
intel/soc/agilex/soc/agilex_memory_controller.c
intel/soc/agilex/soc/agilex_pinmux.c
intel/soc/agilex/soc/agilex_reset_manager.c
intel/soc/agilex/soc/agilex_system_manager.c
intel/soc/agilex/socfpga_delay_timer.c
intel/soc/agilex/socfpga_image_load.c
intel/soc/agilex/socfpga_psci.c
intel/soc/agilex/socfpga_sip_svc.c
intel/soc/agilex/socfpga_storage.c
intel/soc/agilex/socfpga_topology.c
2f11d54827-Jun-2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>

intel: Adds support for Agilex platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef

936072ed13-Jun-2019 Jun Nie <jun.nie@linaro.org>

plat: imx7: Add PicoPi iMX7D basic support

The PicoPi iMX7D is a 2 board development board consisting of
a System-on-Module and a carrier baseboard and optimized for
the Internet-of-Things (IoT).

T

plat: imx7: Add PicoPi iMX7D basic support

The PicoPi iMX7D is a 2 board development board consisting of
a System-on-Module and a carrier baseboard and optimized for
the Internet-of-Things (IoT).

This patch add basic support to this board.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Louis Mayencourt <louis.mayencourt@arm.com>
Change-Id: I009d85819c4f73b7063aab73d0f6ee74e6ef3fc4

show more ...

c5937f2d13-Jun-2019 Jun Nie <jun.nie@linaro.org>

plat: imx7: refactor code for reuse

For the iMX7 SOCs, part of the code for platform
setup implementation can be reused and made
common for all these SoCs. This patch extracts
the common part for re

plat: imx7: refactor code for reuse

For the iMX7 SOCs, part of the code for platform
setup implementation can be reused and made
common for all these SoCs. This patch extracts
the common part for reuse.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Change-Id: I42fd4167e6903416df96a0159a046abf3896e878

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