| 018358fc | 18-May-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: console: Convert to multi-console API
Convert the R-Car Gen3 platform and both SCIF and Log drivers
to multi-console API.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Chang
rcar_gen3: console: Convert to multi-console API
Convert the R-Car Gen3 platform and both SCIF and Log drivers
to multi-console API.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I18556973937d150b60453f9150d54ee612571e35
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| dd5deabd | 11-Jun-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
plat/arm: Skip BL2U if RESET_TO_SP_MIN flag is set
BL2U should not build when RESET_TO_SP_MIN flag is set, like BL1 and
BL2.
Change-Id: Iac516121f98611ca1f58d2b5efdec6525b06ce4e
Signed-off-by: Loui
plat/arm: Skip BL2U if RESET_TO_SP_MIN flag is set
BL2U should not build when RESET_TO_SP_MIN flag is set, like BL1 and
BL2.
Change-Id: Iac516121f98611ca1f58d2b5efdec6525b06ce4e
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| cb60e71e | 10-Jun-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "jts/ti_fix" into integration
* changes:
ti: k3: common: Remove coherency workaround for AM65x
ti: k3: common: Use coherent memory for shared data |
| 8f31853b | 08-Jun-2019 |
Samuel Holland <samuel@sholland.org> |
allwinner: Disable unused features to save space
As all Allwinner platforms are single-cluster A53 chips, we can disable
support for newer, unsupported architecture extensions. We can also
avoid som
allwinner: Disable unused features to save space
As all Allwinner platforms are single-cluster A53 chips, we can disable
support for newer, unsupported architecture extensions. We can also
avoid some cache maintenance code, since no platform-specific setup is
required to enable coherency.
These changes reduce the size of .text on a default build with GCC 9.1
enough that .vectors again fits in the second half of a page, instead
of requiring its own page.
This commit was boot-tested on the Pinebook.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ib90454ef0c798d5e714b7780c585be0b1ed49c6d
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| 74eaf266 | 06-Jun-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Merge "FVP: Remove GIC initialisation from secondary core cold boot" into integration |
| 48d6b264 | 25-Apr-2019 |
Andrew F. Davis <afd@ti.com> |
ti: k3: common: Remove coherency workaround for AM65x
We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the las
ti: k3: common: Remove coherency workaround for AM65x
We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the last accessed areas all being marked as non-cached by
USE_COHERENT_MEM we can rely on that to workaround our interconnect
issues. Remove the old workaround.
Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7
Signed-off-by: Andrew F. Davis <afd@ti.com>
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| 65f7b817 | 25-Apr-2019 |
Andrew F. Davis <afd@ti.com> |
ti: k3: common: Use coherent memory for shared data
HW_ASSISTED_COHERENCY implies something stronger than just hardware
coherent interconnect, specifically a DynamIQ capable ARM core.
For K3, lets
ti: k3: common: Use coherent memory for shared data
HW_ASSISTED_COHERENCY implies something stronger than just hardware
coherent interconnect, specifically a DynamIQ capable ARM core.
For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early
and then let the caches get shut off on powerdown, to prevent data
corruption we also need to USE_COHERENT_MEM so that any accesses to
shared memory after this point is only to memory that is set as
non-cached for all cores.
Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949
Signed-off-by: Andrew F. Davis <afd@ti.com>
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| 16b49f60 | 02-May-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: add mcsi driver
add mcsi driver to support cache coherence.
Change-Id: I94f5922783e5dbc6b7e92aa06464bc1f0177f00a
Signed-off-by: kenny liang <kenny.liang@mediatek.com> |
| 28a773ef | 02-May-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: add GIC driver
Add Mediatek GIC driver to support interrupt functions.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I967a18f2e45b7bbc88c506dd4f1f40a745227ad9 |
| 9c29e5f7 | 03-Jun-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
FVP: Remove GIC initialisation from secondary core cold boot
During the secondary cores' cold boot path, the cores initialise the GIC
CPU interface. However this is a redundant action since 1) the c
FVP: Remove GIC initialisation from secondary core cold boot
During the secondary cores' cold boot path, the cores initialise the GIC
CPU interface. However this is a redundant action since 1) the cores are
powered down immediately after that, 2) the GIC CPU interface is
initialised from scratch when the secondary cores are powered up again
later.
Moreover, this part of code was introducing a bug. In a GICv3 system,
the GIC's CPU interface system registers must not be written without the
core being marked as "awake" in the redistributor. However, this
sequence was performing such accesses and this would cause those cores
to hang. The hang was caused by the DSB instruction that would never
complete because of the GIC not recognising those writes.
For the two aforementioned reasons, the entire part of the GIC CPU
interface initialisation is removed.
Change-Id: I6c33a1edda69dd5b6add16a27390a70731b5532a
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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| 629d04f5 | 03-Jun-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Apply compile-time check for AArch64-only cores
Some cores support only AArch64 mode. In those cores, only a limited
subset of the AArch32 system registers are implemented. Hence, if TF-A
is suppose
Apply compile-time check for AArch64-only cores
Some cores support only AArch64 mode. In those cores, only a limited
subset of the AArch32 system registers are implemented. Hence, if TF-A
is supposed to run on AArch64-only cores, it must be compiled with
CTX_INCLUDE_AARCH32_REGS=0.
Currently, the default settings for compiling TF-A are with the AArch32
system registers included. So, if we compile TF-A the default way and
attempt to run it on an AArch64-only core, we only get a runtime panic.
Now a compile-time check has been added to ensure that this flag has the
appropriate value when AArch64-only cores are included in the build.
Change-Id: I298ec550037fafc9347baafb056926d149197d4c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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| e9eed3f1 | 30-May-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "rockchip: drop rockchip-specific imported linker symbols for bl31" into integration |
| 3e6945e9 | 29-May-2019 |
Heiko Stuebner <heiko@sntech.de> |
rockchip: drop rockchip-specific imported linker symbols for bl31
In the rockchip bl31 setup the __RO_START__ and __RO_END__ symbols are
currently imported into special BL31_RO_* constants while the
rockchip: drop rockchip-specific imported linker symbols for bl31
In the rockchip bl31 setup the __RO_START__ and __RO_END__ symbols are
currently imported into special BL31_RO_* constants while the general
code also imports them as BL_CODE_BASE and BL_CODE_END.
So we can just use the general symbols and can drop the duplication.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ibf1b48ad80bed897247a1690a32711030479262d
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| 4d384eb4 | 28-May-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "plat: imx8m: Add the aipstz init to config peripheral access" into integration |
| 68b8ab0b | 28-May-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "for-upstream" into integration
* changes:
ti: k3: common: Set L2 latency on A72 cores
ti: k3: common: Add support for J721E |
| 570948d3 | 23-May-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "plat/meson/gxl: BL31: remove BL2 dependency" into integration |
| 16a755f3 | 10-May-2019 |
Andrew F. Davis <afd@ti.com> |
ti: k3: common: Set L2 latency on A72 cores
The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency h
ti: k3: common: Set L2 latency on A72 cores
The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Id534316dec1c1f326908efbfd964f219cda7386a
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| 7c088e71 | 22-Jun-2018 |
Nishanth Menon <nm@ti.com> |
ti: k3: common: Add support for J721E
Enable Cortex-A72 support for J721E.
Change-Id: I5bea5fb6ec45d1a9f8f2192d42da2cc03ae0f7ec
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Da
ti: k3: common: Add support for J721E
Enable Cortex-A72 support for J721E.
Change-Id: I5bea5fb6ec45d1a9f8f2192d42da2cc03ae0f7ec
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
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| c8f8579a | 22-May-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes Icf1ea76c,I9ca3f278 into integration
* changes:
imx8: Replace PLAT_IMX8* with automatic PLAT_imx8*
plat: imx8mq: Implement IMX_SIP_GET_SOC_INFO |
| ac166f64 | 21-May-2019 |
Jacky Bai <ping.bai@nxp.com> |
plat: imx8m: Add the aipstz init to config peripheral access
AIPSTZ provide access control for all the peripherals connected
to it. In this patch all the perperals are configured accessible
to all t
plat: imx8m: Add the aipstz init to config peripheral access
AIPSTZ provide access control for all the peripherals connected
to it. In this patch all the perperals are configured accessible
to all the master. it can be customized based the actual use
case.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I5ef5baa1da6906f13a60923d27ede336c61e319a
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| f56afc1f | 20-May-2019 |
Leonard Crestez <leonard.crestez@nxp.com> |
imx8: Replace PLAT_IMX8* with automatic PLAT_imx8*
Platform defines are already provided by the build system so let's not
duplicate them.
Change-Id: Icf1ea76c3c3213e27b447c95e2b22b961fa7693e
Signed
imx8: Replace PLAT_IMX8* with automatic PLAT_imx8*
Platform defines are already provided by the build system so let's not
duplicate them.
Change-Id: Icf1ea76c3c3213e27b447c95e2b22b961fa7693e
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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| 72196cbb | 10-May-2019 |
Leonard Crestez <leonard.crestez@nxp.com> |
plat: imx8mq: Implement IMX_SIP_GET_SOC_INFO
The manual documents that 0x3036006c should contains the soc revision
for imx8mq but this always reports A0. Work around this by parsing the
ROM header a
plat: imx8mq: Implement IMX_SIP_GET_SOC_INFO
The manual documents that 0x3036006c should contains the soc revision
for imx8mq but this always reports A0. Work around this by parsing the
ROM header and checking if OCOTP register 0x40 is stuck at 0xff0055aa.
Determining this inside TF-A makes life easier for OS, see for example
this linux discussion: https://lkml.org/lkml/2019/5/3/465
The soc revision can also be useful inside TF-A itself, for example for
the non-upstream DDR DVFS "busfreq" feature is affected by 8mq erratas.
The clock for OCOTP block can be disabled by OS so only initialize soc
revision once at boot time.
Change-Id: I9ca3f27840229ce8a28b53870e44da29f63c73aa
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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| 2beae525 | 16-May-2019 |
Kevin Hilman <khilman@baylibre.com> |
plat/meson/gxl: BL31: remove BL2 dependency
Remove an assert() that assumes a specific value being passed from
BL2. This value is dependent on BL2 version, so makes this assert()
not portable.
Sug
plat/meson/gxl: BL31: remove BL2 dependency
Remove an assert() that assumes a specific value being passed from
BL2. This value is dependent on BL2 version, so makes this assert()
not portable.
Suggested-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Change-Id: Ife3d934b2fa37fc1c66963dd4eb1afe2ca17d740
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| 482fc9c8 | 16-May-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration
* changes:
N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
N1SDP: Fix DRAM2 start address
Add option for defining platf
Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration
* changes:
N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
N1SDP: Fix DRAM2 start address
Add option for defining platform DRAM2 base
Disable speculative loads only if SSBS is supported
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| d8b11091 | 15-May-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "plat: imx8mq: Remove duplicated linker symbols" into integration |