1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/console.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <lib/coreboot.h> 18 #include <lib/mmio.h> 19 #include <plat_private.h> 20 #include <plat/common/platform.h> 21 22 static entry_point_info_t bl33_ep_info; 23 24 /******************************************************************************* 25 * Return a pointer to the 'entry_point_info' structure of the next image for 26 * the security state specified. BL33 corresponds to the non-secure image type. 27 * A NULL pointer is returned if the image does not exist. 28 ******************************************************************************/ 29 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 30 { 31 entry_point_info_t *next_image_info; 32 33 next_image_info = &bl33_ep_info; 34 35 if (next_image_info->pc == 0U) { 36 return NULL; 37 } 38 39 return next_image_info; 40 } 41 42 #pragma weak params_early_setup 43 void params_early_setup(u_register_t plat_param_from_bl2) 44 { 45 } 46 47 unsigned int plat_is_my_cpu_primary(void); 48 49 /******************************************************************************* 50 * Perform any BL32 specific platform actions. 51 ******************************************************************************/ 52 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 53 u_register_t arg2, u_register_t arg3) 54 { 55 static console_16550_t console; 56 struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0; 57 58 params_early_setup(arg1); 59 60 #if COREBOOT 61 if (coreboot_serial.type) 62 console_16550_register(coreboot_serial.baseaddr, 63 coreboot_serial.input_hertz, 64 coreboot_serial.baud, 65 &console); 66 #else 67 console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK, 68 PLAT_RK_UART_BAUDRATE, &console); 69 #endif 70 VERBOSE("sp_min_setup\n"); 71 72 /* Passing a NULL context is a critical programming error */ 73 assert(arg_from_bl2); 74 75 assert(arg_from_bl2->h.type == PARAM_BL31); 76 assert(arg_from_bl2->h.version >= VERSION_1); 77 78 bl33_ep_info = *arg_from_bl2->bl33_ep_info; 79 } 80 81 /******************************************************************************* 82 * Perform any sp_min platform setup code 83 ******************************************************************************/ 84 void sp_min_platform_setup(void) 85 { 86 generic_delay_timer_init(); 87 plat_rockchip_soc_init(); 88 89 /* Initialize the gic cpu and distributor interfaces */ 90 plat_rockchip_gic_driver_init(); 91 plat_rockchip_gic_init(); 92 plat_rockchip_pmu_init(); 93 } 94 95 /******************************************************************************* 96 * Perform the very early platform specific architectural setup here. At the 97 * moment this is only intializes the mmu in a quick and dirty way. 98 ******************************************************************************/ 99 void sp_min_plat_arch_setup(void) 100 { 101 plat_cci_init(); 102 plat_cci_enable(); 103 104 plat_configure_mmu_svc_mon(BL_CODE_BASE, 105 BL_COHERENT_RAM_END - BL_CODE_BASE, 106 BL_CODE_BASE, 107 BL_CODE_END, 108 BL_COHERENT_RAM_BASE, 109 BL_COHERENT_RAM_END); 110 } 111 112 void sp_min_plat_fiq_handler(uint32_t id) 113 { 114 VERBOSE("[sp_min] interrupt #%d\n", id); 115 } 116