intel: Create SiP service header file

Separate SiP related definition from mailbox header file

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I45ba540f29d92610

intel: Create SiP service header file

Separate SiP related definition from mailbox header file

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I45ba540f29d9261007f7ec23469358747cf140b4

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rockchip: really use base+size for secure ddr regions

The calls to secure ddr regions on rk3288 and rk3399 use parameters of
base and size - as it custom for specifying memory regions, but the
funct

rockchip: really use base+size for secure ddr regions

The calls to secure ddr regions on rk3288 and rk3399 use parameters of
base and size - as it custom for specifying memory regions, but the
functions themself expect start and endpoints of the area.

This only works by chance for the TZRAM, as it starts a 0x0 and therefore
its end location is the same as its size.

To not fall into a trap later on adapt the functions to really take
base+size parameters.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Idb9fab38aa081f3335a4eca971e7b7f6757fbbab

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rockchip: bring TZRAM_SIZE values in line

The agreed upon division of early boot locations is 0x40000 for bl31
to leave enough room for u-boot-spl and 0x100000 for bl33 (u-boot).

rk3288 and rk3399

rockchip: bring TZRAM_SIZE values in line

The agreed upon division of early boot locations is 0x40000 for bl31
to leave enough room for u-boot-spl and 0x100000 for bl33 (u-boot).

rk3288 and rk3399 already correctly secure the ddr up to the 1MB boundary
so pull the other platforms along to also give the Rockchip TF-A enough
room to comfortably live in.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Ie9e0c927d3074a418b6fd23b599d2ed7c15c8c6f

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allwinner: h6: power: Switch to using the AXP driver

Chip ID checking and poweroff work just like they did before.
Regulators are now enabled just like on A64/H5.

This changes the signatures of the

allwinner: h6: power: Switch to using the AXP driver

Chip ID checking and poweroff work just like they did before.
Regulators are now enabled just like on A64/H5.

This changes the signatures of the low-level register read/write
functions to match the interface expected by the common driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I14d63d171a094fa1375904928270fa3e21761646

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allwinner: Convert AXP803 regulator setup code into a driver

Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely
independent. However, some H6 boards also need early regulator setu

allwinner: Convert AXP803 regulator setup code into a driver

Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely
independent. However, some H6 boards also need early regulator setup.

Most of the register interface and all of the device tree traversal code
can be reused between the AXP803 and AXP805. The main difference is the
hardware bus interface, so that part is left to the platforms. The
remainder is moved into a driver.

I factored out the bits that were obviously specific to the AXP803;
additional changes for compatibility with other PMICs can be made as
needed.

The only functional change is that rsb_init() now checks the PMIC's chip
ID register against the expected value. This was already being done in
the H6 version of the code.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Icdcf9edd6565f78cccc503922405129ac27e08a2

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allwinner: a64: power: Use fdt_for_each_subnode

This simplifies the code a bit. Verified to produce the same binary.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie1ec1ce2ea39c465

allwinner: a64: power: Use fdt_for_each_subnode

This simplifies the code a bit. Verified to produce the same binary.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie1ec1ce2ea39c46525840906826c90a8a7eff287

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allwinner: a64: power: Remove obsolete register check

As of a561e41bf1d2 ("allwinner: power: add enable switches for DCDC1/5")
there are no longer regulators without an enable register provided.
Sin

allwinner: a64: power: Remove obsolete register check

As of a561e41bf1d2 ("allwinner: power: add enable switches for DCDC1/5")
there are no longer regulators without an enable register provided.
Since it seems reasonable that this will continue to be the case, drop
the check.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Icd7ec26fc6450d053e6e6d855fc16229b1d65a39

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allwinner: a64: power: Remove duplicate DT check

should_enable_regulator() is already checked in the regulators subnode
loop before setup_regulator() is called, so there's no need to check it
again

allwinner: a64: power: Remove duplicate DT check

should_enable_regulator() is already checked in the regulators subnode
loop before setup_regulator() is called, so there's no need to check it
again here.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idb8b8a6e435246f4fb226bc84813449d80a0a977

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allwinner: Build PMIC bus drivers only in BL31

These are used by the PMIC setup code, which runs during BL31
initialization, and the PSCI shutdown code, also a part of BL31.
They can't be needed bef

allwinner: Build PMIC bus drivers only in BL31

These are used by the PMIC setup code, which runs during BL31
initialization, and the PSCI shutdown code, also a part of BL31.
They can't be needed before BL31, or it wouldn't be possible to boot.
Allwinner platforms don't generally build anything but BL31 anyway, but
this change improves clarity and consistency with allwinner-common.mk.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I24f1d9ca8b4256e44badf5218d04d8690082babf

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allwinner: a64: power: Make sunxi_turn_off_soc static

The function is only used in this file, and it doesn't make sense for it
to be used anywhere else.

Signed-off-by: Samuel Holland <samuel@sholla

allwinner: a64: power: Make sunxi_turn_off_soc static

The function is only used in this file, and it doesn't make sense for it
to be used anywhere else.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iab18f082911edcdbc37ceeaff8c512be68e0cb0f

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allwinner: Merge duplicate code in sunxi_power_down

The action of last resort isn't going to change between SoCs. This moves
that code back to the PSCI implementation, where it more obviously
matche

allwinner: Merge duplicate code in sunxi_power_down

The action of last resort isn't going to change between SoCs. This moves
that code back to the PSCI implementation, where it more obviously
matches the code in sunxi_system_reset().

The two error messages say essentially the same thing anyway.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I62ac35fdb5ed78a016e9b18281416f1dcea38a4a

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allwinner: Clean up PMIC-related error handling

- Check the return value from sunxi_init_platform_r_twi().
- Print the PMIC banner before doing anything that might fail.
- Remove double prefixes in

allwinner: Clean up PMIC-related error handling

- Check the return value from sunxi_init_platform_r_twi().
- Print the PMIC banner before doing anything that might fail.
- Remove double prefixes in error messages.
- Consistently omit the trailing period.
- No need to print the unknown SoC's ID, since we already did that
earlier in bl31_platform_setup().
- On the other hand, do print the ID of the unknown PMIC.
- Try to keep the messages concise, as the large string size in these
files was causing the firmware to spill into the next page.
- Downgrade the banner from NOTICE to INFO. It's purely informational,
and people should be using debug builds on untested hardware anyway.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ib909408a5fdaebe05470fbce48d245dd0bf040eb

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allwinner: Synchronize PMIC enumerations

Ensure that the default (zero) value represents the case where we take
no action. Previously, if a PLAT=sun50i_a64 build was booted on an
unknown SoC ID, it

allwinner: Synchronize PMIC enumerations

Ensure that the default (zero) value represents the case where we take
no action. Previously, if a PLAT=sun50i_a64 build was booted on an
unknown SoC ID, it would be treated as an H5 at shutdown.

This removes some duplicate code and fixes error propagation on H6.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I4e51d8a43a56eccb0d8088593cb9908e52e782bc

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allwinner: Enable clock before resetting I2C/RSB

The clock must be running for the module to be reset.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ic8fafc946f3a1a697174b91288e357

allwinner: Enable clock before resetting I2C/RSB

The clock must be running for the module to be reset.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ic8fafc946f3a1a697174b91288e357ffa033ab9a

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rockchip: Prevent macro expansion in paths

Instead of stringizing the paths to binary files, add them as string
defines on the command line (e.g. -DFOO=\"BAR\" instead of -DFOO=BAR).
This prevents m

rockchip: Prevent macro expansion in paths

Instead of stringizing the paths to binary files, add them as string
defines on the command line (e.g. -DFOO=\"BAR\" instead of -DFOO=BAR).
This prevents macros from being expanded inside the string value itself.
For example, -DFOO=/path/with-linux-in-it would have been expanded to
"/path/with-1-in-it" because `linux=1` is one of the standard GCC
defines.

Change-Id: I7b65df3c9930faed4f1aff75ad726982ae3671e6
Signed-off-by: Joshua Watt <JPEWhacker@gmail.com>

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Merge "allwinner: Fix incorrect ARISC code patch offset check" into integration

Merge "allwinner: power: Add DLDO4 power rail" into integration

Merge "intel: s10: Remove unused source code" into integration

plat/rockchip: cliam a macro to enable hdcp feature for DP

HDCP is using a binary driver, add macro PLAT_RK_DP_HDCP to make it as
an option.

Change-Id: I54ef1a3635a28e8ae56654bd1e91dfe011520a7f
Sig

plat/rockchip: cliam a macro to enable hdcp feature for DP

HDCP is using a binary driver, add macro PLAT_RK_DP_HDCP to make it as
an option.

Change-Id: I54ef1a3635a28e8ae56654bd1e91dfe011520a7f
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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intel: s10: Remove unused source code

remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory
as both has been refactored to common directory for sharing with agilex
platform

Signed-

intel: s10: Remove unused source code

remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory
as both has been refactored to common directory for sharing with agilex
platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I395fed66408f536e8fefd637681e742c63621818

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arm: gicv3: Fix compiler dependent behavior

C99 standard: "What constitutes an access to an object that has
volatile-qualified type is implementation-defined".

GCC is not considering the cast to vo

arm: gicv3: Fix compiler dependent behavior

C99 standard: "What constitutes an access to an object that has
volatile-qualified type is implementation-defined".

GCC is not considering the cast to void of volatile structures as an
access and so is not actually issuing reads.

Clang does read those structures by copying them on the stack, which in
this case creates an overflow because of their large size.

This patch removes the cast to void and instead uses the USED attribute
to tell the compiler to retain the static variables.

Change-Id: I952b5056e3f6e91841e7ef9558434352710ab80d
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Zelalem Aweke <zelalem.aweke@arm.com>

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plat/rockchip: enable power domains of rk3399 before reset

This patch fixes hangs that happen after soft resetting of rk3399.

Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
Change-Id: If41b12b

plat/rockchip: enable power domains of rk3399 before reset

This patch fixes hangs that happen after soft resetting of rk3399.

Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
Change-Id: If41b12ba1dfcb2ba937361b58eafd50bf5c483d4

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Tegra194: smmu: add support for backup multiple smmu regs

Tegra194 supports multiple SMMU blocks. This patch adds support to
save register values for SMMU0 and SMMU2, before entering the System
Susp

Tegra194: smmu: add support for backup multiple smmu regs

Tegra194 supports multiple SMMU blocks. This patch adds support to
save register values for SMMU0 and SMMU2, before entering the System
Suspend state.

Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: introduce tegra_mc_def.h

This patch introduces memory controller register defines
for Tegra194 platforms.

Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6
Signed-off-by: Pritesh Raith

Tegra194: introduce tegra_mc_def.h

This patch introduces memory controller register defines
for Tegra194 platforms.

Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: 40-bit wide memory address space

This patch updates the memory address space, physical and virtual,
to be 40-bits wide for all Tegra194 platforms.

Change-Id: Ie1bcdec2c4e8e15975048ce1c2a3

Tegra194: 40-bit wide memory address space

This patch updates the memory address space, physical and virtual,
to be 40-bits wide for all Tegra194 platforms.

Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c
Signed-off-by: Steven Kao <skao@nvidia.com>

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