Merge "intel: Refactor common platform code [5/5]" into integration

Merge changes from topic "platform-refactor" into integration

* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform c

Merge changes from topic "platform-refactor" into integration

* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform code [2/5]
intel: Refactor common platform code [1/5]

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Merge "rockchip: px30: Add support for UART3 as serial output" into integration

imx: Fix multiple definition of ipc_handle

This is not conforming C and does not compile with -fno-common.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I6535954cc567d6efa06919069b

imx: Fix multiple definition of ipc_handle

This is not conforming C and does not compile with -fno-common.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I6535954cc567d6efa06919069b91e3f50975b073

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imx: Fix missing inclusion of cdefs.h

This was found by compiling with -fno-common:

./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed';
./build/picopi/rele

imx: Fix missing inclusion of cdefs.h

This was found by compiling with -fno-common:

./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed';
./build/picopi/release/bl2/imx_caam.o:(.bss.__packed+0x0): first defined here

__packed was intended to be the attribute macro from cdefs.h, not an
object of the structure type.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id02fac3f098be2d71c35c6b4a18012515532f32a

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allwinner: Fix incorrect ARISC code patch offset check

The current range check for the offset is wrong: it is counting bytes,
while indexing an array of uint32_t. Since the offset is always zero,
th

allwinner: Fix incorrect ARISC code patch offset check

The current range check for the offset is wrong: it is counting bytes,
while indexing an array of uint32_t. Since the offset is always zero,
the parameter is unnecessary. Instead of adding more code to fix the
check, remove the parameter to avoid the problem entirely.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iadfc7d027155adc754e017b3462233ce9a1d64f6

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Merge "Enable -Wlogical-op always" into integration

Merge "Enable -Wshadow always" into integration

Merge "plat/rockchip: initialize reset and poweroff GPIOs with known invalid value" into integration

Merge changes from topic "tegra-downstream-092319" into integration

* changes:
Tegra194: add support to reset GPU
Tegra194: memctrl: fix logic to check TZDRAM config register access
Tegra: int

Merge changes from topic "tegra-downstream-092319" into integration

* changes:
Tegra194: add support to reset GPU
Tegra194: memctrl: fix logic to check TZDRAM config register access
Tegra: introduce plat_enable_console()
Tegra: include: drivers: introduce spe.h
Tegra194: update nvg header to v6.4
Tegra194: mce: enable strict checking
Tegra194: CC6 state from last offline CPU in the cluster
Tegra194: console driver compilation from platform makefiles
Tegra194: memctrl: platform handler for TZDRAM setup
Tegra194: memctrl: override SE client as coherent
Tegra194: save system suspend entry marker to TZDRAM
Tegra194: helper functions for CPU rst handler and SMMU ctx offset
Tegra194: cleanup references to Tegra186
Tegra194: mce: display NVG header version during boot
Tegra194: mce: fix cg_cstate encoding format
Tegra194: drivers: SE and RNG1/PKA1 context save support
Tegra194: rename secure scratch register macros
Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation
Tegra194: mce: remove unsupported functionality
Tegra194: sanity check target cluster during core power on
Tegra194: fix defects flagged by MISRA scan
Tegra194: mce: fix defects flagged by MISRA scan
Tegra194: remove the GPU reset register macro
Tegra194: MC registers to allow CPU accesses to TZRAM
Tegra194: increase MAX_MMAP_REGIONS macro value
Tegra194: update nvg header to v6.1
Tegra194: update cache operations supported by the ROC
Tegra194: memctrl: platform handlers to reprogram MSS
Tegra194: core and cluster count values
Tegra194: correct the TEGRA_CAR_RESET_BASE macro value
Tegra194: add MC_SECURITY mask defines
Tegra194: Update wake mask, wake time for cpu offlining
Tegra194: program stream ids for XUSB
Tegra194: Update checks for c-state stats
Tegra194: smmu: fix mask for board revision id
Tegra194: smmu: ISO support
Tegra194: Initialize smmu on system suspend exit
Tegra194: Update cpu core-id calculation
Tegra194: read-modify-write ACTLR_ELx registers
Tegra194: Enable fake system suspend
Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits
Tegra194: platform support for memctrl/smmu drivers
Tegra194: Support for cpu suspend

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Tegra194: add support to reset GPU

This patch adds macros, to define registers required to support GPU
reset, for Tegra194 SoCs.

Change-Id: Ifa7e0161b9e8de695a33856193f500b847a03526
Signed-off-by:

Tegra194: add support to reset GPU

This patch adds macros, to define registers required to support GPU
reset, for Tegra194 SoCs.

Change-Id: Ifa7e0161b9e8de695a33856193f500b847a03526
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

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Tegra194: memctrl: fix logic to check TZDRAM config register access

This patch fixes the logic to check if the previous bootloader has
disabled access to the TZDRAM configuration registers. The pola

Tegra194: memctrl: fix logic to check TZDRAM config register access

This patch fixes the logic to check if the previous bootloader has
disabled access to the TZDRAM configuration registers. The polarity
for the bit was incorrect in the previous check.

Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra: introduce plat_enable_console()

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while a

Tegra: introduce plat_enable_console()

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.

For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.

Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: include: drivers: introduce spe.h

This patch introduces a header file for the spe-console driver. This
file currently provides a device struct and a registration function
call for clients.

S

Tegra: include: drivers: introduce spe.h

This patch introduces a header file for the spe-console driver. This
file currently provides a device struct and a registration function
call for clients.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ic65c056f5bd60871d8a3f44f2c1210035f878799

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Tegra194: update nvg header to v6.4

This patch updates the header, t194_nvg.h, to v6.4. This
gets it in synch with MTS pre-release 2 - cl39748439.

Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ec

Tegra194: update nvg header to v6.4

This patch updates the header, t194_nvg.h, to v6.4. This
gets it in synch with MTS pre-release 2 - cl39748439.

Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ecd7
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: mce: enable strict checking

"Strict checking" is a mode where secure world can access
secure-only areas unlike legacy mode where secure world could
access non-secure spaces as well. Secure

Tegra194: mce: enable strict checking

"Strict checking" is a mode where secure world can access
secure-only areas unlike legacy mode where secure world could
access non-secure spaces as well. Secure-only areas are defined
as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set.
This mode not only helps prevent issues with IO-Coherency but aids
with security as well.

This patch implements the programming sequence required to enable
strict checking mode for Tegra194 SoCs.

Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0
Signed-off-by: Dilan Lee <dilee@nvidia.com>

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Tegra194: CC6 state from last offline CPU in the cluster

This patch enables the CC6 cluster state for the cluster, if the
current CPU being offlined is the last CPU in the cluster.

Change-Id: I3380

Tegra194: CC6 state from last offline CPU in the cluster

This patch enables the CC6 cluster state for the cluster, if the
current CPU being offlined is the last CPU in the cluster.

Change-Id: I3380a969b534fcd14f9c46433471cc1c2adf6011
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: console driver compilation from platform makefiles

This patch includes the console driver from individual platform
makefile, to allow future platforms to include consoles of their
choice.

Tegra194: console driver compilation from platform makefiles

This patch includes the console driver from individual platform
makefile, to allow future platforms to include consoles of their
choice.

Change-Id: I4c92199717da410c8b5e8d45af67f4345f743dbd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: memctrl: platform handler for TZDRAM setup

This patch provides the platform with flexibility to perform custom
steps during TZDRAM setup. Tegra194 platforms checks if the config
registers

Tegra194: memctrl: platform handler for TZDRAM setup

This patch provides the platform with flexibility to perform custom
steps during TZDRAM setup. Tegra194 platforms checks if the config
registers are locked and TZDRAM setup has already been done by the
previous bootloaders, before setting up the fence.

Change-Id: Ifee7077d4b46a7031c4568934c63e361c53a12e3
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: memctrl: override SE client as coherent

This patch enables IO coherency for SE clients, SEWR and SERD,
by overriding their platform settings to "normal_coherent".
This setting also convert

Tegra194: memctrl: override SE client as coherent

This patch enables IO coherency for SE clients, SEWR and SERD,
by overriding their platform settings to "normal_coherent".
This setting also converts read/write requests from these SE
clients to Normal type.

Change-Id: I31ad195ad30ecc9ee785e5e84184cda2eea5c45a
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Signed-off-by: Jeff Tsai <jefft@nvidia.com>

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Tegra194: save system suspend entry marker to TZDRAM

This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is

Tegra194: save system suspend entry marker to TZDRAM

This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is actually an exit from System Suspend.

The Tegra194 platform handler sets the system suspend entry marker
before entering SC7 state and the trampoline flips the state back to
system resume, on exiting SC7.

Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: helper functions for CPU rst handler and SMMU ctx offset

This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offse

Tegra194: helper functions for CPU rst handler and SMMU ctx offset

This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offset.
These helper functions are used by the System Suspend entry sequence
to save the SMMU context and CPU reset handler to TZDRAM.

Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: cleanup references to Tegra186

This patch cleans up all references to the Tegra186 family of SoCs.

Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0
Signed-off-by: Varun Wadekar <vwade

Tegra194: cleanup references to Tegra186

This patch cleans up all references to the Tegra186 family of SoCs.

Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: mce: display NVG header version during boot

The MCE driver checks the NVG interface version during boot and
disaplys the hardware and software versions on the console. The
software version

Tegra194: mce: display NVG header version during boot

The MCE driver checks the NVG interface version during boot and
disaplys the hardware and software versions on the console. The
software version is being displayed as zero.

This patch updates the prints to use the real NVG header version
instead.

Change-Id: I8e9d2e6c43a59a8a6d5ca7aa8153b940fce86709
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: mce: fix cg_cstate encoding format

This patch does the following:
- cstate_info variable is used to pass on requested cstate to mce
- Currently, cg_cstate is encoded using 2 bits(bits 8, 9

Tegra194: mce: fix cg_cstate encoding format

This patch does the following:
- cstate_info variable is used to pass on requested cstate to mce
- Currently, cg_cstate is encoded using 2 bits(bits 8, 9) in cstate_info
- cg_cstate values can range from 0 to 7, with 7 representing cg7
- Thus, cg_cstate is to be encoded using 3 bits (val: 0-7)
- Fix this, as per ISS and ensure bits 8, 9, 10 are used

Change-Id: Idff207e2a88b2f4654e4a956c27054bf5e8f69bb
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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