| 939fd3db | 09-Mar-2018 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1
PCIE0R1 does not program stream IDs, so allow the stream ID to be
overriden by the MC.
Change-Id: I4dbd71e1ce24b11e646de421ef68c762818c2667
Sig
Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1
PCIE0R1 does not program stream IDs, so allow the stream ID to be
overriden by the MC.
Change-Id: I4dbd71e1ce24b11e646de421ef68c762818c2667
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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|
| 33a8ba6a | 09-Feb-2018 |
Steven Kao <skao@nvidia.com> |
Tegra194: support for boot params wider than 32-bits
The previous bootloader is not able to pass boot params wider than
32-bits due to an oversight in the scratch register being used. A
new secure s
Tegra194: support for boot params wider than 32-bits
The previous bootloader is not able to pass boot params wider than
32-bits due to an oversight in the scratch register being used. A
new secure scratch register #75 has been assigned to pass the higher
bits.
This patch adds support to parse the higher bits from scratch #75
and use them in calculating the base address for the location of
the boot params.
Scratch #75 format
====================
31:16 - bl31_plat_params high address
15:0 - bl31_params high address
Change-Id: Id53c45f70a9cb370c776ed7c82ad3f2258576a80
Signed-off-by: Steven Kao <skao@nvidia.com>
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|
| 34a6610a | 07-Mar-2018 |
Puneet Saxena <puneets@nvidia.com> |
Tegra194: memctrl: set reorder depth limit for PCIE blocks
HW bug in third party PCIE IP - PCIE datapath hangs when there are
more than 28 outstanding requests on data backbone for x1 controller.
S
Tegra194: memctrl: set reorder depth limit for PCIE blocks
HW bug in third party PCIE IP - PCIE datapath hangs when there are
more than 28 outstanding requests on data backbone for x1 controller.
Suggested SW WAR is to limit reorder_depth_limit to 16 for
PCIE 1W/2AW/3W clients.
Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
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|
| eb41fee4 | 01-Mar-2018 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIU
-PTCR is ISO client so setting it to FORCE_NON_COHERENT.
-MPCORER, MPCOREW and MIU0R/W to MIU7R/W clients itself will provide
Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIU
-PTCR is ISO client so setting it to FORCE_NON_COHERENT.
-MPCORER, MPCOREW and MIU0R/W to MIU7R/W clients itself will provide
ordering so no need to override from mc.
-MIU0R/W to MIU7R/W clients registers are not implemented in tegrasim
so skipping it for simulation.
-All the clients need to set CGID_TAG_ADR to maintain request ordering
within a 4K boundary.
Change-Id: Iaa3189a1f3e40fb4cef28be36bc4baeb5ac8f9ca
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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|
| 90dce0f9 | 08-Feb-2018 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: memctrl: set CGID_TAG_ADR instead of CGID_TAG_DEFAULT
- All SoC clients should use CGID_TAG_ADR to improve perf
- Remove tegra194_txn_override_cfgs array that is not getting used.
Change-
Tegra194: memctrl: set CGID_TAG_ADR instead of CGID_TAG_DEFAULT
- All SoC clients should use CGID_TAG_ADR to improve perf
- Remove tegra194_txn_override_cfgs array that is not getting used.
Change-Id: I9130ef5ae8659ed5f9d843ab9a0ecf58b5ce9c74
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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|
| 1296da6d | 05-Jan-2018 |
Puneet Saxena <puneets@nvidia.com> |
Tegra194: memctrl: update mss reprogramming as HW PROD settings
Memory clients are divided in to ISO/NonISO/Order/Unordered/Low
BW/High BW. Based on the client types, HW team recommends, different
m
Tegra194: memctrl: update mss reprogramming as HW PROD settings
Memory clients are divided in to ISO/NonISO/Order/Unordered/Low
BW/High BW. Based on the client types, HW team recommends, different
memory ordering settings, IO coherency settings and SMMU register settings
for optimized performance of the MC clients.
For example ordered ISO clients should be set as strongly ordered and
should bypass SCF and directly access MC hence set as
FORCE_NON_COHERENT. Like this there are multiple recommendations
for all of the MC clients.
This change sets all these MC registers as per HW spec file.
Change-Id: I8a8a0887cd86bf6fe8ac7835df6c888855738cd9
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| a0cacc95 | 18-Jan-2018 |
Arto Merilainen <amerilainen@nvidia.com> |
Tegra194: memctrl: Disable PVARDC coalescer
Due to a hardware bug PVA may perform memory transactions which
cause coalescer faults. This change works around the issue by
disabling coalescer for PVA0
Tegra194: memctrl: Disable PVARDC coalescer
Due to a hardware bug PVA may perform memory transactions which
cause coalescer faults. This change works around the issue by
disabling coalescer for PVA0RDC and PVA1RDC.
Change-Id: I27d1f6e7bc819fb303dae98079d9277fa346a1d3
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
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|
| 21e22fe3 | 02-Jan-2018 |
Puneet Saxena <puneets@nvidia.com> |
Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent
Force memory transactions from seswr and sesrd as coherent_snoop from
no-override. This is necessary as niso clients should use
Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent
Force memory transactions from seswr and sesrd as coherent_snoop from
no-override. This is necessary as niso clients should use coherent
path.
Presently its set as FORCE_COHERENT_SNOOP. Once SE+TZ is enabled
with SMMU, this needs to be replaced by FORCE_COHERENT.
Change-Id: I8b50722de743b9028129b4715769ef93deab73b5
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
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|
| 1a7a1dcd | 28-Dec-2017 |
Vignesh Radhakrishnan <vigneshr@nvidia.com> |
Tegra194: Request CG7 from last core in cluster
- SC7 requires all the cluster groups to be in CG7 state, else
is_sc7_allowed will get denied
- As a WAR while requesting CC6, request CG7 as well
-
Tegra194: Request CG7 from last core in cluster
- SC7 requires all the cluster groups to be in CG7 state, else
is_sc7_allowed will get denied
- As a WAR while requesting CC6, request CG7 as well
- CG7 request will not be honored if it is not last core in Cluster
group
- This is just to satisfy MCE for now as CG7 is going to be defeatured
Change-Id: Ibf2f8a365a2e46bd427abd563da772b6b618350f
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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|
| d11f5e05 | 03-Jan-2018 |
steven kao <skao@nvidia.com> |
Tegra194: toggle SE clock during context save/restore
This patch adds support to toggle SE clock, using the bpmp_ipc
interface, to enable SE context save/restore. The SE sequence mostly
gets called
Tegra194: toggle SE clock during context save/restore
This patch adds support to toggle SE clock, using the bpmp_ipc
interface, to enable SE context save/restore. The SE sequence mostly
gets called during System Suspend/Resume.
Change-Id: I9cee12a9e14861d5e3c8c4f18b4d7f898b6ebfa7
Signed-off-by: steven kao <skao@nvidia.com>
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|
| fdc8021a | 11-Jan-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: bpmp: fix header file paths
This patch fixes the header file paths to include debug.h
from the right location.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: If303792d2169158f
Tegra: bpmp: fix header file paths
This patch fixes the header file paths to include debug.h
from the right location.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: If303792d2169158f436ae6aa5b6d7a4f88e28f7b
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|
| 3c6ec8f1 | 22-Jan-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Revert "plat/arm: Add support for SEPARATE_NOBITS_REGION"
This reverts commit d433bbdd459c222e5bf5ca87319807465b246d8c.
Change-Id: I46c69dce704a1ce1b50452dd4d62425c4a67f7f0 |
| 61cbd41d | 15-Jan-2020 |
Andrew Walbran <qwandor@google.com> |
qemu: Implement qemu_system_off via semihosting.
This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.
Sig
qemu: Implement qemu_system_off via semihosting.
This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.
Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I0fb7cf7909262b675c3143efeac07f4d60730b03
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|
| 74464d5b | 15-Jan-2020 |
Andrew Walbran <qwandor@google.com> |
qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.
This lets the Linux kernel or any other image which expects an FDT in x0 be
loaded directly as BL33 without a separate bootloader on QEMU.
qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.
This lets the Linux kernel or any other image which expects an FDT in x0 be
loaded directly as BL33 without a separate bootloader on QEMU.
Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: Ia8eb4710a3d97cdd877af3b8aae36a2de7cfc654
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|
| 31ce893e | 23-Jan-2020 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
xilinx: versal: PLM to ATF handover
Parse the parameter structure the PLM populates, to populate the
bl32 and bl33 image structures.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xili
xilinx: versal: PLM to ATF handover
Parse the parameter structure the PLM populates, to populate the
bl32 and bl33 image structures.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I317072d1086f6cc6f90883c1b8b6d086ff57b443
show more ...
|
| 4d9f825a | 07-Jan-2020 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
xilinx: common: Move ATF handover to common file
ATF handover can be used by Xilinx platforms, so move it to common
file from platform specific files.
Signed-off-by: Venkatesh Yadav Abbarapu <venka
xilinx: common: Move ATF handover to common file
ATF handover can be used by Xilinx platforms, so move it to common
file from platform specific files.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I5f0839351f534619de581d1953c8427a079487e0
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|
| f461fe34 | 07-Jan-2020 |
Anthony Steinhauser <asteinhauser@google.com> |
Prevent speculative execution past ERET
Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump
Prevent speculative execution past ERET
Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump instruction.
The speculative execution does not cross privilege-levels (to the jump
target as one would expect), but it continues on the kernel privilege
level as if the ERET instruction did not change the control flow -
thus execution anything that is accidentally linked after the ERET
instruction. Later, the results of this speculative execution are
always architecturally discarded, however they can leak data using
microarchitectural side channels. This speculative execution is very
reliable (seems to be unconditional) and it manages to complete even
relatively performance-heavy operations (e.g. multiple dependent
fetches from uncached memory).
This was fixed in Linux, FreeBSD, OpenBSD and Optee OS:
https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8
https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61
https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2
https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a
It is demonstrated in a SafeSide example:
https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc
https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c
Signed-off-by: Anthony Steinhauser <asteinhauser@google.com>
Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
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|
| f44d291f | 22-Jan-2020 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "add-versal-soc-support" into integration
* changes:
plat: xilinx: Move pm_client.h to common directory
plat: xilinx: versal: Make silicon default build target
xilinx:
Merge changes from topic "add-versal-soc-support" into integration
* changes:
plat: xilinx: Move pm_client.h to common directory
plat: xilinx: versal: Make silicon default build target
xilinx: versal: Wire silicon default setup
versal: Increase OCM memory size for DEBUG builds
plat: xilinx: versal: Dont set IOU switch clock
arm64: versal: Adjust cpu clock for versal virtual
xilinx: versal: Add support for PM_GET_OPERATING_CHARACTERISTIC EEMI call
plat: versal: Add Get_ChipID API
plat: xilinx: versal: Add load Pdi API support
xilinx: versal: Add feature check API
xilinx: versal: Implement set wakeup source for client
plat: xilinx: versal: Add GET_CALLBACK_DATA function
xilinx: versal: Add PSCI APIs for system shutdown & reset
xilinx: versal: Add PSCI APIs for suspend/resume
xilinx: versal: Remove no_pmc ops to ON power domain
xilinx: versal: Add set wakeup source API
xilinx: versal: Add client wakeup API
xilinx: versal: Add query data API
xilinx: versal: Add request wakeup API
xilinx: versal: Add PM_INIT_FINALIZE API for versal
xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API
xilinx: versal: enable ipi mailbox service
xilinx: move ipi mailbox svc to xilinx common
plat: xilinx: versal: Implement PM IOCTL API
xilinx: versal: Implement power down/restart related EEMI API
xilinx: versal: Add SMC handler for EEMI API
xilinx: versal: Implement PLL related PM APIs
xilinx: versal: Implement clock related PM APIs
xilinx: versal: Implement pin control related PM APIs
xilinx: versal: Implement reset related PM APIs
xilinx: versal: Implement device related PM APIs
xilinx: versal: Add support for suspend related APIs
xilinx: versal: Add get_api_version support
xilinx: Add support to send PM API to PMC using IPI for versal
plat: xilinx: versal: Move versal_def.h to include directory
plat: xilinx: versal: Move versal_private.h to include directory
plat: xilinx: zynqmp: Use GIC framework for warm restart
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|
| 67878cb0 | 19-Jan-2020 |
Norbert Werner <opensource@lab-w.org> |
Xilinx zynqmp: add missing pin control group for ethernet 0.
Signed-off-by: Norbert Werner <opensource@lab-w.org>
Change-Id: I3264515e5901689328861964ff664ff08b6e852c |
| d433bbdd | 16-Jan-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
plat/arm: Add support for SEPARATE_NOBITS_REGION
In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence m
plat/arm: Add support for SEPARATE_NOBITS_REGION
In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate
the build to require that ARM_BL31_IN_DRAM is enabled as well.
Naturally with SEPARATE_NOBITS_REGION enabled, the BL31 initialization code
cannot be reclaimed to be used for runtime data such as secondary cpu stacks.
Memory map for BL31 NOBITS region also has to be created.
Change-Id: Ibd480f82c1dc74e9cbb54eec07d7a8fecbf25433
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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|
| b449642a | 21-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "allwinner: Clean up MMU setup" into integration |
| 004c9228 | 21-Jan-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes Ib1ed9786,I6c4855c8 into integration
* changes:
plat: imx: Correct the SGIs that used for secure interrupt
plat: imx8mm: Add the support for opteed spd on imx8mq/imx8mm |
| 7b787899 | 20-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "tegra-downstream-01082020" into integration
* changes:
Tegra194: platform handler for entering CPU standby state
Tegra194: memctrl: force viw and vifalr/w transactions
Merge changes from topic "tegra-downstream-01082020" into integration
* changes:
Tegra194: platform handler for entering CPU standby state
Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent
Tegra194: memctrl: fix bug in client order id reg value generation
Tegra194: memctrl: enable mc coalescer
Tegra194: update scratch registers used to read boot parameters
Tegra194: implement system shutdown/reset handlers
Tegra194: mce: support for shutdown and reboot
Tegra194: request CG7 before checking if SC7 is allowed
Tegra194: config to enable/disable strict checking mode
Tegra194: remove unused platform configs
Tegra194: restore XUSB stream IDs on System Resume
show more ...
|
| ddb4c9e0 | 27-Oct-2019 |
Samuel Holland <samuel@sholland.org> |
allwinner: Clean up MMU setup
Remove the general BL31 mmap region: it duplicates the existing static
mapping for the entire SRAM region. Use the helper definitions when
applicable to simplify the co
allwinner: Clean up MMU setup
Remove the general BL31 mmap region: it duplicates the existing static
mapping for the entire SRAM region. Use the helper definitions when
applicable to simplify the code and add the MT_EXECUTE_NEVER flag.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I7a6b79e50e4b5c698774229530dd3d2a89e94a6d
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|
| 7b3ab4eb | 20-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat: xilinx: zynqmp: Add checksum support for IPI data" into integration |