Merge changes If4cd4e71,I0b5158ef into integration

* changes:
docs(fvp): add FVP_HW_CONFIG_ADDR documentation
feat(fvp): add FVP_HW_CONFIG_ADDR make variable

Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file

Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
feat(stm32mp21): add clock and reset bindings
refactor(stm32mp2): update display of reset reason
feat(stm32mp25): add RCC register to display all IWDG flags
feat(stm32mp21): add PWR registers file
feat(st): introduce SoC family compilation switch
docs(changelog): add subsections for STM32MP2
docs(stm32mp2): introduce new STM32MP23 family
docs(stm32mp2): introduce new STM32MP21 family

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Merge "fix(ti): remove validate_power_state definition" into integration

Merge changes I3303ca9a,I682da2d3 into integration

* changes:
feat(intel): migrate RSU client to SiPSVC V3
fix(intel): support generic mailbox command in SiPSVC V3

Merge "fix(intel): support SMC 64bit return args in SiPSVC V3" into integration

Merge changes I23e51bf9,I0fa9adaf into integration

* changes:
fix(intel): verify data size in AES GCM and GCM-GHASH modes
fix(intel): update FCS AES method for GCM block modes

Merge "fix(intel): update initialization to prevent warnings message" into integration

Merge "feat(intel): support IO96B ECC Error Injection via SMC call" into integration

Merge changes from topic "xlnx_versal2_cpuidle_fix" into integration

* changes:
fix(versal2): fix offsets for apu pcil
fix(versal2): initialize counter-timer frequency register
fix(versal2): u

Merge changes from topic "xlnx_versal2_cpuidle_fix" into integration

* changes:
fix(versal2): fix offsets for apu pcil
fix(versal2): initialize counter-timer frequency register
fix(versal2): use common function to get system counter frequency
fix(versal2): align IOU_SCNTR base address macro name with other platforms

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fix(versal2): validate Node ID in PM callback events

The PM_NOTIFY_CB is used to notify both events and errors from the PLM
firmware. The values of events and errors can overlap, they can be
disting

fix(versal2): validate Node ID in PM callback events

The PM_NOTIFY_CB is used to notify both events and errors from the PLM
firmware. The values of events and errors can overlap, they can be
distinguished using the Node ID, which is included in the callback payload.

Currently, when an EVENT_CPU_PWRDWN notification is received, TF-A powers
down cores without validating the Node ID. This leads to incorrect
behavior, as TFA powers down cores even when an error occurs that shares
the same event value.

Add a Node ID check to differentiate between events and errors to fix
this issue.

Change-Id: I65d69731b692928597e47678c684aea2b90b5e6d
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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fix(xilinx): validate Node ID in PM callback events

The PM_NOTIFY_CB is used to notify both events and errors from the PLM
firmware. The values of events and errors can overlap, they can be
distingu

fix(xilinx): validate Node ID in PM callback events

The PM_NOTIFY_CB is used to notify both events and errors from the PLM
firmware. The values of events and errors can overlap, they can be
distinguished using the Node ID, which is included in the callback payload.

Currently, when an EVENT_CPU_PWRDWN notification is received, TF-A powers
down cores without validating the Node ID. This leads to incorrect
behavior, as TFA powers down cores even when an error occurs that shares
the same event value.

Add a Node ID check to differentiate between events and errors to fix
this issue.

Change-Id: I4b92e0e1dac0c41a39f98efdf545bda7d64acba8
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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fix(xilinx): add macro to extract node class from node ID

Introduce the NODECLASS() macro to extract the node class from a given
node ID. This helps in filtering nodes based on their class as encode

fix(xilinx): add macro to extract node class from node ID

Introduce the NODECLASS() macro to extract the node class from a given
node ID. This helps in filtering nodes based on their class as encoded
in the ID.

Change-Id: I0e55b68a0103a99748df93b6fe9a3f1df4a7cca4
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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feat(intel): migrate RSU client to SiPSVC V3

Migrate all the RSU related commands to SiPSVC V3
framework.

Change-Id: I3303ca9ad81e412cc9543e0d50c1d7ea64dcc1f6
Signed-off-by: Girisha Dengi <girisha.

feat(intel): migrate RSU client to SiPSVC V3

Migrate all the RSU related commands to SiPSVC V3
framework.

Change-Id: I3303ca9ad81e412cc9543e0d50c1d7ea64dcc1f6
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): support generic mailbox command in SiPSVC V3

Support generic mailbox command in the SiPSVC V3 framework
and add filter to avoid executing FCS related commands in
the generic mailbox form

fix(intel): support generic mailbox command in SiPSVC V3

Support generic mailbox command in the SiPSVC V3 framework
and add filter to avoid executing FCS related commands in
the generic mailbox format.

Change-Id: I682da2d37c68773ef34194abd6d49c52ddc5c26e
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(intel): support IO96B ECC Error Injection via SMC call

Add SMC call for IO96B ECC error injection, write dummy data
to DDR and read back. This is required to do from ATF,because
the error injec

feat(intel): support IO96B ECC Error Injection via SMC call

Add SMC call for IO96B ECC error injection, write dummy data
to DDR and read back. This is required to do from ATF,because
the error injection from Linux kernel is causing inconsitent
behaviour and sometimes causing memory crash.

Change-Id: I62f9dca319ea6a7ddbdbb7cc2965a0a4e2d41ab6
Signed-off-by: Rabara, Niravkumar L <niravkumar.l.rabara@intel.com>
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(fvp): add FVP_HW_CONFIG_ADDR make variable

Add a new variable that can be optionally set when calling `make`
to allow hw_config (such as DTB) to exist at a specified address.
Prior to this chan

feat(fvp): add FVP_HW_CONFIG_ADDR make variable

Add a new variable that can be optionally set when calling `make`
to allow hw_config (such as DTB) to exist at a specified address.
Prior to this change, the location was hardcoded to 0x82000000, which
could be overwritten if a preceeding image is large enough.
This new variable acts such that if it is unset, the behaviour
is exactly as before this patch, and if it is set, then the value
given is the hw-config's secondary-load-address value in the
fvp_fw_config DT.

Change-Id: I0b5158ef8c089b04078f2e9bb4408f03107591a5
Signed-off-by: emily.boarer@arm.com

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fix(ti): remove validate_power_state definition

validate_power_state should not be defined since CPU suspend is not yet
supported.

Defining the validate_power_state function without any meaningful

fix(ti): remove validate_power_state definition

validate_power_state should not be defined since CPU suspend is not yet
supported.

Defining the validate_power_state function without any meaningful logic
caused a bug where a crash would happen if a device tried to enter a power
state that was not yet supported by TFA. This is because
validate_power_state would return a pass when the state was not properly
checked.

Removing the validate_power_state definition disables the
PSCI_CPU_SUSPEND_AARCH64 capability which will prevent the HLOS from
trying to suspend the CPU all together. This will fix the aforementioned
bug from occurring.

Fixes: 2e9c9e829964 ("ti: k3: common: Add PSCI stubs")
Change-Id: I3bbbd228fbddea64e72f0cf50afc6b25fb6d317c
Signed-off-by: Kendall Willis <k-willis@ti.com>

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fix(fvp): avoid stack usage in check_cpupwrctrl_el1_is_available()

The function is called from assembly language before the stack is set
up. This fix prevents accessing unmapped memory at 0xffffffff

fix(fvp): avoid stack usage in check_cpupwrctrl_el1_is_available()

The function is called from assembly language before the stack is set
up. This fix prevents accessing unmapped memory at 0xffffffff_ffffffxx
by not storing the midr_no_cpupwrctl array on the stack.

Change-Id: I920e32c34bddf86a1dbf05b7115026413483b3c1
Signed-off-by: Linus Nielsen <linus@haxx.se>

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fix(versal2): fix offsets for apu pcil

The current APU_PCIL offsets for disabling power down and wakeup
interrupts are incorrect. The cpuid passed to the register offset
macro is linear (0-8), but t

fix(versal2): fix offsets for apu pcil

The current APU_PCIL offsets for disabling power down and wakeup
interrupts are incorrect. The cpuid passed to the register offset
macro is linear (0-8), but the actual register offsets are
non-linear: 0, 1, 4, 5, 8, 9, 12, 13. As a result, the system
mistakenly disables wakeup and power down interrupts for other
cores. So convert the linear cpuid to a non-linear mapping and
update the APU_PCIL offset macros accordingly.

Change-Id: Ifd823f51d70d9d03fa87cc35ccc733a462eae36a
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal2): initialize counter-timer frequency register

During initialization CNTFRQ_EL0 value is not getting updated and
its remaining 0. Because of that Linux is not able to get system
timer fre

fix(versal2): initialize counter-timer frequency register

During initialization CNTFRQ_EL0 value is not getting updated and
its remaining 0. Because of that Linux is not able to get system
timer frequency and cpu idle with cpu power down state is not
working. So update CNTFRQ_EL0 value during initialization.

Change-Id: I238f67521bbc338c433ce18f60df51efc4c5f387
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal2): use common function to get system counter frequency

Currently, the IOU_SCNTR system counter frequency value is not read from
plat_get_syscnt_freq2(), and it returns the local cpu_freq,

fix(versal2): use common function to get system counter frequency

Currently, the IOU_SCNTR system counter frequency value is not read from
plat_get_syscnt_freq2(), and it returns the local cpu_freq, which is
incorrect. Use the common plat_get_syscnt_freq2() to read the IOU_SCNTR
frequency register and return the correct value.

Change-Id: I277dc6a2e4acd1acd3f048aaf242a3580d06e1c8
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal2): align IOU_SCNTR base address macro name with other platforms

Renamed the IOU_SCNTR base address macro to match the naming
convention used in Versal and Versal NET. This ensures
consist

fix(versal2): align IOU_SCNTR base address macro name with other platforms

Renamed the IOU_SCNTR base address macro to match the naming
convention used in Versal and Versal NET. This ensures
consistency across platforms and enables the use of a common
function for getting and setting the system counter-timer
frequency.

Change-Id: I257a1086d77350858d63859b0fbe6e2b47deb9e5
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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Merge changes from topic "st_fixes" into integration

* changes:
fix(st-iwdg): remove num_irq
fix(st-drivers): remove useless field in fixed regul
fix(st-bsec): remove useless defines in BSEC3

Merge changes from topic "st_fixes" into integration

* changes:
fix(st-iwdg): remove num_irq
fix(st-drivers): remove useless field in fixed regul
fix(st-bsec): remove useless defines in BSEC3
fix(st-bsec): rename OTPSR field
fix(st-crypto): do not set IPRST if BUSY flag is present
fix(st-ddr): bad refresh update level toggle sequence
fix(st-ddr): remove TODO in STM32MP2 driver
fix(stm32mp2): correct typo in definition header

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feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32

feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32MP21,
STM32MP23 and STM32MP25 flags.
STM32MP23 will use the same RCC clock compatible of STM32MP25 SoC.

Change-Id: I6422cd0553067dc92f80da1ad8ec78cadf2432bb
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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refactor(stm32mp2): update display of reset reason

Update the check of reset reason management, update displayed string
aligned with reference manual (por_rstn/bor_rstn/Pin reset), add some
missing

refactor(stm32mp2): update display of reset reason

Update the check of reset reason management, update displayed string
aligned with reference manual (por_rstn/bor_rstn/Pin reset), add some
missing reset reason (C1RST) and reuse string to reduce the size of BL2.

Change-Id: I343a46d69bf0447cafed684eab1b2e812e08ab3a
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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