fix(zynqmp): workaround issue around cntpct_el0

cntvct_el0 after power up has an architecturally UNKNOWN value.
In ZynqMP case the value is very high (e.g. 0xefffffe80d4de62d).
At best value should

fix(zynqmp): workaround issue around cntpct_el0

cntvct_el0 after power up has an architecturally UNKNOWN value.
In ZynqMP case the value is very high (e.g. 0xefffffe80d4de62d).
At best value should be 0 because it is used for time measuring when
systemd analyze command is called (via storing it in UEFI variables).
As a workaround for this issue use cntvoff_el2 to record offset from actual value which clears cntvct_el0.
There could be different way how to achieve this behavior but till that
time use this workaround to fix systemd analyze behavior.

Change-Id: Ie43096bb33bb0e02c8cac07f965610b4565e141c
Signed-off-by: Michal Simek <michal.simek@amd.com>

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refactor(versal2): guard handoff logic w/ build flag

Prepare for environments where the Firmware Handoff (LibTL) submodule
may not be available. Wrap all Transfer List dependent logic in `#if
TRANSF

refactor(versal2): guard handoff logic w/ build flag

Prepare for environments where the Firmware Handoff (LibTL) submodule
may not be available. Wrap all Transfer List dependent logic in `#if
TRANSFER_LIST` guards, ensuring the platform can build and run without
the submodule.

This is useful for builds not integrating the firmware handoff
mechanism.

Change-Id: Ia34bc0f4d352a3014c71eda6589c0f3e0a107ca0
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(qemu): guard handoff logic w/ build flag

Prepare for environments where the Firmware Handoff (LibTL)
submodule may not be available. Wrap all Transfer List dependent logic
in `#if TRANSFER

refactor(qemu): guard handoff logic w/ build flag

Prepare for environments where the Firmware Handoff (LibTL)
submodule may not be available. Wrap all Transfer List dependent logic
in `#if TRANSFER_LIST` guards, ensuring QEMU can build and run without
the submodule.

This is useful for builds not integrating the firmware handoff
mechanism.

Change-Id: I0be3773bf300b02cd3beccf738a021925e3c53c6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(s32g274a): move fip in a dedicated partition

Modify the deployment method for TF-A binaries on the SD card. To
simplify deployment, BL2 will be decorated with an IVT, making it a
bootable image

feat(s32g274a): move fip in a dedicated partition

Modify the deployment method for TF-A binaries on the SD card. To
simplify deployment, BL2 will be decorated with an IVT, making it a
bootable image, while fip.bin will be deployed as a raw MBR partition on
the SD card. This approach allows the FIP location to be auto-discovered
based on information found in the MBR. The partition ID where the image
is stored is set to partition zero but can be changed using the FIP_PART
makefile parameter. The GPT header cannot be used instead of MBR due to
the boot header on the S32G274A, which may overlap with the GPT reserved
area.

Change-Id: I26746023dba7788613a74ae69c86124b450e6bdb
Co-developed-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Co-developed-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): initialize the IO buffer

Define and initialize the IO buffer that will be used by the uSDHC
driver to load images from the SD card.

Change-Id: I8d9712b1243a58fd6830f2682edbb9e661

feat(s32g274ardb): initialize the IO buffer

Define and initialize the IO buffer that will be used by the uSDHC
driver to load images from the SD card.

Change-Id: I8d9712b1243a58fd6830f2682edbb9e661d2f6b5
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): initialize the uSDHC driver

S32G2 and IMX share the same uSDHC controller. Therefore, it is
initialized during BL2 to facilitate the loading of subsequent boot
stages.

Change-Id:

feat(s32g274ardb): initialize the uSDHC driver

S32G2 and IMX share the same uSDHC controller. Therefore, it is
initialized during BL2 to facilitate the loading of subsequent boot
stages.

Change-Id: I223904c24a14a89ef676626b54a5937f39a17eda
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): set the system counter rate

Generic timer initialization at the BL2 stage is incomplete without
configuring the system counter frequency. This configuration is
performed by the PS

feat(s32g274ardb): set the system counter rate

Generic timer initialization at the BL2 stage is incomplete without
configuring the system counter frequency. This configuration is
performed by the PSCI layer in BL31.

Change-Id: I134cffe47819061f1608386cf98a39014cd12396
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): init the generic timer for BL2

The generic timer must be initialized during BL2 because the uSDHC
driver, which will be enabled in subsequent commits, requires it for
delays.

Cha

feat(s32g274ardb): init the generic timer for BL2

The generic timer must be initialized during BL2 because the uSDHC
driver, which will be enabled in subsequent commits, requires it for
delays.

Change-Id: Ia09b3d3565a09ace7389d2e063af1185cc80fa27
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes I2af839ae,Ifd0c7b4e,I56763cb4,I93aec580,Icbd43503, ... into integration

* changes:
docs(fvp): add GICv5 build instructions and limitations
feat(fvp): add GICv5 support
feat(gicv5

Merge changes I2af839ae,Ifd0c7b4e,I56763cb4,I93aec580,Icbd43503, ... into integration

* changes:
docs(fvp): add GICv5 build instructions and limitations
feat(fvp): add GICv5 support
feat(gicv5): probe components
feat(gicv5): initialise the IWB
feat(gicv5): initialise the IRS
feat(gicv5): assign interrupt sources to appropriate security states
feat(gicv5): add a barebones GICv5 driver
feat(gicv5): add support for building with gicv5

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docs(fvp): add GICv5 build instructions and limitations

Add documentation for enabling GICv5 support in the FVP platform,
including required build options and guidance on usage. Also document
curren

docs(fvp): add GICv5 build instructions and limitations

Add documentation for enabling GICv5 support in the FVP platform,
including required build options and guidance on usage. Also document
current limitations and known constraints.

Introduce build-time checks to ensure incompatible configurations
(e.g., with SPMD or RMMD) fail early with a clear error message.

Initial GICv5 support in FVP is intended to facilitate early Linux
kernel bring-up and to assist with upstream kernel patch development.

Note: This patch is a temporary measure and should be reverted once
proper and complete GICv5 support is upstreamed in TF-A.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2af839aec600040dfde75d74d02eff5a57ecda4e

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feat(fvp): add GICv5 support

Factors out GICv3 specific code and replace it with GICv5. This can be
selected with FVP_USE_GIC_DRIVER=FVP_GICV5. Specifically, the FCONF
logic does not apply to GICv5

feat(fvp): add GICv5 support

Factors out GICv3 specific code and replace it with GICv5. This can be
selected with FVP_USE_GIC_DRIVER=FVP_GICV5. Specifically, the FCONF
logic does not apply to GICv5 as the bindings are completely different.

This patch does not include a device tree. This will be added at a later
date.

Change-Id: Ifd0c7b4e0bc2ea1e53a6779ab4c50c4aec39dafb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(fvp): workaround when PCIe 2 region is not present in DTB" into integration

feat(gicv5): add a barebones GICv5 driver

This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the nec

feat(gicv5): add a barebones GICv5 driver

This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the necessary hooks are populated.

Notably, SCR_EL3.FIQ becomes RES1 as GICv5 behaves in a similar manner
to a GICv3 with FIQ set.

Change-Id: Idae52b9df97f4ca2996b2dcd1e5efc45478a43f2
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gicv5): add support for building with gicv5

The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support fo

feat(gicv5): add support for building with gicv5

The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support for the latest Armv9 features. As such it is entirely backwards
incompatible with GICv3/v4.

This patch adds the necessary boilerplate to select a build with GICv5.
The GIC has always had two parts. BL31 deals directly with the CPU
interface while platform code is responsible for managing the IRI. In v5
this split is formalised and the CPU interface, FEAT_GCIE, may be
implemented on its own. So reflect this split in our code with
ENABLE_FEAT_GCIE which only affects BL31 and the GICv5 IRI lies in the
generic GIC driver.

No actual functionality yet.

Change-Id: I97a0c3ba708877c213e50e7ef148e3412aa2af90
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(fvp): workaround when PCIe 2 region is not present in DTB

This patch applies a workaround to the RMM manifest when the DT
does not specify the 2nd PCIe region. As per FVP RevC memory map [1],
th

fix(fvp): workaround when PCIe 2 region is not present in DTB

This patch applies a workaround to the RMM manifest when the DT
does not specify the 2nd PCIe region. As per FVP RevC memory map [1],
there are 2 PCIe regions but the upstream FVP DT sourced from
kernel.org does not have this region specified. Temporarily
workaround this issue in FVP platform layer till the upstream DT is
fixed.

Note that the DT in `fdts` folder of TF-A source tree already has the
2 regions specified.

[1] https://developer.arm.com/documentation/100966/1101-00/Programming-Reference-for-Base-FVPs/Base---memory

Change-Id: If220e2dbeff00a1bf6eccadbb0ebb661b9c5e529
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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fix(nxp-crypto): restricts generating nxp_mkvb via ns-world

Master-key-verification-blob (MKVB) value generated on request from
the secure world, is same to the MKVB value generated on request from

fix(nxp-crypto): restricts generating nxp_mkvb via ns-world

Master-key-verification-blob (MKVB) value generated on request from
the secure world, is same to the MKVB value generated on request from
Normal world. Leading to the leak og MKVB to non-secure world.

Fix to prevent MKVB generation for requests originating from non-secure
world.
- For non-secure world, this SMC is return failure.

Additional fix for bound-check before continuing to generate the MKVB.

Change-Id: I9940b4dfe33289c2d57595a2a08acff29a12c974
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>

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Merge changes Ie23e8ae5,I4d142cb0,I528a1117 into integration

* changes:
feat(mt8189): add pmic driver
feat(mt8189): add PWRAP driver
feat(mt8189): add SPMI driver

Merge "fix(mt8195): fix variable may be used uninitialized error" into integration

Merge "fix(mt8188): fix variable may be used uninitialized error" into integration

Merge changes from topic "validate node ID in PM events" into integration

* changes:
fix(versal2): validate Node ID in PM callback events
fix(xilinx): validate Node ID in PM callback events
fi

Merge changes from topic "validate node ID in PM events" into integration

* changes:
fix(versal2): validate Node ID in PM callback events
fix(xilinx): validate Node ID in PM callback events
fix(xilinx): add macro to extract node class from node ID

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Merge "fix(allwinner): fix variable may be used uninitialized error" into integration

feat(mt8189): add pmic driver

1. add pmic shutdown/reset function
2. add pmic low power setting api

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ie23e8ae50a6

feat(mt8189): add pmic driver

1. add pmic shutdown/reset function
2. add pmic low power setting api

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ie23e8ae50a67be07f9025d69335c26b9569b3d70

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feat(mt8189): add PWRAP driver

Add PWRAP driver for mt6365 pmic communication

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I4d142cb020f0e1b0372f7ef2ba1eb0328

feat(mt8189): add PWRAP driver

Add PWRAP driver for mt6365 pmic communication

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I4d142cb020f0e1b0372f7ef2ba1eb03287cbcd8f

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feat(mt8189): add SPMI driver

Add SPMI driver for PMIC communication

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I528a111791798cc442dbd43e56eddfe91735be2e

Merge changes I54d18f01,I4e06c8a7,Ib5fc7dcd,Id5db5558,Ib941a04a into integration

* changes:
feat(st): adapt .stm32 file creation for clang
feat(st): adapt stm32 linker scripts for clang
feat(s

Merge changes I54d18f01,I4e06c8a7,Ib5fc7dcd,Id5db5558,Ib941a04a into integration

* changes:
feat(st): adapt .stm32 file creation for clang
feat(st): adapt stm32 linker scripts for clang
feat(st): update stm32 linker scripts
fix(st): mark INCBIN-generated sections as SHF_ALLOC
feat(st): remove unsupported option for clang

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