| 15e54af3 | 20-Aug-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "SPM: Add third cactus partition to manifests" into integration |
| e168b66d | 19-Aug-2020 |
André Przywara <andre.przywara@arm.com> |
Merge changes from topic "aw_drivevbus" into integration
* changes: plat/allwinner: Only enable DRIVEVBUS if really needed plat/allwinner: Use common gicv2.mk |
| e7d344de | 16-Aug-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
libc/memset: Implement function in assembler
Trace analysis of FVP_Base_AEMv8A model running in Aarch32 mode with the build options listed below: TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 ARM_ROTPK_LOCATI
libc/memset: Implement function in assembler
Trace analysis of FVP_Base_AEMv8A model running in Aarch32 mode with the build options listed below: TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem shows that when auth_signature() gets called 71.84% of CPU execution time is spent in memset() function written in C using single byte write operations, see lib\libc\memset.c. This patch replaces C memset() implementation with assembler version giving the following results: - for Aarch32 in auth_signature() call memset() CPU time reduced to 24.84%. - Number of CPU instructions executed during TF-A boot stage before start of BL33 in RELEASE builds: ---------------------------------------------- | Arch | C | assembler | % | ---------------------------------------------- | Aarch32 | 2073275460 | 1487400003 | -28.25 | | Aarch64 | 2056807158 | 1244898303 | -39.47 | ---------------------------------------------- The patch also replaces memset.c with aarch64/memset.S in plat\nvidia\tegra\platform.mk.
Change-Id: Ifbf085a2f577a25491e2d28446ee95a4ac891597 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| 9de91c75 | 17-Jul-2020 |
Ruari Phipps <ruari.phipps@arm.com> |
SPM: Add third cactus partition to manifests
Add information about the third partition so it can be loaded into SPM when running the tests
Signed-off-by: Ruari Phipps <ruari.phipps@arm.com> Change-
SPM: Add third cactus partition to manifests
Add information about the third partition so it can be loaded into SPM when running the tests
Signed-off-by: Ruari Phipps <ruari.phipps@arm.com> Change-Id: I5544e88df391ef294ddf6b5750d468d3e74892b1
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| 572dea85 | 19-Aug-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat: qti: Fix build failure" into integration |
| fb9212be | 22-Jul-2020 |
Jacky Bai <ping.bai@nxp.com> |
plat: imx8m: Correct the imr mask reg offset
The number of gpc imr mask reg & the offset is different on some SOC, so correct it & replace the magic number with macro define.
Signed-off-by: Jacky B
plat: imx8m: Correct the imr mask reg offset
The number of gpc imr mask reg & the offset is different on some SOC, so correct it & replace the magic number with macro define.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ic701675cdd92e043dcd7f06722f2e871068aec74
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| 9eb1bb63 | 09-Dec-2019 |
Jacky Bai <ping.bai@nxp.com> |
plat: imx8m: Keep A53 PLAT on in wait mode(ret)
Keep A53 PLAT(SCU) power domain on in wait mode(ret). RBC count only need to be set in PLAT OFF mode, so change it accordingly.
Signed-off-by: Jacky
plat: imx8m: Keep A53 PLAT on in wait mode(ret)
Keep A53 PLAT(SCU) power domain on in wait mode(ret). RBC count only need to be set in PLAT OFF mode, so change it accordingly.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ie55e25c8210d298506fc4dca7a9653583db45e0c
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| 9ce37110 | 19-Aug-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "qemu/qemu_sbsa: enable SPM support" into integration |
| 5a32a033 | 19-Aug-2020 |
Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: platform: Include GICv2 makefile
This patch update each Intel's platform makefiles to include GICv2 makefile instead of manually sourcing individual c files. This aligns with latest changes f
intel: platform: Include GICv2 makefile
This patch update each Intel's platform makefiles to include GICv2 makefile instead of manually sourcing individual c files. This aligns with latest changes from commit #1322dc94f7.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib1f446a6fc578f73a9ef86f9708ddf12d7d75f48
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| 43d22073 | 06-Aug-2019 |
David Pu <dpu@nvidia.com> |
Tegra: platform: add function to check t194 chip
This patch adds tegra_chipid_is_t194() function to check if it is a Tegra 194 chip.
Change-Id: I6da6d3a2c9676b748931e42fde1b174cbcb4fd40 Signed-off-
Tegra: platform: add function to check t194 chip
This patch adds tegra_chipid_is_t194() function to check if it is a Tegra 194 chip.
Change-Id: I6da6d3a2c9676b748931e42fde1b174cbcb4fd40 Signed-off-by: David Pu <dpu@nvidia.com>
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| 57e92daf | 08-Aug-2019 |
David Pu <dpu@nvidia.com> |
Tegra: common: make plat_psci_ops routines static
This patch makes Tegra platform psci ops routines to static. These routines are called by PSCI framework and no external linkage is necessary. This
Tegra: common: make plat_psci_ops routines static
This patch makes Tegra platform psci ops routines to static. These routines are called by PSCI framework and no external linkage is necessary. This patch also fixes MISRA C-2012 Rule 8.6 violations.
Change-Id: Idd2381809f76dc0fd578c1c92c0f8eea124f2e88 Signed-off-by: David Pu <dpu@nvidia.com>
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| 6a2426a9 | 11-Jun-2020 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
qemu/qemu_sbsa: enable SPM support
Enable the spm_mm framework for the qemu_sbsa platform. Memory layout required for spm_mm is created in secure SRAM.
Co-developed-by: Fu Wei <fu.wei@linaro.org> S
qemu/qemu_sbsa: enable SPM support
Enable the spm_mm framework for the qemu_sbsa platform. Memory layout required for spm_mm is created in secure SRAM.
Co-developed-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
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| 86ba5853 | 14-Jul-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
Add wrapper for AT instruction
In case of AT speculative workaround applied, page table walk is disabled for lower ELs (EL1 and EL0) in EL3. Hence added a wrapper function which temporarily enables
Add wrapper for AT instruction
In case of AT speculative workaround applied, page table walk is disabled for lower ELs (EL1 and EL0) in EL3. Hence added a wrapper function which temporarily enables page table walk to execute AT instruction for lower ELs and then disables page table walk.
Execute AT instructions directly for lower ELs (EL1 and EL0) assuming page table walk is enabled always when AT speculative workaround is not applied.
Change-Id: I4ad4c0bcbb761448af257e9f72ae979473c0dde8 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 3f34663f | 04-Aug-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
plat/arm: juno: Implement methods to retrieve soc-id information
Implemented platform functions to retrieve the soc-id information for juno platform
Change-Id: Ie677120710b45e202a2d63a954459ece8a64
plat/arm: juno: Implement methods to retrieve soc-id information
Implemented platform functions to retrieve the soc-id information for juno platform
Change-Id: Ie677120710b45e202a2d63a954459ece8a64b353 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| ed9653ff | 04-Aug-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
plat/arm: fvp: Implement methods to retrieve soc-id information
Implemented platform functions to retrieve the soc-id information for FVP platform.
Change-Id: Id3df02ab290a210310e8d34ec9d706a59d817
plat/arm: fvp: Implement methods to retrieve soc-id information
Implemented platform functions to retrieve the soc-id information for FVP platform.
Change-Id: Id3df02ab290a210310e8d34ec9d706a59d817517 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 7f03d80d | 04-Aug-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
plat/arm: remove common code for soc-id feature
Removed common code for soc-id feature which is applicable for all arm platforms.
In subsequent patches, added a platform based functions for FVP and
plat/arm: remove common code for soc-id feature
Removed common code for soc-id feature which is applicable for all arm platforms.
In subsequent patches, added a platform based functions for FVP and Juno to retrieve the soc-id information.
Change-Id: Idb632a935758a6caff2ca03a6eab8f663da8a93a Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 752ff3bf | 17-Aug-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
plat: qti: Fix build failure
Fixed build failure due to the commit:905f93c77 by removing the inclusion of non-existent 'stdinit.h' file.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> C
plat: qti: Fix build failure
Fixed build failure due to the commit:905f93c77 by removing the inclusion of non-existent 'stdinit.h' file.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I8e3ca69c016b7a2354c58c4d384a492631c36286
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| 0d4ad1fe | 17-Aug-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "plat/arm: Use common build flag for using generic sp804 driver" into integration |
| fddfb3ba | 12-Aug-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
plat/arm: Use common build flag for using generic sp804 driver
SP804 TIMER is not platform specific, and current code base adds multiple defines to use this driver. Like FVP_USE_SP804_TIMER and FVP_
plat/arm: Use common build flag for using generic sp804 driver
SP804 TIMER is not platform specific, and current code base adds multiple defines to use this driver. Like FVP_USE_SP804_TIMER and FVP_VE_USE_SP804_TIMER.
This patch removes platform specific build flag and adds generic flag `USE_SP804_TIMER` to be set to 1 by platform if needed.
Change-Id: I5ab792c189885fd1b98ddd187f3a38ebdd0baba2 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| 9bc28a5e | 02-Aug-2020 |
Andre Przywara <andre.przywara@arm.com> |
plat/allwinner: Use common gicv2.mk
Compiling BL31 for the Allwinner platform now produces a message about the deprecation of gic_common.c. Follow the advice and use include gicv2.mk instead.
Colle
plat/allwinner: Use common gicv2.mk
Compiling BL31 for the Allwinner platform now produces a message about the deprecation of gic_common.c. Follow the advice and use include gicv2.mk instead.
Collect all includes at the beginning of the file on the way.
Change-Id: Iee46e21a630bfa831d28059f09aa7b049eb554bb Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 1b662661 | 16-Aug-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "stm32mp1: use newly introduced GICv2 makefile" into integration |
| 01096cac | 14-Aug-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge changes from topic "tegra-downstream-07092020" into integration
* changes: Tegra: memctrl: remove unused TZRAM setup function Tegra: reorganize drivers and lib folders |
| 33c91baf | 07-Aug-2020 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: use newly introduced GICv2 makefile
Include the GICv2 makefile in STM32MP1 SP_min makefile, and use ${GICV2_SOURCES} instead of taking drivers/arm/gic files directly.
Change-Id: Ibcaed5b0
stm32mp1: use newly introduced GICv2 makefile
Include the GICv2 makefile in STM32MP1 SP_min makefile, and use ${GICV2_SOURCES} instead of taking drivers/arm/gic files directly.
Change-Id: Ibcaed5b0bd17f6d8cf200e208c11cc10cd6d2ee5 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| b693fbf4 | 14-Aug-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "sp_dual_signing" into integration
* changes: SPM: Add owner field to cactus secure partitions SPM: Alter sp_gen.mk entry depending on owner of partition plat/arm: ena
Merge changes from topic "sp_dual_signing" into integration
* changes: SPM: Add owner field to cactus secure partitions SPM: Alter sp_gen.mk entry depending on owner of partition plat/arm: enable support for Plat owned SPs
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| ad86d35a | 11-Aug-2020 |
Ruari Phipps <ruari.phipps@arm.com> |
SPM: Add owner field to cactus secure partitions
For supporting dualroot CoT for Secure Partitions a new optional field "owner" is introduced which will be used to sign the SP with corresponding sig
SPM: Add owner field to cactus secure partitions
For supporting dualroot CoT for Secure Partitions a new optional field "owner" is introduced which will be used to sign the SP with corresponding signing domain. To demonstrate its usage, this patch adds owners to cactus Secure Partitions.
Signed-off-by: Ruari Phipps <ruari.phipps@arm.com> Change-Id: I7b760580355fc92edf5402cecc38c38125dc1cae
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