History log of /rk3399_ARM-atf/plat/ (Results 4826 – 4850 of 8868)
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54b590ec01-Dec-2020 Masato Fukumori <masato.fukumori@linaro.org>

qemu/qemu_sbsa: increase SHARED_RAM_SIZE

Increase SHARED_RAM_SIZE in sbsa_qemu platform from 4KB to 8KB.

sbsa_qemu uses SHARED_RAM for mail box and hold state of each cpus. If
qemu is configured wi

qemu/qemu_sbsa: increase SHARED_RAM_SIZE

Increase SHARED_RAM_SIZE in sbsa_qemu platform from 4KB to 8KB.

sbsa_qemu uses SHARED_RAM for mail box and hold state of each cpus. If
qemu is configured with 512 cpus, region size used by qemu is greater
than 4KB.

Signed-off-by: Masato Fukumori <masato.fukumori@linaro.org>
Change-Id: I639e44e89335249d385cdc339350f509e9bd5e36

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826ba36320-Nov-2020 Christoph Müllner <christophm30@gmail.com>

rockchip: Add support for the stack protector

It uses the system timer as "entropy" source in the same
way as QEMU, layerscape and others.

Change-Id: Icda17b78e85255bea96109ca2ee0e091187d62ac
Signe

rockchip: Add support for the stack protector

It uses the system timer as "entropy" source in the same
way as QEMU, layerscape and others.

Change-Id: Icda17b78e85255bea96109ca2ee0e091187d62ac
Signed-off-by: Christoph Müllner <christophm30@gmail.com>

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25bbbd2d23-Oct-2020 Javier Almansa Sobrino <javier.almansasobrino@arm.com>

Add support for Neoverse-N2 CPUs.

Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8

Add support for Neoverse-N2 CPUs.

Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad

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9acf573630-Nov-2020 Manish Pandey <manish.pandey2@arm.com>

Merge changes from topic "xilinx-pm-mainline-linux" into integration

* changes:
zynqmp: pm: update error codes to match Linux and PMU Firmware
zynqmp: pm: Filter errors related to clock gate per

Merge changes from topic "xilinx-pm-mainline-linux" into integration

* changes:
zynqmp: pm: update error codes to match Linux and PMU Firmware
zynqmp: pm: Filter errors related to clock gate permissions

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441e7f4827-Nov-2020 Manish Pandey <manish.pandey2@arm.com>

Merge "mediatek: mt8183: add timer V20 compensation" into integration

9272a8fd23-Nov-2020 Manish Pandey <manish.pandey2@arm.com>

Merge "plat:qti Mandate SMC implementaion" into integration

7cf307d220-Nov-2020 Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge "plat/nvidia: tegra: Rename SMC API" into integration

5f14ca9920-Nov-2020 Tanmay Jagdale <tanmay.jagdale@linaro.org>

plat/qemu_sbsa: Include libraries for Cortex-A72

Include libraries needed to emulate Cortex-A72 on
sbsa-ref target of QEMU.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Change-Id: I98c

plat/qemu_sbsa: Include libraries for Cortex-A72

Include libraries needed to emulate Cortex-A72 on
sbsa-ref target of QEMU.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Change-Id: I98cf17b1662c70898977a841af07e07b5cfca8ba

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840fa94a19-Nov-2020 Manish V Badarkhe <Manish.Badarkhe@arm.com>

plat/nvidia: tegra: Rename SMC API

Renamed SMC API from "plat_smccc_feature_available" to
"plat_is_smccc_feature_available" as per the current implementation.

Signed-off-by: Manish V Badarkhe <Mani

plat/nvidia: tegra: Rename SMC API

Renamed SMC API from "plat_smccc_feature_available" to
"plat_is_smccc_feature_available" as per the current implementation.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib0fa400816fba61039c2029a9e127501a6a36811

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7a0f795e19-Nov-2020 Saurabh Gorecha <sgorecha@codeaurora.org>

plat:qti Mandate SMC implementaion

renamed smcc api with correct name plat_is_smccc_feature_available

Change-Id: I277ece02bffc2caa065256576c1a047dfcde1c92
Signed-off-by: Saurabh Gorecha <sgorecha@

plat:qti Mandate SMC implementaion

renamed smcc api with correct name plat_is_smccc_feature_available

Change-Id: I277ece02bffc2caa065256576c1a047dfcde1c92
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>

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d22db1b010-Nov-2020 Pali Rohár <pali@kernel.org>

plat: marvell: Update SUBVERSION to match Marvell's forked version

Marvell's TF-A fork has SUBVERSION set to devel-18.12.2.

The only differences between Marvell's devel-18.12.0 and devel-18.12.2
ve

plat: marvell: Update SUBVERSION to match Marvell's forked version

Marvell's TF-A fork has SUBVERSION set to devel-18.12.2.

The only differences between Marvell's devel-18.12.0 and devel-18.12.2
versions are documentation updates and cherry-picked patches from TF-A
upstream repository.

So upstream TF-A has already all changes from Marvell's TF-A devel-18.12.2
fork and therefore update SUBVERSION to reflect this state.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5ce946a5176a5cbf124acd8037392463d586b072

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91bc2da729-Oct-2020 Pali Rohár <pali@kernel.org>

plat: marvell: armada: Add new target mrvl_bootimage

This new target builds boot-image.bin binary as described in documentation.
This image does not contain WTMI image and therefore WTP repository i

plat: marvell: armada: Add new target mrvl_bootimage

This new target builds boot-image.bin binary as described in documentation.
This image does not contain WTMI image and therefore WTP repository is not
required for building.

Having ability to build just this boot-image.bin binary without full
flash-image.bin is useful for A3720 Turris MOX board which does not use
Marvell's WTP and a3700_utils.

To reduce duplicity between a8k and a3k code, define this new target and
also definitions for $(BUILD_PLAT)/$(BOOT_IMAGE) in common include file
marvell_common.mk.

For this purpose it is needed to include plat/marvell/marvell.mk file from
a3700_common.mk unconditionally (and not only when WTP is defined). Now
when common file plat/marvell/marvell.mk does not contain definition for
building $(DOIMAGETOOL), it is possible to move its inclusion at the top of
the a3700_common.mk file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ic58303b37a1601be9a06ff83b7a279cb7cfc8280

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c6a7ab7729-Oct-2020 Pali Rohár <pali@kernel.org>

plat: marvell: armada: a3k: Add support for building $(DOIMAGETOOL)

Current binary wtptp/linux/tbb_linux which is specified in $(DOIMAGETOOL)
variable points to external pre-compiled Marvell x86_64

plat: marvell: armada: a3k: Add support for building $(DOIMAGETOOL)

Current binary wtptp/linux/tbb_linux which is specified in $(DOIMAGETOOL)
variable points to external pre-compiled Marvell x86_64 ELF linux binary
from A3700-utils-marvell WTP repository.

It means that currently it is not possible to compile TF-A for A3720 on
other host platform then linux x86_64.

Part of the A3700-utils-marvell WTP repository is also source code of
$(DOIMAGETOOL) TBB_Linux tool.

This change adds support for building $(DOIMAGETOOL) also for a3k platform.

After running $(MAKE) at appropriate subdirectory of A3700-utils-marvell
WTP repository, compiled TBB_linux tool will appear in WTP subdirectory
wtptp/src/TBB_Linux/release/. So update also $(DOIMAGETOOL) variable to
point to the correct location where TBB_linux was built.

To build TBB_linux it is required to compile external Crypto++ library
which is available at: https://github.com/weidai11/cryptopp.git

User needs to set CRYPTOPP_PATH option to specify path to that library.

After this change it is now possible to build whole firmware for A3720
platform without requirement to use pre-compiled/proprietary x86_64
executable binaries from Marvell.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6f26bd4356778a2f8f730a223067a2e550e6c8e0

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5d9101b312-Nov-2020 David Horstmann <david.horstmann@arm.com>

Fix typos and misspellings

Fix a number of typos and misspellings in TF-A
documentation and comments.

Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: I34c5a28c3af15f28d1ccada4d9

Fix typos and misspellings

Fix a number of typos and misspellings in TF-A
documentation and comments.

Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: I34c5a28c3af15f28d1ccada4d9866aee6af136ee

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e9930d4214-Jul-2020 Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>

plat: xilinx: Use fno-jump-tables flag in CPPFLAGS

From GCC-9 implementation of switch case was generated through jump tables,
because of which we are seeing 1MB increase in rodata section. To reduc

plat: xilinx: Use fno-jump-tables flag in CPPFLAGS

From GCC-9 implementation of switch case was generated through jump tables,
because of which we are seeing 1MB increase in rodata section. To reduce
the size we are recommending to use fno-jump-tables.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I069733610809b8299fbf641f0ae35b359a8afd69

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a8b10c6424-Aug-2018 Davorin Mista <davorin.mista@aggios.com>

zynqmp: pm: update error codes to match Linux and PMU Firmware

All EEMI error codes start with value 2000.

Note: Legacy error codes ARGS (=1) and NOTSUPPORTED (=4) returned by
current ATF code have

zynqmp: pm: update error codes to match Linux and PMU Firmware

All EEMI error codes start with value 2000.

Note: Legacy error codes ARGS (=1) and NOTSUPPORTED (=4) returned by
current ATF code have been left in place.

Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I939afa85957cac88025d82a80f9f6dd49be993b6

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c23cf05324-Aug-2018 Mirela Simonovic <mirela.simonovic@aggios.com>

zynqmp: pm: Filter errors related to clock gate permissions

Linux clock framework cannot properly deal with these errors. When the
error is related to the lack of permissions to control the clock we

zynqmp: pm: Filter errors related to clock gate permissions

Linux clock framework cannot properly deal with these errors. When the
error is related to the lack of permissions to control the clock we
filter the error and report the success to linux. Before recent changes
in clock framework across the stack, this was done in the PMU-FW as a
workaround. Since the PMU-FW now handles clocks and the permissions to
control them using general principles rather than workarounds, it can
no longer distinguish such exceptions and it has to return no-access
error.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I1491a80e472f44e322a542b29a20eb1cb3319802

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8109d2dd29-Oct-2020 Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "Use constant stack size with RECLAIM_INIT_CODE" into integration

271708e029-Oct-2020 Manish Pandey <manish.pandey2@arm.com>

Merge changes from topic "mbox-patches" into integration

* changes:
intel: common: Fix non-MISRA compliant code v2
intel: mailbox: Fix non-MISRA compliant code
intel: mailbox: Mailbox error re

Merge changes from topic "mbox-patches" into integration

* changes:
intel: common: Fix non-MISRA compliant code v2
intel: mailbox: Fix non-MISRA compliant code
intel: mailbox: Mailbox error recovery handling
intel: mailbox: Enable sending large mailbox command
intel: mailbox: Use retry count in mailbox poll
intel: mailbox: Ensure time out duration is predictive
intel: mailbox: Read mailbox response even there is an error
intel: mailbox: Driver now handles larger response
intel: common: Change how mailbox handles job id & buffer
intel: common: Improve readability of mailbox read response
intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB
intel: common: Remove urgent from mailbox async
intel: common: Improve mailbox driver readability

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3ed5606b14-Oct-2020 David Horstmann <david.horstmann@arm.com>

Use constant stack size with RECLAIM_INIT_CODE

Currently, when RECLAIM_INIT_CODE is set, the
stacks are scaled to ensure that the entirety
of the init section can be reclaimed as stack.

This causes

Use constant stack size with RECLAIM_INIT_CODE

Currently, when RECLAIM_INIT_CODE is set, the
stacks are scaled to ensure that the entirety
of the init section can be reclaimed as stack.

This causes an issue in lib/psci/aarch64/psci_helpers.S,
where the stack size is used for cache operations in
psci_do_pwrdown_cache_maintenance(). If the stacks
are scaled, then the PSCI code may fail to invalidate
some of the stack memory before power down.

Resizing stacks is also not good for stability in general,
since code that works with a small number of cores may
overflow the stack when the number of cores is increased.

Change to make every stack be PLATFORM_STACK_SIZE big,
and allow the total stack to be smaller than the
init section.

Any pages of the init section not reclaimed as
stack will be set to read-only and execute-never,
for security.

Change-Id: I10b3884981006431f2fcbec3864c81d4a8c246e8
Signed-off-by: David Horstmann <david.horstmann@arm.com>

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6e97b22428-Oct-2020 Manish Pandey <manish.pandey2@arm.com>

Merge changes from topic "mbox-patches" into integration

* changes:
intel: common: Clean up mailbox and sip header
intel: clear 'PLAT_SEC_ENTRY' in early platform setup

350c04f628-Oct-2020 Manish Pandey <manish.pandey2@arm.com>

Merge changes I07448d85,If85be70b,Ie6802d6d,I67a9abef into integration

* changes:
mediatek: mt8192: add timer support
mediatek: mt8192: Add reboot function for PSCI
mediatek: mt8192: add sys_c

Merge changes I07448d85,If85be70b,Ie6802d6d,I67a9abef into integration

* changes:
mediatek: mt8192: add timer support
mediatek: mt8192: Add reboot function for PSCI
mediatek: mt8192: add sys_cirq driver
mediatek: mt8192: add GPIO driver support

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4a12801803-Jul-2020 Dehui Sun <dehui.sun@mediatek.com>

mediatek: mt8192: add timer support

add timer driver.

Signed-off-by: Dehui Sun <dehui.sun@mediatek.com>
Change-Id: I07448d85a15bb14577b05e4f302860d609420ba7

0f40824702-Jul-2020 Nina Wu <nina-cm.wu@mediatek.com>

mediatek: mt8192: Add reboot function for PSCI

Add system_reset function in psci ops

Change-Id: If85be70b8ae9d6487e02626356f0ff1e78b76de9
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>

b6cec33719-Dec-2019 gtk_pangao <gtk_pangao@mediatek.com>

mediatek: mt8192: add sys_cirq driver

1.add sys_cirq driver
2.add gic api for cirq

Change-Id: Ie6802d6ddcf7dde3412a050736dfdc85f97cb51b
Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com>

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