1 /* 2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * ZynqMP system level PM-API functions for pin control. 9 */ 10 11 #include <string.h> 12 13 #include <arch_helpers.h> 14 #include <plat/common/platform.h> 15 16 #include "pm_api_pinctrl.h" 17 #include "pm_api_sys.h" 18 #include "pm_client.h" 19 #include "pm_common.h" 20 #include "pm_ipi.h" 21 22 #define PINCTRL_VOLTAGE_STATUS_MASK U(0x01) 23 #define PINCTRL_NUM_MIOS U(78) 24 #define MAX_PIN_PER_REG U(26) 25 #define PINCTRL_BANK_ADDR_STEP U(28) 26 27 #define PINCTRL_DRVSTRN0_REG_OFFSET U(0) 28 #define PINCTRL_DRVSTRN1_REG_OFFSET U(4) 29 #define PINCTRL_SCHCMOS_REG_OFFSET U(8) 30 #define PINCTRL_PULLCTRL_REG_OFFSET U(12) 31 #define PINCTRL_PULLSTAT_REG_OFFSET U(16) 32 #define PINCTRL_SLEWCTRL_REG_OFFSET U(20) 33 #define PINCTRL_VOLTAGE_STAT_REG_OFFSET U(24) 34 35 #define IOU_SLCR_BANK1_CTRL5 U(0XFF180164) 36 37 #define PINCTRL_CFG_ADDR_OFFSET(addr, reg, miopin) \ 38 ((addr) + 4 * PINCTRL_NUM_MIOS + PINCTRL_BANK_ADDR_STEP * \ 39 ((miopin) / MAX_PIN_PER_REG) + (reg)) 40 41 #define PINCTRL_PIN_OFFSET(_miopin) \ 42 ((_miopin) - (MAX_PIN_PER_REG * ((_miopin) / MAX_PIN_PER_REG))) 43 44 #define PINCTRL_REGVAL_TO_PIN_CONFIG(_pin, _val) \ 45 (((_val) >> PINCTRL_PIN_OFFSET(_pin)) & 0x1) 46 47 struct pinctrl_function { 48 char name[FUNCTION_NAME_LEN]; 49 uint16_t (*groups)[]; 50 uint8_t regval; 51 }; 52 53 /* Max groups for one pin */ 54 #define MAX_PIN_GROUPS U(13) 55 56 struct zynqmp_pin_group { 57 uint16_t (*groups)[]; 58 }; 59 60 static struct pinctrl_function pinctrl_functions[MAX_FUNCTION] = { 61 [PINCTRL_FUNC_CAN0] = { 62 .name = "can0", 63 .regval = 0x20, 64 .groups = &((uint16_t []) { 65 PINCTRL_GRP_CAN0_0, 66 PINCTRL_GRP_CAN0_1, 67 PINCTRL_GRP_CAN0_2, 68 PINCTRL_GRP_CAN0_3, 69 PINCTRL_GRP_CAN0_4, 70 PINCTRL_GRP_CAN0_5, 71 PINCTRL_GRP_CAN0_6, 72 PINCTRL_GRP_CAN0_7, 73 PINCTRL_GRP_CAN0_8, 74 PINCTRL_GRP_CAN0_9, 75 PINCTRL_GRP_CAN0_10, 76 PINCTRL_GRP_CAN0_11, 77 PINCTRL_GRP_CAN0_12, 78 PINCTRL_GRP_CAN0_13, 79 PINCTRL_GRP_CAN0_14, 80 PINCTRL_GRP_CAN0_15, 81 PINCTRL_GRP_CAN0_16, 82 PINCTRL_GRP_CAN0_17, 83 PINCTRL_GRP_CAN0_18, 84 END_OF_GROUPS, 85 }), 86 }, 87 [PINCTRL_FUNC_CAN1] = { 88 .name = "can1", 89 .regval = 0x20, 90 .groups = &((uint16_t []) { 91 PINCTRL_GRP_CAN1_0, 92 PINCTRL_GRP_CAN1_1, 93 PINCTRL_GRP_CAN1_2, 94 PINCTRL_GRP_CAN1_3, 95 PINCTRL_GRP_CAN1_4, 96 PINCTRL_GRP_CAN1_5, 97 PINCTRL_GRP_CAN1_6, 98 PINCTRL_GRP_CAN1_7, 99 PINCTRL_GRP_CAN1_8, 100 PINCTRL_GRP_CAN1_9, 101 PINCTRL_GRP_CAN1_10, 102 PINCTRL_GRP_CAN1_11, 103 PINCTRL_GRP_CAN1_12, 104 PINCTRL_GRP_CAN1_13, 105 PINCTRL_GRP_CAN1_14, 106 PINCTRL_GRP_CAN1_15, 107 PINCTRL_GRP_CAN1_16, 108 PINCTRL_GRP_CAN1_17, 109 PINCTRL_GRP_CAN1_18, 110 PINCTRL_GRP_CAN1_19, 111 END_OF_GROUPS, 112 }), 113 }, 114 [PINCTRL_FUNC_ETHERNET0] = { 115 .name = "ethernet0", 116 .regval = 0x02, 117 .groups = &((uint16_t []) { 118 PINCTRL_GRP_ETHERNET0_0, 119 END_OF_GROUPS, 120 }), 121 }, 122 [PINCTRL_FUNC_ETHERNET1] = { 123 .name = "ethernet1", 124 .regval = 0x02, 125 .groups = &((uint16_t []) { 126 PINCTRL_GRP_ETHERNET1_0, 127 END_OF_GROUPS, 128 }), 129 }, 130 [PINCTRL_FUNC_ETHERNET2] = { 131 .name = "ethernet2", 132 .regval = 0x02, 133 .groups = &((uint16_t []) { 134 PINCTRL_GRP_ETHERNET2_0, 135 END_OF_GROUPS, 136 }), 137 }, 138 [PINCTRL_FUNC_ETHERNET3] = { 139 .name = "ethernet3", 140 .regval = 0x02, 141 .groups = &((uint16_t []) { 142 PINCTRL_GRP_ETHERNET3_0, 143 END_OF_GROUPS, 144 }), 145 }, 146 [PINCTRL_FUNC_GEMTSU0] = { 147 .name = "gemtsu0", 148 .regval = 0x02, 149 .groups = &((uint16_t []) { 150 PINCTRL_GRP_GEMTSU0_0, 151 PINCTRL_GRP_GEMTSU0_1, 152 PINCTRL_GRP_GEMTSU0_2, 153 END_OF_GROUPS, 154 }), 155 }, 156 [PINCTRL_FUNC_GPIO0] = { 157 .name = "gpio0", 158 .regval = 0x00, 159 .groups = &((uint16_t []) { 160 PINCTRL_GRP_GPIO0_0, 161 PINCTRL_GRP_GPIO0_1, 162 PINCTRL_GRP_GPIO0_2, 163 PINCTRL_GRP_GPIO0_3, 164 PINCTRL_GRP_GPIO0_4, 165 PINCTRL_GRP_GPIO0_5, 166 PINCTRL_GRP_GPIO0_6, 167 PINCTRL_GRP_GPIO0_7, 168 PINCTRL_GRP_GPIO0_8, 169 PINCTRL_GRP_GPIO0_9, 170 PINCTRL_GRP_GPIO0_10, 171 PINCTRL_GRP_GPIO0_11, 172 PINCTRL_GRP_GPIO0_12, 173 PINCTRL_GRP_GPIO0_13, 174 PINCTRL_GRP_GPIO0_14, 175 PINCTRL_GRP_GPIO0_15, 176 PINCTRL_GRP_GPIO0_16, 177 PINCTRL_GRP_GPIO0_17, 178 PINCTRL_GRP_GPIO0_18, 179 PINCTRL_GRP_GPIO0_19, 180 PINCTRL_GRP_GPIO0_20, 181 PINCTRL_GRP_GPIO0_21, 182 PINCTRL_GRP_GPIO0_22, 183 PINCTRL_GRP_GPIO0_23, 184 PINCTRL_GRP_GPIO0_24, 185 PINCTRL_GRP_GPIO0_25, 186 PINCTRL_GRP_GPIO0_26, 187 PINCTRL_GRP_GPIO0_27, 188 PINCTRL_GRP_GPIO0_28, 189 PINCTRL_GRP_GPIO0_29, 190 PINCTRL_GRP_GPIO0_30, 191 PINCTRL_GRP_GPIO0_31, 192 PINCTRL_GRP_GPIO0_32, 193 PINCTRL_GRP_GPIO0_33, 194 PINCTRL_GRP_GPIO0_34, 195 PINCTRL_GRP_GPIO0_35, 196 PINCTRL_GRP_GPIO0_36, 197 PINCTRL_GRP_GPIO0_37, 198 PINCTRL_GRP_GPIO0_38, 199 PINCTRL_GRP_GPIO0_39, 200 PINCTRL_GRP_GPIO0_40, 201 PINCTRL_GRP_GPIO0_41, 202 PINCTRL_GRP_GPIO0_42, 203 PINCTRL_GRP_GPIO0_43, 204 PINCTRL_GRP_GPIO0_44, 205 PINCTRL_GRP_GPIO0_45, 206 PINCTRL_GRP_GPIO0_46, 207 PINCTRL_GRP_GPIO0_47, 208 PINCTRL_GRP_GPIO0_48, 209 PINCTRL_GRP_GPIO0_49, 210 PINCTRL_GRP_GPIO0_50, 211 PINCTRL_GRP_GPIO0_51, 212 PINCTRL_GRP_GPIO0_52, 213 PINCTRL_GRP_GPIO0_53, 214 PINCTRL_GRP_GPIO0_54, 215 PINCTRL_GRP_GPIO0_55, 216 PINCTRL_GRP_GPIO0_56, 217 PINCTRL_GRP_GPIO0_57, 218 PINCTRL_GRP_GPIO0_58, 219 PINCTRL_GRP_GPIO0_59, 220 PINCTRL_GRP_GPIO0_60, 221 PINCTRL_GRP_GPIO0_61, 222 PINCTRL_GRP_GPIO0_62, 223 PINCTRL_GRP_GPIO0_63, 224 PINCTRL_GRP_GPIO0_64, 225 PINCTRL_GRP_GPIO0_65, 226 PINCTRL_GRP_GPIO0_66, 227 PINCTRL_GRP_GPIO0_67, 228 PINCTRL_GRP_GPIO0_68, 229 PINCTRL_GRP_GPIO0_69, 230 PINCTRL_GRP_GPIO0_70, 231 PINCTRL_GRP_GPIO0_71, 232 PINCTRL_GRP_GPIO0_72, 233 PINCTRL_GRP_GPIO0_73, 234 PINCTRL_GRP_GPIO0_74, 235 PINCTRL_GRP_GPIO0_75, 236 PINCTRL_GRP_GPIO0_76, 237 PINCTRL_GRP_GPIO0_77, 238 END_OF_GROUPS, 239 }), 240 }, 241 [PINCTRL_FUNC_I2C0] = { 242 .name = "i2c0", 243 .regval = 0x40, 244 .groups = &((uint16_t []) { 245 PINCTRL_GRP_I2C0_0, 246 PINCTRL_GRP_I2C0_1, 247 PINCTRL_GRP_I2C0_2, 248 PINCTRL_GRP_I2C0_3, 249 PINCTRL_GRP_I2C0_4, 250 PINCTRL_GRP_I2C0_5, 251 PINCTRL_GRP_I2C0_6, 252 PINCTRL_GRP_I2C0_7, 253 PINCTRL_GRP_I2C0_8, 254 PINCTRL_GRP_I2C0_9, 255 PINCTRL_GRP_I2C0_10, 256 PINCTRL_GRP_I2C0_11, 257 PINCTRL_GRP_I2C0_12, 258 PINCTRL_GRP_I2C0_13, 259 PINCTRL_GRP_I2C0_14, 260 PINCTRL_GRP_I2C0_15, 261 PINCTRL_GRP_I2C0_16, 262 PINCTRL_GRP_I2C0_17, 263 PINCTRL_GRP_I2C0_18, 264 END_OF_GROUPS, 265 }), 266 }, 267 [PINCTRL_FUNC_I2C1] = { 268 .name = "i2c1", 269 .regval = 0x40, 270 .groups = &((uint16_t []) { 271 PINCTRL_GRP_I2C1_0, 272 PINCTRL_GRP_I2C1_1, 273 PINCTRL_GRP_I2C1_2, 274 PINCTRL_GRP_I2C1_3, 275 PINCTRL_GRP_I2C1_4, 276 PINCTRL_GRP_I2C1_5, 277 PINCTRL_GRP_I2C1_6, 278 PINCTRL_GRP_I2C1_7, 279 PINCTRL_GRP_I2C1_8, 280 PINCTRL_GRP_I2C1_9, 281 PINCTRL_GRP_I2C1_10, 282 PINCTRL_GRP_I2C1_11, 283 PINCTRL_GRP_I2C1_12, 284 PINCTRL_GRP_I2C1_13, 285 PINCTRL_GRP_I2C1_14, 286 PINCTRL_GRP_I2C1_15, 287 PINCTRL_GRP_I2C1_16, 288 PINCTRL_GRP_I2C1_17, 289 PINCTRL_GRP_I2C1_18, 290 PINCTRL_GRP_I2C1_19, 291 END_OF_GROUPS, 292 }), 293 }, 294 [PINCTRL_FUNC_MDIO0] = { 295 .name = "mdio0", 296 .regval = 0x60, 297 .groups = &((uint16_t []) { 298 PINCTRL_GRP_MDIO0_0, 299 END_OF_GROUPS, 300 }), 301 }, 302 [PINCTRL_FUNC_MDIO1] = { 303 .name = "mdio1", 304 .regval = 0x80, 305 .groups = &((uint16_t []) { 306 PINCTRL_GRP_MDIO1_0, 307 PINCTRL_GRP_MDIO1_1, 308 END_OF_GROUPS, 309 }), 310 }, 311 [PINCTRL_FUNC_MDIO2] = { 312 .name = "mdio2", 313 .regval = 0xa0, 314 .groups = &((uint16_t []) { 315 PINCTRL_GRP_MDIO2_0, 316 END_OF_GROUPS, 317 }), 318 }, 319 [PINCTRL_FUNC_MDIO3] = { 320 .name = "mdio3", 321 .regval = 0xc0, 322 .groups = &((uint16_t []) { 323 PINCTRL_GRP_MDIO3_0, 324 END_OF_GROUPS, 325 }), 326 }, 327 [PINCTRL_FUNC_QSPI0] = { 328 .name = "qspi0", 329 .regval = 0x02, 330 .groups = &((uint16_t []) { 331 PINCTRL_GRP_QSPI0_0, 332 END_OF_GROUPS, 333 }), 334 }, 335 [PINCTRL_FUNC_QSPI_FBCLK] = { 336 .name = "qspi_fbclk", 337 .regval = 0x02, 338 .groups = &((uint16_t []) { 339 PINCTRL_GRP_QSPI_FBCLK, 340 END_OF_GROUPS, 341 }), 342 }, 343 [PINCTRL_FUNC_QSPI_SS] = { 344 .name = "qspi_ss", 345 .regval = 0x02, 346 .groups = &((uint16_t []) { 347 PINCTRL_GRP_QSPI_SS, 348 END_OF_GROUPS, 349 }), 350 }, 351 [PINCTRL_FUNC_SPI0] = { 352 .name = "spi0", 353 .regval = 0x80, 354 .groups = &((uint16_t []) { 355 PINCTRL_GRP_SPI0_0, 356 PINCTRL_GRP_SPI0_1, 357 PINCTRL_GRP_SPI0_2, 358 PINCTRL_GRP_SPI0_3, 359 PINCTRL_GRP_SPI0_4, 360 PINCTRL_GRP_SPI0_5, 361 END_OF_GROUPS, 362 }), 363 }, 364 [PINCTRL_FUNC_SPI1] = { 365 .name = "spi1", 366 .regval = 0x80, 367 .groups = &((uint16_t []) { 368 PINCTRL_GRP_SPI1_0, 369 PINCTRL_GRP_SPI1_1, 370 PINCTRL_GRP_SPI1_2, 371 PINCTRL_GRP_SPI1_3, 372 PINCTRL_GRP_SPI1_4, 373 PINCTRL_GRP_SPI1_5, 374 END_OF_GROUPS, 375 }), 376 }, 377 [PINCTRL_FUNC_SPI0_SS] = { 378 .name = "spi0_ss", 379 .regval = 0x80, 380 .groups = &((uint16_t []) { 381 PINCTRL_GRP_SPI0_0_SS0, 382 PINCTRL_GRP_SPI0_0_SS1, 383 PINCTRL_GRP_SPI0_0_SS2, 384 PINCTRL_GRP_SPI0_1_SS0, 385 PINCTRL_GRP_SPI0_1_SS1, 386 PINCTRL_GRP_SPI0_1_SS2, 387 PINCTRL_GRP_SPI0_2_SS0, 388 PINCTRL_GRP_SPI0_2_SS1, 389 PINCTRL_GRP_SPI0_2_SS2, 390 PINCTRL_GRP_SPI0_3_SS0, 391 PINCTRL_GRP_SPI0_3_SS1, 392 PINCTRL_GRP_SPI0_3_SS2, 393 PINCTRL_GRP_SPI0_4_SS0, 394 PINCTRL_GRP_SPI0_4_SS1, 395 PINCTRL_GRP_SPI0_4_SS2, 396 PINCTRL_GRP_SPI0_5_SS0, 397 PINCTRL_GRP_SPI0_5_SS1, 398 PINCTRL_GRP_SPI0_5_SS2, 399 END_OF_GROUPS, 400 }), 401 }, 402 [PINCTRL_FUNC_SPI1_SS] = { 403 .name = "spi1_ss", 404 .regval = 0x80, 405 .groups = &((uint16_t []) { 406 PINCTRL_GRP_SPI1_0_SS0, 407 PINCTRL_GRP_SPI1_0_SS1, 408 PINCTRL_GRP_SPI1_0_SS2, 409 PINCTRL_GRP_SPI1_1_SS0, 410 PINCTRL_GRP_SPI1_1_SS1, 411 PINCTRL_GRP_SPI1_1_SS2, 412 PINCTRL_GRP_SPI1_2_SS0, 413 PINCTRL_GRP_SPI1_2_SS1, 414 PINCTRL_GRP_SPI1_2_SS2, 415 PINCTRL_GRP_SPI1_3_SS0, 416 PINCTRL_GRP_SPI1_3_SS1, 417 PINCTRL_GRP_SPI1_3_SS2, 418 PINCTRL_GRP_SPI1_4_SS0, 419 PINCTRL_GRP_SPI1_4_SS1, 420 PINCTRL_GRP_SPI1_4_SS2, 421 PINCTRL_GRP_SPI1_5_SS0, 422 PINCTRL_GRP_SPI1_5_SS1, 423 PINCTRL_GRP_SPI1_5_SS2, 424 END_OF_GROUPS, 425 }), 426 }, 427 [PINCTRL_FUNC_SDIO0] = { 428 .name = "sdio0", 429 .regval = 0x08, 430 .groups = &((uint16_t []) { 431 PINCTRL_GRP_SDIO0_0, 432 PINCTRL_GRP_SDIO0_1, 433 PINCTRL_GRP_SDIO0_2, 434 PINCTRL_GRP_SDIO0_4BIT_0_0, 435 PINCTRL_GRP_SDIO0_4BIT_0_1, 436 PINCTRL_GRP_SDIO0_4BIT_1_0, 437 PINCTRL_GRP_SDIO0_4BIT_1_1, 438 PINCTRL_GRP_SDIO0_4BIT_2_0, 439 PINCTRL_GRP_SDIO0_4BIT_2_1, 440 PINCTRL_GRP_SDIO0_1BIT_0_0, 441 PINCTRL_GRP_SDIO0_1BIT_0_1, 442 PINCTRL_GRP_SDIO0_1BIT_0_2, 443 PINCTRL_GRP_SDIO0_1BIT_0_3, 444 PINCTRL_GRP_SDIO0_1BIT_0_4, 445 PINCTRL_GRP_SDIO0_1BIT_0_5, 446 PINCTRL_GRP_SDIO0_1BIT_0_6, 447 PINCTRL_GRP_SDIO0_1BIT_0_7, 448 PINCTRL_GRP_SDIO0_1BIT_1_0, 449 PINCTRL_GRP_SDIO0_1BIT_1_1, 450 PINCTRL_GRP_SDIO0_1BIT_1_2, 451 PINCTRL_GRP_SDIO0_1BIT_1_3, 452 PINCTRL_GRP_SDIO0_1BIT_1_4, 453 PINCTRL_GRP_SDIO0_1BIT_1_5, 454 PINCTRL_GRP_SDIO0_1BIT_1_6, 455 PINCTRL_GRP_SDIO0_1BIT_1_7, 456 PINCTRL_GRP_SDIO0_1BIT_2_0, 457 PINCTRL_GRP_SDIO0_1BIT_2_1, 458 PINCTRL_GRP_SDIO0_1BIT_2_2, 459 PINCTRL_GRP_SDIO0_1BIT_2_3, 460 PINCTRL_GRP_SDIO0_1BIT_2_4, 461 PINCTRL_GRP_SDIO0_1BIT_2_5, 462 PINCTRL_GRP_SDIO0_1BIT_2_6, 463 PINCTRL_GRP_SDIO0_1BIT_2_7, 464 END_OF_GROUPS, 465 }), 466 }, 467 [PINCTRL_FUNC_SDIO0_PC] = { 468 .name = "sdio0_pc", 469 .regval = 0x08, 470 .groups = &((uint16_t []) { 471 PINCTRL_GRP_SDIO0_0_PC, 472 PINCTRL_GRP_SDIO0_1_PC, 473 PINCTRL_GRP_SDIO0_2_PC, 474 END_OF_GROUPS, 475 }), 476 }, 477 [PINCTRL_FUNC_SDIO0_CD] = { 478 .name = "sdio0_cd", 479 .regval = 0x08, 480 .groups = &((uint16_t []) { 481 PINCTRL_GRP_SDIO0_0_CD, 482 PINCTRL_GRP_SDIO0_1_CD, 483 PINCTRL_GRP_SDIO0_2_CD, 484 END_OF_GROUPS, 485 }), 486 }, 487 [PINCTRL_FUNC_SDIO0_WP] = { 488 .name = "sdio0_wp", 489 .regval = 0x08, 490 .groups = &((uint16_t []) { 491 PINCTRL_GRP_SDIO0_0_WP, 492 PINCTRL_GRP_SDIO0_1_WP, 493 PINCTRL_GRP_SDIO0_2_WP, 494 END_OF_GROUPS, 495 }), 496 }, 497 [PINCTRL_FUNC_SDIO1] = { 498 .name = "sdio1", 499 .regval = 0x10, 500 .groups = &((uint16_t []) { 501 PINCTRL_GRP_SDIO1_0, 502 PINCTRL_GRP_SDIO1_4BIT_0_0, 503 PINCTRL_GRP_SDIO1_4BIT_0_1, 504 PINCTRL_GRP_SDIO1_4BIT_1_0, 505 PINCTRL_GRP_SDIO1_1BIT_0_0, 506 PINCTRL_GRP_SDIO1_1BIT_0_1, 507 PINCTRL_GRP_SDIO1_1BIT_0_2, 508 PINCTRL_GRP_SDIO1_1BIT_0_3, 509 PINCTRL_GRP_SDIO1_1BIT_0_4, 510 PINCTRL_GRP_SDIO1_1BIT_0_5, 511 PINCTRL_GRP_SDIO1_1BIT_0_6, 512 PINCTRL_GRP_SDIO1_1BIT_0_7, 513 PINCTRL_GRP_SDIO1_1BIT_1_0, 514 PINCTRL_GRP_SDIO1_1BIT_1_1, 515 PINCTRL_GRP_SDIO1_1BIT_1_2, 516 PINCTRL_GRP_SDIO1_1BIT_1_3, 517 END_OF_GROUPS, 518 }), 519 }, 520 [PINCTRL_FUNC_SDIO1_PC] = { 521 .name = "sdio1_pc", 522 .regval = 0x10, 523 .groups = &((uint16_t []) { 524 PINCTRL_GRP_SDIO1_0_PC, 525 PINCTRL_GRP_SDIO1_1_PC, 526 END_OF_GROUPS, 527 }), 528 }, 529 [PINCTRL_FUNC_SDIO1_CD] = { 530 .name = "sdio1_cd", 531 .regval = 0x10, 532 .groups = &((uint16_t []) { 533 PINCTRL_GRP_SDIO1_0_CD, 534 PINCTRL_GRP_SDIO1_1_CD, 535 END_OF_GROUPS, 536 }), 537 }, 538 [PINCTRL_FUNC_SDIO1_WP] = { 539 .name = "sdio1_wp", 540 .regval = 0x10, 541 .groups = &((uint16_t []) { 542 PINCTRL_GRP_SDIO1_0_WP, 543 PINCTRL_GRP_SDIO1_1_WP, 544 END_OF_GROUPS, 545 }), 546 }, 547 [PINCTRL_FUNC_NAND0] = { 548 .name = "nand0", 549 .regval = 0x04, 550 .groups = &((uint16_t []) { 551 PINCTRL_GRP_NAND0_0, 552 END_OF_GROUPS, 553 }), 554 }, 555 [PINCTRL_FUNC_NAND0_CE] = { 556 .name = "nand0_ce", 557 .regval = 0x04, 558 .groups = &((uint16_t []) { 559 PINCTRL_GRP_NAND0_0_CE, 560 PINCTRL_GRP_NAND0_1_CE, 561 END_OF_GROUPS, 562 }), 563 }, 564 [PINCTRL_FUNC_NAND0_RB] = { 565 .name = "nand0_rb", 566 .regval = 0x04, 567 .groups = &((uint16_t []) { 568 PINCTRL_GRP_NAND0_0_RB, 569 PINCTRL_GRP_NAND0_1_RB, 570 END_OF_GROUPS, 571 }), 572 }, 573 [PINCTRL_FUNC_NAND0_DQS] = { 574 .name = "nand0_dqs", 575 .regval = 0x04, 576 .groups = &((uint16_t []) { 577 PINCTRL_GRP_NAND0_0_DQS, 578 PINCTRL_GRP_NAND0_1_DQS, 579 END_OF_GROUPS, 580 }), 581 }, 582 [PINCTRL_FUNC_TTC0_CLK] = { 583 .name = "ttc0_clk", 584 .regval = 0xa0, 585 .groups = &((uint16_t []) { 586 PINCTRL_GRP_TTC0_0_CLK, 587 PINCTRL_GRP_TTC0_1_CLK, 588 PINCTRL_GRP_TTC0_2_CLK, 589 PINCTRL_GRP_TTC0_3_CLK, 590 PINCTRL_GRP_TTC0_4_CLK, 591 PINCTRL_GRP_TTC0_5_CLK, 592 PINCTRL_GRP_TTC0_6_CLK, 593 PINCTRL_GRP_TTC0_7_CLK, 594 PINCTRL_GRP_TTC0_8_CLK, 595 END_OF_GROUPS, 596 }), 597 }, 598 [PINCTRL_FUNC_TTC0_WAV] = { 599 .name = "ttc0_wav", 600 .regval = 0xa0, 601 .groups = &((uint16_t []) { 602 PINCTRL_GRP_TTC0_0_WAV, 603 PINCTRL_GRP_TTC0_1_WAV, 604 PINCTRL_GRP_TTC0_2_WAV, 605 PINCTRL_GRP_TTC0_3_WAV, 606 PINCTRL_GRP_TTC0_4_WAV, 607 PINCTRL_GRP_TTC0_5_WAV, 608 PINCTRL_GRP_TTC0_6_WAV, 609 PINCTRL_GRP_TTC0_7_WAV, 610 PINCTRL_GRP_TTC0_8_WAV, 611 END_OF_GROUPS, 612 }), 613 }, 614 [PINCTRL_FUNC_TTC1_CLK] = { 615 .name = "ttc1_clk", 616 .regval = 0xa0, 617 .groups = &((uint16_t []) { 618 PINCTRL_GRP_TTC1_0_CLK, 619 PINCTRL_GRP_TTC1_1_CLK, 620 PINCTRL_GRP_TTC1_2_CLK, 621 PINCTRL_GRP_TTC1_3_CLK, 622 PINCTRL_GRP_TTC1_4_CLK, 623 PINCTRL_GRP_TTC1_5_CLK, 624 PINCTRL_GRP_TTC1_6_CLK, 625 PINCTRL_GRP_TTC1_7_CLK, 626 PINCTRL_GRP_TTC1_8_CLK, 627 END_OF_GROUPS, 628 }), 629 }, 630 [PINCTRL_FUNC_TTC1_WAV] = { 631 .name = "ttc1_wav", 632 .regval = 0xa0, 633 .groups = &((uint16_t []) { 634 PINCTRL_GRP_TTC1_0_WAV, 635 PINCTRL_GRP_TTC1_1_WAV, 636 PINCTRL_GRP_TTC1_2_WAV, 637 PINCTRL_GRP_TTC1_3_WAV, 638 PINCTRL_GRP_TTC1_4_WAV, 639 PINCTRL_GRP_TTC1_5_WAV, 640 PINCTRL_GRP_TTC1_6_WAV, 641 PINCTRL_GRP_TTC1_7_WAV, 642 PINCTRL_GRP_TTC1_8_WAV, 643 END_OF_GROUPS, 644 }), 645 }, 646 [PINCTRL_FUNC_TTC2_CLK] = { 647 .name = "ttc2_clk", 648 .regval = 0xa0, 649 .groups = &((uint16_t []) { 650 PINCTRL_GRP_TTC2_0_CLK, 651 PINCTRL_GRP_TTC2_1_CLK, 652 PINCTRL_GRP_TTC2_2_CLK, 653 PINCTRL_GRP_TTC2_3_CLK, 654 PINCTRL_GRP_TTC2_4_CLK, 655 PINCTRL_GRP_TTC2_5_CLK, 656 PINCTRL_GRP_TTC2_6_CLK, 657 PINCTRL_GRP_TTC2_7_CLK, 658 PINCTRL_GRP_TTC2_8_CLK, 659 END_OF_GROUPS, 660 }), 661 }, 662 [PINCTRL_FUNC_TTC2_WAV] = { 663 .name = "ttc2_wav", 664 .regval = 0xa0, 665 .groups = &((uint16_t []) { 666 PINCTRL_GRP_TTC2_0_WAV, 667 PINCTRL_GRP_TTC2_1_WAV, 668 PINCTRL_GRP_TTC2_2_WAV, 669 PINCTRL_GRP_TTC2_3_WAV, 670 PINCTRL_GRP_TTC2_4_WAV, 671 PINCTRL_GRP_TTC2_5_WAV, 672 PINCTRL_GRP_TTC2_6_WAV, 673 PINCTRL_GRP_TTC2_7_WAV, 674 PINCTRL_GRP_TTC2_8_WAV, 675 END_OF_GROUPS, 676 }), 677 }, 678 [PINCTRL_FUNC_TTC3_CLK] = { 679 .name = "ttc3_clk", 680 .regval = 0xa0, 681 .groups = &((uint16_t []) { 682 PINCTRL_GRP_TTC3_0_CLK, 683 PINCTRL_GRP_TTC3_1_CLK, 684 PINCTRL_GRP_TTC3_2_CLK, 685 PINCTRL_GRP_TTC3_3_CLK, 686 PINCTRL_GRP_TTC3_4_CLK, 687 PINCTRL_GRP_TTC3_5_CLK, 688 PINCTRL_GRP_TTC3_6_CLK, 689 PINCTRL_GRP_TTC3_7_CLK, 690 PINCTRL_GRP_TTC3_8_CLK, 691 END_OF_GROUPS, 692 }), 693 }, 694 [PINCTRL_FUNC_TTC3_WAV] = { 695 .name = "ttc3_wav", 696 .regval = 0xa0, 697 .groups = &((uint16_t []) { 698 PINCTRL_GRP_TTC3_0_WAV, 699 PINCTRL_GRP_TTC3_1_WAV, 700 PINCTRL_GRP_TTC3_2_WAV, 701 PINCTRL_GRP_TTC3_3_WAV, 702 PINCTRL_GRP_TTC3_4_WAV, 703 PINCTRL_GRP_TTC3_5_WAV, 704 PINCTRL_GRP_TTC3_6_WAV, 705 PINCTRL_GRP_TTC3_7_WAV, 706 PINCTRL_GRP_TTC3_8_WAV, 707 END_OF_GROUPS, 708 }), 709 }, 710 [PINCTRL_FUNC_UART0] = { 711 .name = "uart0", 712 .regval = 0xc0, 713 .groups = &((uint16_t []) { 714 PINCTRL_GRP_UART0_0, 715 PINCTRL_GRP_UART0_1, 716 PINCTRL_GRP_UART0_2, 717 PINCTRL_GRP_UART0_3, 718 PINCTRL_GRP_UART0_4, 719 PINCTRL_GRP_UART0_5, 720 PINCTRL_GRP_UART0_6, 721 PINCTRL_GRP_UART0_7, 722 PINCTRL_GRP_UART0_8, 723 PINCTRL_GRP_UART0_9, 724 PINCTRL_GRP_UART0_10, 725 PINCTRL_GRP_UART0_11, 726 PINCTRL_GRP_UART0_12, 727 PINCTRL_GRP_UART0_13, 728 PINCTRL_GRP_UART0_14, 729 PINCTRL_GRP_UART0_15, 730 PINCTRL_GRP_UART0_16, 731 PINCTRL_GRP_UART0_17, 732 PINCTRL_GRP_UART0_18, 733 END_OF_GROUPS, 734 }), 735 }, 736 [PINCTRL_FUNC_UART1] = { 737 .name = "uart1", 738 .regval = 0xc0, 739 .groups = &((uint16_t []) { 740 PINCTRL_GRP_UART1_0, 741 PINCTRL_GRP_UART1_1, 742 PINCTRL_GRP_UART1_2, 743 PINCTRL_GRP_UART1_3, 744 PINCTRL_GRP_UART1_4, 745 PINCTRL_GRP_UART1_5, 746 PINCTRL_GRP_UART1_6, 747 PINCTRL_GRP_UART1_7, 748 PINCTRL_GRP_UART1_8, 749 PINCTRL_GRP_UART1_9, 750 PINCTRL_GRP_UART1_10, 751 PINCTRL_GRP_UART1_11, 752 PINCTRL_GRP_UART1_12, 753 PINCTRL_GRP_UART1_13, 754 PINCTRL_GRP_UART1_14, 755 PINCTRL_GRP_UART1_15, 756 PINCTRL_GRP_UART1_16, 757 PINCTRL_GRP_UART1_17, 758 PINCTRL_GRP_UART1_18, 759 END_OF_GROUPS, 760 }), 761 }, 762 [PINCTRL_FUNC_USB0] = { 763 .name = "usb0", 764 .regval = 0x04, 765 .groups = &((uint16_t []) { 766 PINCTRL_GRP_USB0_0, 767 END_OF_GROUPS, 768 }), 769 }, 770 [PINCTRL_FUNC_USB1] = { 771 .name = "usb1", 772 .regval = 0x04, 773 .groups = &((uint16_t []) { 774 PINCTRL_GRP_USB1_0, 775 END_OF_GROUPS, 776 }), 777 }, 778 [PINCTRL_FUNC_SWDT0_CLK] = { 779 .name = "swdt0_clk", 780 .regval = 0x60, 781 .groups = &((uint16_t []) { 782 PINCTRL_GRP_SWDT0_0_CLK, 783 PINCTRL_GRP_SWDT0_1_CLK, 784 PINCTRL_GRP_SWDT0_2_CLK, 785 PINCTRL_GRP_SWDT0_3_CLK, 786 PINCTRL_GRP_SWDT0_4_CLK, 787 PINCTRL_GRP_SWDT0_5_CLK, 788 PINCTRL_GRP_SWDT0_6_CLK, 789 PINCTRL_GRP_SWDT0_7_CLK, 790 PINCTRL_GRP_SWDT0_8_CLK, 791 PINCTRL_GRP_SWDT0_9_CLK, 792 PINCTRL_GRP_SWDT0_10_CLK, 793 PINCTRL_GRP_SWDT0_11_CLK, 794 PINCTRL_GRP_SWDT0_12_CLK, 795 END_OF_GROUPS, 796 }), 797 }, 798 [PINCTRL_FUNC_SWDT0_RST] = { 799 .name = "swdt0_rst", 800 .regval = 0x60, 801 .groups = &((uint16_t []) { 802 PINCTRL_GRP_SWDT0_0_RST, 803 PINCTRL_GRP_SWDT0_1_RST, 804 PINCTRL_GRP_SWDT0_2_RST, 805 PINCTRL_GRP_SWDT0_3_RST, 806 PINCTRL_GRP_SWDT0_4_RST, 807 PINCTRL_GRP_SWDT0_5_RST, 808 PINCTRL_GRP_SWDT0_6_RST, 809 PINCTRL_GRP_SWDT0_7_RST, 810 PINCTRL_GRP_SWDT0_8_RST, 811 PINCTRL_GRP_SWDT0_9_RST, 812 PINCTRL_GRP_SWDT0_10_RST, 813 PINCTRL_GRP_SWDT0_11_RST, 814 PINCTRL_GRP_SWDT0_12_RST, 815 END_OF_GROUPS, 816 }), 817 }, 818 [PINCTRL_FUNC_SWDT1_CLK] = { 819 .name = "swdt1_clk", 820 .regval = 0x60, 821 .groups = &((uint16_t []) { 822 PINCTRL_GRP_SWDT1_0_CLK, 823 PINCTRL_GRP_SWDT1_1_CLK, 824 PINCTRL_GRP_SWDT1_2_CLK, 825 PINCTRL_GRP_SWDT1_3_CLK, 826 PINCTRL_GRP_SWDT1_4_CLK, 827 PINCTRL_GRP_SWDT1_5_CLK, 828 PINCTRL_GRP_SWDT1_6_CLK, 829 PINCTRL_GRP_SWDT1_7_CLK, 830 PINCTRL_GRP_SWDT1_8_CLK, 831 PINCTRL_GRP_SWDT1_9_CLK, 832 PINCTRL_GRP_SWDT1_10_CLK, 833 PINCTRL_GRP_SWDT1_11_CLK, 834 PINCTRL_GRP_SWDT1_12_CLK, 835 END_OF_GROUPS, 836 }), 837 }, 838 [PINCTRL_FUNC_SWDT1_RST] = { 839 .name = "swdt1_rst", 840 .regval = 0x60, 841 .groups = &((uint16_t []) { 842 PINCTRL_GRP_SWDT1_0_RST, 843 PINCTRL_GRP_SWDT1_1_RST, 844 PINCTRL_GRP_SWDT1_2_RST, 845 PINCTRL_GRP_SWDT1_3_RST, 846 PINCTRL_GRP_SWDT1_4_RST, 847 PINCTRL_GRP_SWDT1_5_RST, 848 PINCTRL_GRP_SWDT1_6_RST, 849 PINCTRL_GRP_SWDT1_7_RST, 850 PINCTRL_GRP_SWDT1_8_RST, 851 PINCTRL_GRP_SWDT1_9_RST, 852 PINCTRL_GRP_SWDT1_10_RST, 853 PINCTRL_GRP_SWDT1_11_RST, 854 PINCTRL_GRP_SWDT1_12_RST, 855 END_OF_GROUPS, 856 }), 857 }, 858 [PINCTRL_FUNC_PMU0] = { 859 .name = "pmu0", 860 .regval = 0x08, 861 .groups = &((uint16_t []) { 862 PINCTRL_GRP_PMU0_0, 863 PINCTRL_GRP_PMU0_1, 864 PINCTRL_GRP_PMU0_2, 865 PINCTRL_GRP_PMU0_3, 866 PINCTRL_GRP_PMU0_4, 867 PINCTRL_GRP_PMU0_5, 868 PINCTRL_GRP_PMU0_6, 869 PINCTRL_GRP_PMU0_7, 870 PINCTRL_GRP_PMU0_8, 871 PINCTRL_GRP_PMU0_9, 872 PINCTRL_GRP_PMU0_10, 873 PINCTRL_GRP_PMU0_11, 874 END_OF_GROUPS, 875 }), 876 }, 877 [PINCTRL_FUNC_PCIE0] = { 878 .name = "pcie0", 879 .regval = 0x04, 880 .groups = &((uint16_t []) { 881 PINCTRL_GRP_PCIE0_0, 882 PINCTRL_GRP_PCIE0_1, 883 PINCTRL_GRP_PCIE0_2, 884 PINCTRL_GRP_PCIE0_3, 885 PINCTRL_GRP_PCIE0_4, 886 PINCTRL_GRP_PCIE0_5, 887 PINCTRL_GRP_PCIE0_6, 888 PINCTRL_GRP_PCIE0_7, 889 END_OF_GROUPS, 890 }), 891 }, 892 [PINCTRL_FUNC_CSU0] = { 893 .name = "csu0", 894 .regval = 0x18, 895 .groups = &((uint16_t []) { 896 PINCTRL_GRP_CSU0_0, 897 PINCTRL_GRP_CSU0_1, 898 PINCTRL_GRP_CSU0_2, 899 PINCTRL_GRP_CSU0_3, 900 PINCTRL_GRP_CSU0_4, 901 PINCTRL_GRP_CSU0_5, 902 PINCTRL_GRP_CSU0_6, 903 PINCTRL_GRP_CSU0_7, 904 PINCTRL_GRP_CSU0_8, 905 PINCTRL_GRP_CSU0_9, 906 PINCTRL_GRP_CSU0_10, 907 PINCTRL_GRP_CSU0_11, 908 END_OF_GROUPS, 909 }), 910 }, 911 [PINCTRL_FUNC_DPAUX0] = { 912 .name = "dpaux0", 913 .regval = 0x18, 914 .groups = &((uint16_t []) { 915 PINCTRL_GRP_DPAUX0_0, 916 PINCTRL_GRP_DPAUX0_1, 917 PINCTRL_GRP_DPAUX0_2, 918 PINCTRL_GRP_DPAUX0_3, 919 END_OF_GROUPS, 920 }), 921 }, 922 [PINCTRL_FUNC_PJTAG0] = { 923 .name = "pjtag0", 924 .regval = 0x60, 925 .groups = &((uint16_t []) { 926 PINCTRL_GRP_PJTAG0_0, 927 PINCTRL_GRP_PJTAG0_1, 928 PINCTRL_GRP_PJTAG0_2, 929 PINCTRL_GRP_PJTAG0_3, 930 PINCTRL_GRP_PJTAG0_4, 931 PINCTRL_GRP_PJTAG0_5, 932 END_OF_GROUPS, 933 }), 934 }, 935 [PINCTRL_FUNC_TRACE0] = { 936 .name = "trace0", 937 .regval = 0xe0, 938 .groups = &((uint16_t []) { 939 PINCTRL_GRP_TRACE0_0, 940 PINCTRL_GRP_TRACE0_1, 941 PINCTRL_GRP_TRACE0_2, 942 END_OF_GROUPS, 943 }), 944 }, 945 [PINCTRL_FUNC_TRACE0_CLK] = { 946 .name = "trace0_clk", 947 .regval = 0xe0, 948 .groups = &((uint16_t []) { 949 PINCTRL_GRP_TRACE0_0_CLK, 950 PINCTRL_GRP_TRACE0_1_CLK, 951 PINCTRL_GRP_TRACE0_2_CLK, 952 END_OF_GROUPS, 953 }), 954 }, 955 [PINCTRL_FUNC_TESTSCAN0] = { 956 .name = "testscan0", 957 .regval = 0x10, 958 .groups = &((uint16_t []) { 959 PINCTRL_GRP_TESTSCAN0_0, 960 END_OF_GROUPS, 961 }), 962 }, 963 }; 964 965 static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = { 966 [PINCTRL_PIN_0] = { 967 .groups = &((uint16_t []) { 968 PINCTRL_GRP_QSPI0_0, 969 PINCTRL_GRP_RESERVED, 970 PINCTRL_GRP_RESERVED, 971 PINCTRL_GRP_TESTSCAN0_0, 972 PINCTRL_GRP_RESERVED, 973 PINCTRL_GRP_GPIO0_0, 974 PINCTRL_GRP_CAN1_0, 975 PINCTRL_GRP_I2C1_0, 976 PINCTRL_GRP_PJTAG0_0, 977 PINCTRL_GRP_SPI0_0, 978 PINCTRL_GRP_TTC3_0_CLK, 979 PINCTRL_GRP_UART1_0, 980 PINCTRL_GRP_TRACE0_0_CLK, 981 END_OF_GROUPS, 982 }), 983 }, 984 [PINCTRL_PIN_1] = { 985 .groups = &((uint16_t []) { 986 PINCTRL_GRP_QSPI0_0, 987 PINCTRL_GRP_RESERVED, 988 PINCTRL_GRP_RESERVED, 989 PINCTRL_GRP_TESTSCAN0_0, 990 PINCTRL_GRP_RESERVED, 991 PINCTRL_GRP_GPIO0_1, 992 PINCTRL_GRP_CAN1_0, 993 PINCTRL_GRP_I2C1_0, 994 PINCTRL_GRP_PJTAG0_0, 995 PINCTRL_GRP_SPI0_0_SS2, 996 PINCTRL_GRP_TTC3_0_WAV, 997 PINCTRL_GRP_UART1_0, 998 PINCTRL_GRP_TRACE0_0_CLK, 999 END_OF_GROUPS, 1000 }), 1001 }, 1002 [PINCTRL_PIN_2] = { 1003 .groups = &((uint16_t []) { 1004 PINCTRL_GRP_QSPI0_0, 1005 PINCTRL_GRP_RESERVED, 1006 PINCTRL_GRP_RESERVED, 1007 PINCTRL_GRP_TESTSCAN0_0, 1008 PINCTRL_GRP_RESERVED, 1009 PINCTRL_GRP_GPIO0_2, 1010 PINCTRL_GRP_CAN0_0, 1011 PINCTRL_GRP_I2C0_0, 1012 PINCTRL_GRP_PJTAG0_0, 1013 PINCTRL_GRP_SPI0_0_SS1, 1014 PINCTRL_GRP_TTC2_0_CLK, 1015 PINCTRL_GRP_UART0_0, 1016 PINCTRL_GRP_TRACE0_0, 1017 END_OF_GROUPS, 1018 }), 1019 }, 1020 [PINCTRL_PIN_3] = { 1021 .groups = &((uint16_t []) { 1022 PINCTRL_GRP_QSPI0_0, 1023 PINCTRL_GRP_RESERVED, 1024 PINCTRL_GRP_RESERVED, 1025 PINCTRL_GRP_TESTSCAN0_0, 1026 PINCTRL_GRP_RESERVED, 1027 PINCTRL_GRP_GPIO0_3, 1028 PINCTRL_GRP_CAN0_0, 1029 PINCTRL_GRP_I2C0_0, 1030 PINCTRL_GRP_PJTAG0_0, 1031 PINCTRL_GRP_SPI0_0_SS0, 1032 PINCTRL_GRP_TTC2_0_WAV, 1033 PINCTRL_GRP_UART0_0, 1034 PINCTRL_GRP_TRACE0_0, 1035 END_OF_GROUPS, 1036 }), 1037 }, 1038 [PINCTRL_PIN_4] = { 1039 .groups = &((uint16_t []) { 1040 PINCTRL_GRP_QSPI0_0, 1041 PINCTRL_GRP_RESERVED, 1042 PINCTRL_GRP_RESERVED, 1043 PINCTRL_GRP_TESTSCAN0_0, 1044 PINCTRL_GRP_RESERVED, 1045 PINCTRL_GRP_GPIO0_4, 1046 PINCTRL_GRP_CAN1_1, 1047 PINCTRL_GRP_I2C1_1, 1048 PINCTRL_GRP_SWDT1_0_CLK, 1049 PINCTRL_GRP_SPI0_0, 1050 PINCTRL_GRP_TTC1_0_CLK, 1051 PINCTRL_GRP_UART1_1, 1052 PINCTRL_GRP_TRACE0_0, 1053 END_OF_GROUPS, 1054 }), 1055 }, 1056 [PINCTRL_PIN_5] = { 1057 .groups = &((uint16_t []) { 1058 PINCTRL_GRP_QSPI_SS, 1059 PINCTRL_GRP_RESERVED, 1060 PINCTRL_GRP_RESERVED, 1061 PINCTRL_GRP_TESTSCAN0_0, 1062 PINCTRL_GRP_RESERVED, 1063 PINCTRL_GRP_GPIO0_5, 1064 PINCTRL_GRP_CAN1_1, 1065 PINCTRL_GRP_I2C1_1, 1066 PINCTRL_GRP_SWDT1_0_RST, 1067 PINCTRL_GRP_SPI0_0, 1068 PINCTRL_GRP_TTC1_0_WAV, 1069 PINCTRL_GRP_UART1_1, 1070 PINCTRL_GRP_TRACE0_0, 1071 END_OF_GROUPS, 1072 }), 1073 }, 1074 [PINCTRL_PIN_6] = { 1075 .groups = &((uint16_t []) { 1076 PINCTRL_GRP_QSPI_FBCLK, 1077 PINCTRL_GRP_RESERVED, 1078 PINCTRL_GRP_RESERVED, 1079 PINCTRL_GRP_TESTSCAN0_0, 1080 PINCTRL_GRP_RESERVED, 1081 PINCTRL_GRP_GPIO0_6, 1082 PINCTRL_GRP_CAN0_1, 1083 PINCTRL_GRP_I2C0_1, 1084 PINCTRL_GRP_SWDT0_0_CLK, 1085 PINCTRL_GRP_SPI1_0, 1086 PINCTRL_GRP_TTC0_0_CLK, 1087 PINCTRL_GRP_UART0_1, 1088 PINCTRL_GRP_TRACE0_0, 1089 END_OF_GROUPS, 1090 }), 1091 }, 1092 [PINCTRL_PIN_7] = { 1093 .groups = &((uint16_t []) { 1094 PINCTRL_GRP_QSPI_SS, 1095 PINCTRL_GRP_RESERVED, 1096 PINCTRL_GRP_RESERVED, 1097 PINCTRL_GRP_TESTSCAN0_0, 1098 PINCTRL_GRP_RESERVED, 1099 PINCTRL_GRP_GPIO0_7, 1100 PINCTRL_GRP_CAN0_1, 1101 PINCTRL_GRP_I2C0_1, 1102 PINCTRL_GRP_SWDT0_0_RST, 1103 PINCTRL_GRP_SPI1_0_SS2, 1104 PINCTRL_GRP_TTC0_0_WAV, 1105 PINCTRL_GRP_UART0_1, 1106 PINCTRL_GRP_TRACE0_0, 1107 END_OF_GROUPS, 1108 }), 1109 }, 1110 [PINCTRL_PIN_8] = { 1111 .groups = &((uint16_t []) { 1112 PINCTRL_GRP_QSPI0_0, 1113 PINCTRL_GRP_RESERVED, 1114 PINCTRL_GRP_RESERVED, 1115 PINCTRL_GRP_TESTSCAN0_0, 1116 PINCTRL_GRP_RESERVED, 1117 PINCTRL_GRP_GPIO0_8, 1118 PINCTRL_GRP_CAN1_2, 1119 PINCTRL_GRP_I2C1_2, 1120 PINCTRL_GRP_SWDT1_1_CLK, 1121 PINCTRL_GRP_SPI1_0_SS1, 1122 PINCTRL_GRP_TTC3_1_CLK, 1123 PINCTRL_GRP_UART1_2, 1124 PINCTRL_GRP_TRACE0_0, 1125 END_OF_GROUPS, 1126 }), 1127 }, 1128 [PINCTRL_PIN_9] = { 1129 .groups = &((uint16_t []) { 1130 PINCTRL_GRP_QSPI0_0, 1131 PINCTRL_GRP_NAND0_0_CE, 1132 PINCTRL_GRP_RESERVED, 1133 PINCTRL_GRP_TESTSCAN0_0, 1134 PINCTRL_GRP_RESERVED, 1135 PINCTRL_GRP_GPIO0_9, 1136 PINCTRL_GRP_CAN1_2, 1137 PINCTRL_GRP_I2C1_2, 1138 PINCTRL_GRP_SWDT1_1_RST, 1139 PINCTRL_GRP_SPI1_0_SS0, 1140 PINCTRL_GRP_TTC3_1_WAV, 1141 PINCTRL_GRP_UART1_2, 1142 PINCTRL_GRP_TRACE0_0, 1143 END_OF_GROUPS, 1144 }), 1145 }, 1146 [PINCTRL_PIN_10] = { 1147 .groups = &((uint16_t []) { 1148 PINCTRL_GRP_QSPI0_0, 1149 PINCTRL_GRP_NAND0_0_RB, 1150 PINCTRL_GRP_RESERVED, 1151 PINCTRL_GRP_TESTSCAN0_0, 1152 PINCTRL_GRP_RESERVED, 1153 PINCTRL_GRP_GPIO0_10, 1154 PINCTRL_GRP_CAN0_2, 1155 PINCTRL_GRP_I2C0_2, 1156 PINCTRL_GRP_SWDT0_1_CLK, 1157 PINCTRL_GRP_SPI1_0, 1158 PINCTRL_GRP_TTC2_1_CLK, 1159 PINCTRL_GRP_UART0_2, 1160 PINCTRL_GRP_TRACE0_0, 1161 END_OF_GROUPS, 1162 }), 1163 }, 1164 [PINCTRL_PIN_11] = { 1165 .groups = &((uint16_t []) { 1166 PINCTRL_GRP_QSPI0_0, 1167 PINCTRL_GRP_NAND0_0_RB, 1168 PINCTRL_GRP_RESERVED, 1169 PINCTRL_GRP_TESTSCAN0_0, 1170 PINCTRL_GRP_RESERVED, 1171 PINCTRL_GRP_GPIO0_11, 1172 PINCTRL_GRP_CAN0_2, 1173 PINCTRL_GRP_I2C0_2, 1174 PINCTRL_GRP_SWDT0_1_RST, 1175 PINCTRL_GRP_SPI1_0, 1176 PINCTRL_GRP_TTC2_1_WAV, 1177 PINCTRL_GRP_UART0_2, 1178 PINCTRL_GRP_TRACE0_0, 1179 END_OF_GROUPS, 1180 }), 1181 }, 1182 [PINCTRL_PIN_12] = { 1183 .groups = &((uint16_t []) { 1184 PINCTRL_GRP_QSPI0_0, 1185 PINCTRL_GRP_NAND0_0_DQS, 1186 PINCTRL_GRP_RESERVED, 1187 PINCTRL_GRP_TESTSCAN0_0, 1188 PINCTRL_GRP_RESERVED, 1189 PINCTRL_GRP_GPIO0_12, 1190 PINCTRL_GRP_CAN1_3, 1191 PINCTRL_GRP_I2C1_3, 1192 PINCTRL_GRP_PJTAG0_1, 1193 PINCTRL_GRP_SPI0_1, 1194 PINCTRL_GRP_TTC1_1_CLK, 1195 PINCTRL_GRP_UART1_3, 1196 PINCTRL_GRP_TRACE0_0, 1197 END_OF_GROUPS, 1198 }), 1199 }, 1200 [PINCTRL_PIN_13] = { 1201 .groups = &((uint16_t []) { 1202 PINCTRL_GRP_RESERVED, 1203 PINCTRL_GRP_NAND0_0, 1204 PINCTRL_GRP_SDIO0_0, 1205 PINCTRL_GRP_TESTSCAN0_0, 1206 PINCTRL_GRP_RESERVED, 1207 PINCTRL_GRP_GPIO0_13, 1208 PINCTRL_GRP_CAN1_3, 1209 PINCTRL_GRP_I2C1_3, 1210 PINCTRL_GRP_PJTAG0_1, 1211 PINCTRL_GRP_SPI0_1_SS2, 1212 PINCTRL_GRP_TTC1_1_WAV, 1213 PINCTRL_GRP_UART1_3, 1214 PINCTRL_GRP_TRACE0_0, 1215 PINCTRL_GRP_SDIO0_4BIT_0_0, 1216 PINCTRL_GRP_SDIO0_1BIT_0_0, 1217 END_OF_GROUPS, 1218 }), 1219 }, 1220 [PINCTRL_PIN_14] = { 1221 .groups = &((uint16_t []) { 1222 PINCTRL_GRP_RESERVED, 1223 PINCTRL_GRP_NAND0_0, 1224 PINCTRL_GRP_SDIO0_0, 1225 PINCTRL_GRP_TESTSCAN0_0, 1226 PINCTRL_GRP_RESERVED, 1227 PINCTRL_GRP_GPIO0_14, 1228 PINCTRL_GRP_CAN0_3, 1229 PINCTRL_GRP_I2C0_3, 1230 PINCTRL_GRP_PJTAG0_1, 1231 PINCTRL_GRP_SPI0_1_SS1, 1232 PINCTRL_GRP_TTC0_1_CLK, 1233 PINCTRL_GRP_UART0_3, 1234 PINCTRL_GRP_TRACE0_0, 1235 PINCTRL_GRP_SDIO0_4BIT_0_0, 1236 PINCTRL_GRP_SDIO0_1BIT_0_1, 1237 END_OF_GROUPS, 1238 }), 1239 }, 1240 [PINCTRL_PIN_15] = { 1241 .groups = &((uint16_t []) { 1242 PINCTRL_GRP_RESERVED, 1243 PINCTRL_GRP_NAND0_0, 1244 PINCTRL_GRP_SDIO0_0, 1245 PINCTRL_GRP_TESTSCAN0_0, 1246 PINCTRL_GRP_RESERVED, 1247 PINCTRL_GRP_GPIO0_15, 1248 PINCTRL_GRP_CAN0_3, 1249 PINCTRL_GRP_I2C0_3, 1250 PINCTRL_GRP_PJTAG0_1, 1251 PINCTRL_GRP_SPI0_1_SS0, 1252 PINCTRL_GRP_TTC0_1_WAV, 1253 PINCTRL_GRP_UART0_3, 1254 PINCTRL_GRP_TRACE0_0, 1255 PINCTRL_GRP_SDIO0_4BIT_0_0, 1256 PINCTRL_GRP_SDIO0_1BIT_0_2, 1257 END_OF_GROUPS, 1258 }), 1259 }, 1260 [PINCTRL_PIN_16] = { 1261 .groups = &((uint16_t []) { 1262 PINCTRL_GRP_RESERVED, 1263 PINCTRL_GRP_NAND0_0, 1264 PINCTRL_GRP_SDIO0_0, 1265 PINCTRL_GRP_TESTSCAN0_0, 1266 PINCTRL_GRP_RESERVED, 1267 PINCTRL_GRP_GPIO0_16, 1268 PINCTRL_GRP_CAN1_4, 1269 PINCTRL_GRP_I2C1_4, 1270 PINCTRL_GRP_SWDT1_2_CLK, 1271 PINCTRL_GRP_SPI0_1, 1272 PINCTRL_GRP_TTC3_2_CLK, 1273 PINCTRL_GRP_UART1_4, 1274 PINCTRL_GRP_TRACE0_0, 1275 PINCTRL_GRP_SDIO0_4BIT_0_0, 1276 PINCTRL_GRP_SDIO0_1BIT_0_3, 1277 END_OF_GROUPS, 1278 }), 1279 }, 1280 [PINCTRL_PIN_17] = { 1281 .groups = &((uint16_t []) { 1282 PINCTRL_GRP_RESERVED, 1283 PINCTRL_GRP_NAND0_0, 1284 PINCTRL_GRP_SDIO0_0, 1285 PINCTRL_GRP_TESTSCAN0_0, 1286 PINCTRL_GRP_RESERVED, 1287 PINCTRL_GRP_GPIO0_17, 1288 PINCTRL_GRP_CAN1_4, 1289 PINCTRL_GRP_I2C1_4, 1290 PINCTRL_GRP_SWDT1_2_RST, 1291 PINCTRL_GRP_SPI0_1, 1292 PINCTRL_GRP_TTC3_2_WAV, 1293 PINCTRL_GRP_UART1_4, 1294 PINCTRL_GRP_TRACE0_0, 1295 PINCTRL_GRP_SDIO0_4BIT_0_1, 1296 PINCTRL_GRP_SDIO0_1BIT_0_4, 1297 END_OF_GROUPS, 1298 }), 1299 }, 1300 [PINCTRL_PIN_18] = { 1301 .groups = &((uint16_t []) { 1302 PINCTRL_GRP_RESERVED, 1303 PINCTRL_GRP_NAND0_0, 1304 PINCTRL_GRP_SDIO0_0, 1305 PINCTRL_GRP_TESTSCAN0_0, 1306 PINCTRL_GRP_CSU0_0, 1307 PINCTRL_GRP_GPIO0_18, 1308 PINCTRL_GRP_CAN0_4, 1309 PINCTRL_GRP_I2C0_4, 1310 PINCTRL_GRP_SWDT0_2_CLK, 1311 PINCTRL_GRP_SPI1_1, 1312 PINCTRL_GRP_TTC2_2_CLK, 1313 PINCTRL_GRP_UART0_4, 1314 PINCTRL_GRP_RESERVED, 1315 PINCTRL_GRP_SDIO0_4BIT_0_1, 1316 PINCTRL_GRP_SDIO0_1BIT_0_5, 1317 END_OF_GROUPS, 1318 }), 1319 }, 1320 [PINCTRL_PIN_19] = { 1321 .groups = &((uint16_t []) { 1322 PINCTRL_GRP_RESERVED, 1323 PINCTRL_GRP_NAND0_0, 1324 PINCTRL_GRP_SDIO0_0, 1325 PINCTRL_GRP_TESTSCAN0_0, 1326 PINCTRL_GRP_CSU0_1, 1327 PINCTRL_GRP_GPIO0_19, 1328 PINCTRL_GRP_CAN0_4, 1329 PINCTRL_GRP_I2C0_4, 1330 PINCTRL_GRP_SWDT0_2_RST, 1331 PINCTRL_GRP_SPI1_1_SS2, 1332 PINCTRL_GRP_TTC2_2_WAV, 1333 PINCTRL_GRP_UART0_4, 1334 PINCTRL_GRP_RESERVED, 1335 PINCTRL_GRP_SDIO0_4BIT_0_1, 1336 PINCTRL_GRP_SDIO0_1BIT_0_6, 1337 END_OF_GROUPS, 1338 }), 1339 }, 1340 [PINCTRL_PIN_20] = { 1341 .groups = &((uint16_t []) { 1342 PINCTRL_GRP_RESERVED, 1343 PINCTRL_GRP_NAND0_0, 1344 PINCTRL_GRP_SDIO0_0, 1345 PINCTRL_GRP_TESTSCAN0_0, 1346 PINCTRL_GRP_CSU0_2, 1347 PINCTRL_GRP_GPIO0_20, 1348 PINCTRL_GRP_CAN1_5, 1349 PINCTRL_GRP_I2C1_5, 1350 PINCTRL_GRP_SWDT1_3_CLK, 1351 PINCTRL_GRP_SPI1_1_SS1, 1352 PINCTRL_GRP_TTC1_2_CLK, 1353 PINCTRL_GRP_UART1_5, 1354 PINCTRL_GRP_RESERVED, 1355 PINCTRL_GRP_SDIO0_4BIT_0_1, 1356 PINCTRL_GRP_SDIO0_1BIT_0_7, 1357 END_OF_GROUPS, 1358 }), 1359 }, 1360 [PINCTRL_PIN_21] = { 1361 .groups = &((uint16_t []) { 1362 PINCTRL_GRP_RESERVED, 1363 PINCTRL_GRP_NAND0_0, 1364 PINCTRL_GRP_SDIO0_0, 1365 PINCTRL_GRP_TESTSCAN0_0, 1366 PINCTRL_GRP_CSU0_3, 1367 PINCTRL_GRP_GPIO0_21, 1368 PINCTRL_GRP_CAN1_5, 1369 PINCTRL_GRP_I2C1_5, 1370 PINCTRL_GRP_SWDT1_3_RST, 1371 PINCTRL_GRP_SPI1_1_SS0, 1372 PINCTRL_GRP_TTC1_2_WAV, 1373 PINCTRL_GRP_UART1_5, 1374 PINCTRL_GRP_RESERVED, 1375 PINCTRL_GRP_SDIO0_4BIT_0_0, 1376 PINCTRL_GRP_SDIO0_4BIT_0_1, 1377 PINCTRL_GRP_SDIO0_1BIT_0_0, 1378 PINCTRL_GRP_SDIO0_1BIT_0_1, 1379 PINCTRL_GRP_SDIO0_1BIT_0_2, 1380 PINCTRL_GRP_SDIO0_1BIT_0_3, 1381 PINCTRL_GRP_SDIO0_1BIT_0_4, 1382 PINCTRL_GRP_SDIO0_1BIT_0_5, 1383 PINCTRL_GRP_SDIO0_1BIT_0_6, 1384 PINCTRL_GRP_SDIO0_1BIT_0_7, 1385 END_OF_GROUPS, 1386 }), 1387 }, 1388 [PINCTRL_PIN_22] = { 1389 .groups = &((uint16_t []) { 1390 PINCTRL_GRP_RESERVED, 1391 PINCTRL_GRP_NAND0_0, 1392 PINCTRL_GRP_SDIO0_0, 1393 PINCTRL_GRP_TESTSCAN0_0, 1394 PINCTRL_GRP_CSU0_4, 1395 PINCTRL_GRP_GPIO0_22, 1396 PINCTRL_GRP_CAN0_5, 1397 PINCTRL_GRP_I2C0_5, 1398 PINCTRL_GRP_SWDT0_3_CLK, 1399 PINCTRL_GRP_SPI1_1, 1400 PINCTRL_GRP_TTC0_2_CLK, 1401 PINCTRL_GRP_UART0_5, 1402 PINCTRL_GRP_RESERVED, 1403 PINCTRL_GRP_SDIO0_4BIT_0_0, 1404 PINCTRL_GRP_SDIO0_4BIT_0_1, 1405 PINCTRL_GRP_SDIO0_1BIT_0_0, 1406 PINCTRL_GRP_SDIO0_1BIT_0_1, 1407 PINCTRL_GRP_SDIO0_1BIT_0_2, 1408 PINCTRL_GRP_SDIO0_1BIT_0_3, 1409 PINCTRL_GRP_SDIO0_1BIT_0_4, 1410 PINCTRL_GRP_SDIO0_1BIT_0_5, 1411 PINCTRL_GRP_SDIO0_1BIT_0_6, 1412 PINCTRL_GRP_SDIO0_1BIT_0_7, 1413 END_OF_GROUPS, 1414 }), 1415 }, 1416 [PINCTRL_PIN_23] = { 1417 .groups = &((uint16_t []) { 1418 PINCTRL_GRP_RESERVED, 1419 PINCTRL_GRP_NAND0_0, 1420 PINCTRL_GRP_SDIO0_0_PC, 1421 PINCTRL_GRP_TESTSCAN0_0, 1422 PINCTRL_GRP_CSU0_5, 1423 PINCTRL_GRP_GPIO0_23, 1424 PINCTRL_GRP_CAN0_5, 1425 PINCTRL_GRP_I2C0_5, 1426 PINCTRL_GRP_SWDT0_3_RST, 1427 PINCTRL_GRP_SPI1_1, 1428 PINCTRL_GRP_TTC0_2_WAV, 1429 PINCTRL_GRP_UART0_5, 1430 PINCTRL_GRP_RESERVED, 1431 END_OF_GROUPS, 1432 }), 1433 }, 1434 [PINCTRL_PIN_24] = { 1435 .groups = &((uint16_t []) { 1436 PINCTRL_GRP_RESERVED, 1437 PINCTRL_GRP_NAND0_0, 1438 PINCTRL_GRP_SDIO0_0_CD, 1439 PINCTRL_GRP_TESTSCAN0_0, 1440 PINCTRL_GRP_CSU0_6, 1441 PINCTRL_GRP_GPIO0_24, 1442 PINCTRL_GRP_CAN1_6, 1443 PINCTRL_GRP_I2C1_6, 1444 PINCTRL_GRP_SWDT1_4_CLK, 1445 PINCTRL_GRP_RESERVED, 1446 PINCTRL_GRP_TTC3_3_CLK, 1447 PINCTRL_GRP_UART1_6, 1448 PINCTRL_GRP_RESERVED, 1449 END_OF_GROUPS, 1450 }), 1451 }, 1452 [PINCTRL_PIN_25] = { 1453 .groups = &((uint16_t []) { 1454 PINCTRL_GRP_RESERVED, 1455 PINCTRL_GRP_NAND0_0, 1456 PINCTRL_GRP_SDIO0_0_WP, 1457 PINCTRL_GRP_TESTSCAN0_0, 1458 PINCTRL_GRP_CSU0_7, 1459 PINCTRL_GRP_GPIO0_25, 1460 PINCTRL_GRP_CAN1_6, 1461 PINCTRL_GRP_I2C1_6, 1462 PINCTRL_GRP_SWDT1_4_RST, 1463 PINCTRL_GRP_RESERVED, 1464 PINCTRL_GRP_TTC3_3_WAV, 1465 PINCTRL_GRP_UART1_6, 1466 PINCTRL_GRP_RESERVED, 1467 END_OF_GROUPS, 1468 }), 1469 }, 1470 [PINCTRL_PIN_26] = { 1471 .groups = &((uint16_t []) { 1472 PINCTRL_GRP_ETHERNET0_0, 1473 PINCTRL_GRP_GEMTSU0_0, 1474 PINCTRL_GRP_NAND0_1_CE, 1475 PINCTRL_GRP_PMU0_0, 1476 PINCTRL_GRP_TESTSCAN0_0, 1477 PINCTRL_GRP_CSU0_8, 1478 PINCTRL_GRP_GPIO0_26, 1479 PINCTRL_GRP_CAN0_6, 1480 PINCTRL_GRP_I2C0_6, 1481 PINCTRL_GRP_PJTAG0_2, 1482 PINCTRL_GRP_SPI0_2, 1483 PINCTRL_GRP_TTC2_3_CLK, 1484 PINCTRL_GRP_UART0_6, 1485 PINCTRL_GRP_TRACE0_1, 1486 END_OF_GROUPS, 1487 }), 1488 }, 1489 [PINCTRL_PIN_27] = { 1490 .groups = &((uint16_t []) { 1491 PINCTRL_GRP_ETHERNET0_0, 1492 PINCTRL_GRP_NAND0_1_RB, 1493 PINCTRL_GRP_PMU0_1, 1494 PINCTRL_GRP_TESTSCAN0_0, 1495 PINCTRL_GRP_DPAUX0_0, 1496 PINCTRL_GRP_GPIO0_27, 1497 PINCTRL_GRP_CAN0_6, 1498 PINCTRL_GRP_I2C0_6, 1499 PINCTRL_GRP_PJTAG0_2, 1500 PINCTRL_GRP_SPI0_2_SS2, 1501 PINCTRL_GRP_TTC2_3_WAV, 1502 PINCTRL_GRP_UART0_6, 1503 PINCTRL_GRP_TRACE0_1, 1504 END_OF_GROUPS, 1505 }), 1506 }, 1507 [PINCTRL_PIN_28] = { 1508 .groups = &((uint16_t []) { 1509 PINCTRL_GRP_ETHERNET0_0, 1510 PINCTRL_GRP_NAND0_1_RB, 1511 PINCTRL_GRP_PMU0_2, 1512 PINCTRL_GRP_TESTSCAN0_0, 1513 PINCTRL_GRP_DPAUX0_0, 1514 PINCTRL_GRP_GPIO0_28, 1515 PINCTRL_GRP_CAN1_7, 1516 PINCTRL_GRP_I2C1_7, 1517 PINCTRL_GRP_PJTAG0_2, 1518 PINCTRL_GRP_SPI0_2_SS1, 1519 PINCTRL_GRP_TTC1_3_CLK, 1520 PINCTRL_GRP_UART1_7, 1521 PINCTRL_GRP_TRACE0_1, 1522 END_OF_GROUPS, 1523 }), 1524 }, 1525 [PINCTRL_PIN_29] = { 1526 .groups = &((uint16_t []) { 1527 PINCTRL_GRP_ETHERNET0_0, 1528 PINCTRL_GRP_PCIE0_0, 1529 PINCTRL_GRP_PMU0_3, 1530 PINCTRL_GRP_TESTSCAN0_0, 1531 PINCTRL_GRP_DPAUX0_1, 1532 PINCTRL_GRP_GPIO0_29, 1533 PINCTRL_GRP_CAN1_7, 1534 PINCTRL_GRP_I2C1_7, 1535 PINCTRL_GRP_PJTAG0_2, 1536 PINCTRL_GRP_SPI0_2_SS0, 1537 PINCTRL_GRP_TTC1_3_WAV, 1538 PINCTRL_GRP_UART1_7, 1539 PINCTRL_GRP_TRACE0_1, 1540 END_OF_GROUPS, 1541 }), 1542 }, 1543 [PINCTRL_PIN_30] = { 1544 .groups = &((uint16_t []) { 1545 PINCTRL_GRP_ETHERNET0_0, 1546 PINCTRL_GRP_PCIE0_1, 1547 PINCTRL_GRP_PMU0_4, 1548 PINCTRL_GRP_TESTSCAN0_0, 1549 PINCTRL_GRP_DPAUX0_1, 1550 PINCTRL_GRP_GPIO0_30, 1551 PINCTRL_GRP_CAN0_7, 1552 PINCTRL_GRP_I2C0_7, 1553 PINCTRL_GRP_SWDT0_4_CLK, 1554 PINCTRL_GRP_SPI0_2, 1555 PINCTRL_GRP_TTC0_3_CLK, 1556 PINCTRL_GRP_UART0_7, 1557 PINCTRL_GRP_TRACE0_1, 1558 END_OF_GROUPS, 1559 }), 1560 }, 1561 [PINCTRL_PIN_31] = { 1562 .groups = &((uint16_t []) { 1563 PINCTRL_GRP_ETHERNET0_0, 1564 PINCTRL_GRP_PCIE0_2, 1565 PINCTRL_GRP_PMU0_5, 1566 PINCTRL_GRP_TESTSCAN0_0, 1567 PINCTRL_GRP_CSU0_9, 1568 PINCTRL_GRP_GPIO0_31, 1569 PINCTRL_GRP_CAN0_7, 1570 PINCTRL_GRP_I2C0_7, 1571 PINCTRL_GRP_SWDT0_4_RST, 1572 PINCTRL_GRP_SPI0_2, 1573 PINCTRL_GRP_TTC0_3_WAV, 1574 PINCTRL_GRP_UART0_7, 1575 PINCTRL_GRP_TRACE0_1, 1576 END_OF_GROUPS, 1577 }), 1578 }, 1579 [PINCTRL_PIN_32] = { 1580 .groups = &((uint16_t []) { 1581 PINCTRL_GRP_ETHERNET0_0, 1582 PINCTRL_GRP_NAND0_1_DQS, 1583 PINCTRL_GRP_PMU0_6, 1584 PINCTRL_GRP_TESTSCAN0_0, 1585 PINCTRL_GRP_CSU0_10, 1586 PINCTRL_GRP_GPIO0_32, 1587 PINCTRL_GRP_CAN1_8, 1588 PINCTRL_GRP_I2C1_8, 1589 PINCTRL_GRP_SWDT1_5_CLK, 1590 PINCTRL_GRP_SPI1_2, 1591 PINCTRL_GRP_TTC3_4_CLK, 1592 PINCTRL_GRP_UART1_8, 1593 PINCTRL_GRP_TRACE0_1, 1594 END_OF_GROUPS, 1595 }), 1596 }, 1597 [PINCTRL_PIN_33] = { 1598 .groups = &((uint16_t []) { 1599 PINCTRL_GRP_ETHERNET0_0, 1600 PINCTRL_GRP_PCIE0_3, 1601 PINCTRL_GRP_PMU0_7, 1602 PINCTRL_GRP_TESTSCAN0_0, 1603 PINCTRL_GRP_CSU0_11, 1604 PINCTRL_GRP_GPIO0_33, 1605 PINCTRL_GRP_CAN1_8, 1606 PINCTRL_GRP_I2C1_8, 1607 PINCTRL_GRP_SWDT1_5_RST, 1608 PINCTRL_GRP_SPI1_2_SS2, 1609 PINCTRL_GRP_TTC3_4_WAV, 1610 PINCTRL_GRP_UART1_8, 1611 PINCTRL_GRP_TRACE0_1, 1612 END_OF_GROUPS, 1613 }), 1614 }, 1615 [PINCTRL_PIN_34] = { 1616 .groups = &((uint16_t []) { 1617 PINCTRL_GRP_ETHERNET0_0, 1618 PINCTRL_GRP_PCIE0_4, 1619 PINCTRL_GRP_PMU0_8, 1620 PINCTRL_GRP_TESTSCAN0_0, 1621 PINCTRL_GRP_DPAUX0_2, 1622 PINCTRL_GRP_GPIO0_34, 1623 PINCTRL_GRP_CAN0_8, 1624 PINCTRL_GRP_I2C0_8, 1625 PINCTRL_GRP_SWDT0_5_CLK, 1626 PINCTRL_GRP_SPI1_2_SS1, 1627 PINCTRL_GRP_TTC2_4_CLK, 1628 PINCTRL_GRP_UART0_8, 1629 PINCTRL_GRP_TRACE0_1, 1630 END_OF_GROUPS, 1631 }), 1632 }, 1633 [PINCTRL_PIN_35] = { 1634 .groups = &((uint16_t []) { 1635 PINCTRL_GRP_ETHERNET0_0, 1636 PINCTRL_GRP_PCIE0_5, 1637 PINCTRL_GRP_PMU0_9, 1638 PINCTRL_GRP_TESTSCAN0_0, 1639 PINCTRL_GRP_DPAUX0_2, 1640 PINCTRL_GRP_GPIO0_35, 1641 PINCTRL_GRP_CAN0_8, 1642 PINCTRL_GRP_I2C0_8, 1643 PINCTRL_GRP_SWDT0_5_RST, 1644 PINCTRL_GRP_SPI1_2_SS0, 1645 PINCTRL_GRP_TTC2_4_WAV, 1646 PINCTRL_GRP_UART0_8, 1647 PINCTRL_GRP_TRACE0_1, 1648 END_OF_GROUPS, 1649 }), 1650 }, 1651 [PINCTRL_PIN_36] = { 1652 .groups = &((uint16_t []) { 1653 PINCTRL_GRP_ETHERNET0_0, 1654 PINCTRL_GRP_PCIE0_6, 1655 PINCTRL_GRP_PMU0_10, 1656 PINCTRL_GRP_TESTSCAN0_0, 1657 PINCTRL_GRP_DPAUX0_3, 1658 PINCTRL_GRP_GPIO0_36, 1659 PINCTRL_GRP_CAN1_9, 1660 PINCTRL_GRP_I2C1_9, 1661 PINCTRL_GRP_SWDT1_6_CLK, 1662 PINCTRL_GRP_SPI1_2, 1663 PINCTRL_GRP_TTC1_4_CLK, 1664 PINCTRL_GRP_UART1_9, 1665 PINCTRL_GRP_TRACE0_1, 1666 END_OF_GROUPS, 1667 }), 1668 }, 1669 [PINCTRL_PIN_37] = { 1670 .groups = &((uint16_t []) { 1671 PINCTRL_GRP_ETHERNET0_0, 1672 PINCTRL_GRP_PCIE0_7, 1673 PINCTRL_GRP_PMU0_11, 1674 PINCTRL_GRP_TESTSCAN0_0, 1675 PINCTRL_GRP_DPAUX0_3, 1676 PINCTRL_GRP_GPIO0_37, 1677 PINCTRL_GRP_CAN1_9, 1678 PINCTRL_GRP_I2C1_9, 1679 PINCTRL_GRP_SWDT1_6_RST, 1680 PINCTRL_GRP_SPI1_2, 1681 PINCTRL_GRP_TTC1_4_WAV, 1682 PINCTRL_GRP_UART1_9, 1683 PINCTRL_GRP_TRACE0_1, 1684 END_OF_GROUPS, 1685 }), 1686 }, 1687 [PINCTRL_PIN_38] = { 1688 .groups = &((uint16_t []) { 1689 PINCTRL_GRP_ETHERNET1_0, 1690 PINCTRL_GRP_RESERVED, 1691 PINCTRL_GRP_SDIO0_1, 1692 PINCTRL_GRP_RESERVED, 1693 PINCTRL_GRP_RESERVED, 1694 PINCTRL_GRP_GPIO0_38, 1695 PINCTRL_GRP_CAN0_9, 1696 PINCTRL_GRP_I2C0_9, 1697 PINCTRL_GRP_PJTAG0_3, 1698 PINCTRL_GRP_SPI0_3, 1699 PINCTRL_GRP_TTC0_4_CLK, 1700 PINCTRL_GRP_UART0_9, 1701 PINCTRL_GRP_TRACE0_1_CLK, 1702 PINCTRL_GRP_SDIO0_4BIT_1_0, 1703 PINCTRL_GRP_SDIO0_4BIT_1_1, 1704 PINCTRL_GRP_SDIO0_1BIT_1_0, 1705 PINCTRL_GRP_SDIO0_1BIT_1_1, 1706 PINCTRL_GRP_SDIO0_1BIT_1_2, 1707 PINCTRL_GRP_SDIO0_1BIT_1_3, 1708 PINCTRL_GRP_SDIO0_1BIT_1_4, 1709 PINCTRL_GRP_SDIO0_1BIT_1_5, 1710 PINCTRL_GRP_SDIO0_1BIT_1_6, 1711 PINCTRL_GRP_SDIO0_1BIT_1_7, 1712 END_OF_GROUPS, 1713 }), 1714 }, 1715 [PINCTRL_PIN_39] = { 1716 .groups = &((uint16_t []) { 1717 PINCTRL_GRP_ETHERNET1_0, 1718 PINCTRL_GRP_RESERVED, 1719 PINCTRL_GRP_SDIO0_1_CD, 1720 PINCTRL_GRP_SDIO1_0, 1721 PINCTRL_GRP_RESERVED, 1722 PINCTRL_GRP_GPIO0_39, 1723 PINCTRL_GRP_CAN0_9, 1724 PINCTRL_GRP_I2C0_9, 1725 PINCTRL_GRP_PJTAG0_3, 1726 PINCTRL_GRP_SPI0_3_SS2, 1727 PINCTRL_GRP_TTC0_4_WAV, 1728 PINCTRL_GRP_UART0_9, 1729 PINCTRL_GRP_TRACE0_1_CLK, 1730 PINCTRL_GRP_SDIO1_4BIT_0_0, 1731 PINCTRL_GRP_SDIO1_1BIT_0_0, 1732 END_OF_GROUPS, 1733 }), 1734 }, 1735 [PINCTRL_PIN_40] = { 1736 .groups = &((uint16_t []) { 1737 PINCTRL_GRP_ETHERNET1_0, 1738 PINCTRL_GRP_RESERVED, 1739 PINCTRL_GRP_SDIO0_1, 1740 PINCTRL_GRP_SDIO1_0, 1741 PINCTRL_GRP_RESERVED, 1742 PINCTRL_GRP_GPIO0_40, 1743 PINCTRL_GRP_CAN1_10, 1744 PINCTRL_GRP_I2C1_10, 1745 PINCTRL_GRP_PJTAG0_3, 1746 PINCTRL_GRP_SPI0_3_SS1, 1747 PINCTRL_GRP_TTC3_5_CLK, 1748 PINCTRL_GRP_UART1_10, 1749 PINCTRL_GRP_TRACE0_1, 1750 PINCTRL_GRP_SDIO0_4BIT_1_0, 1751 PINCTRL_GRP_SDIO0_4BIT_1_1, 1752 PINCTRL_GRP_SDIO0_1BIT_1_0, 1753 PINCTRL_GRP_SDIO0_1BIT_1_1, 1754 PINCTRL_GRP_SDIO0_1BIT_1_2, 1755 PINCTRL_GRP_SDIO0_1BIT_1_3, 1756 PINCTRL_GRP_SDIO0_1BIT_1_4, 1757 PINCTRL_GRP_SDIO0_1BIT_1_5, 1758 PINCTRL_GRP_SDIO0_1BIT_1_6, 1759 PINCTRL_GRP_SDIO0_1BIT_1_7, 1760 PINCTRL_GRP_SDIO1_4BIT_0_0, 1761 PINCTRL_GRP_SDIO1_1BIT_0_1, 1762 END_OF_GROUPS, 1763 }), 1764 }, 1765 [PINCTRL_PIN_41] = { 1766 .groups = &((uint16_t []) { 1767 PINCTRL_GRP_ETHERNET1_0, 1768 PINCTRL_GRP_RESERVED, 1769 PINCTRL_GRP_SDIO0_1, 1770 PINCTRL_GRP_SDIO1_0, 1771 PINCTRL_GRP_RESERVED, 1772 PINCTRL_GRP_GPIO0_41, 1773 PINCTRL_GRP_CAN1_10, 1774 PINCTRL_GRP_I2C1_10, 1775 PINCTRL_GRP_PJTAG0_3, 1776 PINCTRL_GRP_SPI0_3_SS0, 1777 PINCTRL_GRP_TTC3_5_WAV, 1778 PINCTRL_GRP_UART1_10, 1779 PINCTRL_GRP_TRACE0_1, 1780 PINCTRL_GRP_SDIO0_4BIT_1_0, 1781 PINCTRL_GRP_SDIO0_1BIT_1_0, 1782 PINCTRL_GRP_SDIO1_4BIT_0_0, 1783 PINCTRL_GRP_SDIO1_1BIT_0_2, 1784 END_OF_GROUPS, 1785 }), 1786 }, 1787 [PINCTRL_PIN_42] = { 1788 .groups = &((uint16_t []) { 1789 PINCTRL_GRP_ETHERNET1_0, 1790 PINCTRL_GRP_RESERVED, 1791 PINCTRL_GRP_SDIO0_1, 1792 PINCTRL_GRP_SDIO1_0, 1793 PINCTRL_GRP_RESERVED, 1794 PINCTRL_GRP_GPIO0_42, 1795 PINCTRL_GRP_CAN0_10, 1796 PINCTRL_GRP_I2C0_10, 1797 PINCTRL_GRP_SWDT0_6_CLK, 1798 PINCTRL_GRP_SPI0_3, 1799 PINCTRL_GRP_TTC2_5_CLK, 1800 PINCTRL_GRP_UART0_10, 1801 PINCTRL_GRP_TRACE0_1, 1802 PINCTRL_GRP_SDIO0_1, 1803 PINCTRL_GRP_SDIO0_4BIT_1_0, 1804 PINCTRL_GRP_SDIO0_1BIT_1_1, 1805 PINCTRL_GRP_SDIO1_4BIT_0_0, 1806 PINCTRL_GRP_SDIO1_1BIT_0_3, 1807 END_OF_GROUPS, 1808 }), 1809 }, 1810 [PINCTRL_PIN_43] = { 1811 .groups = &((uint16_t []) { 1812 PINCTRL_GRP_ETHERNET1_0, 1813 PINCTRL_GRP_RESERVED, 1814 PINCTRL_GRP_SDIO0_1, 1815 PINCTRL_GRP_SDIO1_0_PC, 1816 PINCTRL_GRP_RESERVED, 1817 PINCTRL_GRP_GPIO0_43, 1818 PINCTRL_GRP_CAN0_10, 1819 PINCTRL_GRP_I2C0_10, 1820 PINCTRL_GRP_SWDT0_6_RST, 1821 PINCTRL_GRP_SPI0_3, 1822 PINCTRL_GRP_TTC2_5_WAV, 1823 PINCTRL_GRP_UART0_10, 1824 PINCTRL_GRP_TRACE0_1, 1825 PINCTRL_GRP_SDIO0_4BIT_1_0, 1826 PINCTRL_GRP_SDIO0_1BIT_1_2, 1827 END_OF_GROUPS, 1828 }), 1829 }, 1830 [PINCTRL_PIN_44] = { 1831 .groups = &((uint16_t []) { 1832 PINCTRL_GRP_ETHERNET1_0, 1833 PINCTRL_GRP_RESERVED, 1834 PINCTRL_GRP_SDIO0_1, 1835 PINCTRL_GRP_SDIO1_0_WP, 1836 PINCTRL_GRP_RESERVED, 1837 PINCTRL_GRP_GPIO0_44, 1838 PINCTRL_GRP_CAN1_11, 1839 PINCTRL_GRP_I2C1_11, 1840 PINCTRL_GRP_SWDT1_7_CLK, 1841 PINCTRL_GRP_SPI1_3, 1842 PINCTRL_GRP_TTC1_5_CLK, 1843 PINCTRL_GRP_UART1_11, 1844 PINCTRL_GRP_RESERVED, 1845 PINCTRL_GRP_SDIO0_4BIT_1_0, 1846 PINCTRL_GRP_SDIO0_1BIT_1_3, 1847 END_OF_GROUPS, 1848 }), 1849 }, 1850 [PINCTRL_PIN_45] = { 1851 .groups = &((uint16_t []) { 1852 PINCTRL_GRP_ETHERNET1_0, 1853 PINCTRL_GRP_RESERVED, 1854 PINCTRL_GRP_SDIO0_1, 1855 PINCTRL_GRP_SDIO1_0_CD, 1856 PINCTRL_GRP_RESERVED, 1857 PINCTRL_GRP_GPIO0_45, 1858 PINCTRL_GRP_CAN1_11, 1859 PINCTRL_GRP_I2C1_11, 1860 PINCTRL_GRP_SWDT1_7_RST, 1861 PINCTRL_GRP_SPI1_3_SS2, 1862 PINCTRL_GRP_TTC1_5_WAV, 1863 PINCTRL_GRP_UART1_11, 1864 PINCTRL_GRP_RESERVED, 1865 PINCTRL_GRP_SDIO0_4BIT_1_1, 1866 PINCTRL_GRP_SDIO0_1BIT_1_4, 1867 END_OF_GROUPS, 1868 }), 1869 }, 1870 [PINCTRL_PIN_46] = { 1871 .groups = &((uint16_t []) { 1872 PINCTRL_GRP_ETHERNET1_0, 1873 PINCTRL_GRP_RESERVED, 1874 PINCTRL_GRP_SDIO0_1, 1875 PINCTRL_GRP_SDIO1_0, 1876 PINCTRL_GRP_RESERVED, 1877 PINCTRL_GRP_GPIO0_46, 1878 PINCTRL_GRP_CAN0_11, 1879 PINCTRL_GRP_I2C0_11, 1880 PINCTRL_GRP_SWDT0_7_CLK, 1881 PINCTRL_GRP_SPI1_3_SS1, 1882 PINCTRL_GRP_TTC0_5_CLK, 1883 PINCTRL_GRP_UART0_11, 1884 PINCTRL_GRP_RESERVED, 1885 PINCTRL_GRP_SDIO0_4BIT_1_1, 1886 PINCTRL_GRP_SDIO0_1BIT_1_5, 1887 PINCTRL_GRP_SDIO1_4BIT_0_1, 1888 PINCTRL_GRP_SDIO1_1BIT_0_4, 1889 END_OF_GROUPS, 1890 }), 1891 }, 1892 [PINCTRL_PIN_47] = { 1893 .groups = &((uint16_t []) { 1894 PINCTRL_GRP_ETHERNET1_0, 1895 PINCTRL_GRP_RESERVED, 1896 PINCTRL_GRP_SDIO0_1, 1897 PINCTRL_GRP_SDIO1_0, 1898 PINCTRL_GRP_RESERVED, 1899 PINCTRL_GRP_GPIO0_47, 1900 PINCTRL_GRP_CAN0_11, 1901 PINCTRL_GRP_I2C0_11, 1902 PINCTRL_GRP_SWDT0_7_RST, 1903 PINCTRL_GRP_SPI1_3_SS0, 1904 PINCTRL_GRP_TTC0_5_WAV, 1905 PINCTRL_GRP_UART0_11, 1906 PINCTRL_GRP_RESERVED, 1907 PINCTRL_GRP_SDIO0_4BIT_1_1, 1908 PINCTRL_GRP_SDIO0_1BIT_1_6, 1909 PINCTRL_GRP_SDIO1_4BIT_0_1, 1910 PINCTRL_GRP_SDIO1_1BIT_0_5, 1911 END_OF_GROUPS, 1912 }), 1913 }, 1914 [PINCTRL_PIN_48] = { 1915 .groups = &((uint16_t []) { 1916 PINCTRL_GRP_ETHERNET1_0, 1917 PINCTRL_GRP_RESERVED, 1918 PINCTRL_GRP_SDIO0_1, 1919 PINCTRL_GRP_SDIO1_0, 1920 PINCTRL_GRP_RESERVED, 1921 PINCTRL_GRP_GPIO0_48, 1922 PINCTRL_GRP_CAN1_12, 1923 PINCTRL_GRP_I2C1_12, 1924 PINCTRL_GRP_SWDT1_8_CLK, 1925 PINCTRL_GRP_SPI1_3, 1926 PINCTRL_GRP_TTC3_6_CLK, 1927 PINCTRL_GRP_UART1_12, 1928 PINCTRL_GRP_RESERVED, 1929 PINCTRL_GRP_SDIO0_4BIT_1_1, 1930 PINCTRL_GRP_SDIO0_1BIT_1_7, 1931 PINCTRL_GRP_SDIO1_4BIT_0_1, 1932 PINCTRL_GRP_SDIO1_1BIT_0_6, 1933 END_OF_GROUPS, 1934 }), 1935 }, 1936 [PINCTRL_PIN_49] = { 1937 .groups = &((uint16_t []) { 1938 PINCTRL_GRP_ETHERNET1_0, 1939 PINCTRL_GRP_RESERVED, 1940 PINCTRL_GRP_SDIO0_1_PC, 1941 PINCTRL_GRP_SDIO1_0, 1942 PINCTRL_GRP_RESERVED, 1943 PINCTRL_GRP_GPIO0_49, 1944 PINCTRL_GRP_CAN1_12, 1945 PINCTRL_GRP_I2C1_12, 1946 PINCTRL_GRP_SWDT1_8_RST, 1947 PINCTRL_GRP_SPI1_3, 1948 PINCTRL_GRP_TTC3_6_WAV, 1949 PINCTRL_GRP_UART1_12, 1950 PINCTRL_GRP_RESERVED, 1951 PINCTRL_GRP_SDIO1_4BIT_0_1, 1952 PINCTRL_GRP_SDIO1_1BIT_0_7, 1953 END_OF_GROUPS, 1954 }), 1955 }, 1956 [PINCTRL_PIN_50] = { 1957 .groups = &((uint16_t []) { 1958 PINCTRL_GRP_GEMTSU0_1, 1959 PINCTRL_GRP_RESERVED, 1960 PINCTRL_GRP_SDIO0_1_WP, 1961 PINCTRL_GRP_SDIO1_0, 1962 PINCTRL_GRP_RESERVED, 1963 PINCTRL_GRP_GPIO0_50, 1964 PINCTRL_GRP_CAN0_12, 1965 PINCTRL_GRP_I2C0_12, 1966 PINCTRL_GRP_SWDT0_8_CLK, 1967 PINCTRL_GRP_MDIO1_0, 1968 PINCTRL_GRP_TTC2_6_CLK, 1969 PINCTRL_GRP_UART0_12, 1970 PINCTRL_GRP_RESERVED, 1971 PINCTRL_GRP_SDIO1_4BIT_0_0, 1972 PINCTRL_GRP_SDIO1_4BIT_0_1, 1973 PINCTRL_GRP_SDIO1_1BIT_0_0, 1974 PINCTRL_GRP_SDIO1_1BIT_0_1, 1975 PINCTRL_GRP_SDIO1_1BIT_0_2, 1976 PINCTRL_GRP_SDIO1_1BIT_0_3, 1977 PINCTRL_GRP_SDIO1_1BIT_0_4, 1978 PINCTRL_GRP_SDIO1_1BIT_0_5, 1979 PINCTRL_GRP_SDIO1_1BIT_0_6, 1980 PINCTRL_GRP_SDIO1_1BIT_0_7, 1981 END_OF_GROUPS, 1982 }), 1983 }, 1984 [PINCTRL_PIN_51] = { 1985 .groups = &((uint16_t []) { 1986 PINCTRL_GRP_GEMTSU0_2, 1987 PINCTRL_GRP_RESERVED, 1988 PINCTRL_GRP_RESERVED, 1989 PINCTRL_GRP_SDIO1_0, 1990 PINCTRL_GRP_RESERVED, 1991 PINCTRL_GRP_GPIO0_51, 1992 PINCTRL_GRP_CAN0_12, 1993 PINCTRL_GRP_I2C0_12, 1994 PINCTRL_GRP_SWDT0_8_RST, 1995 PINCTRL_GRP_MDIO1_0, 1996 PINCTRL_GRP_TTC2_6_WAV, 1997 PINCTRL_GRP_UART0_12, 1998 PINCTRL_GRP_RESERVED, 1999 PINCTRL_GRP_SDIO1_4BIT_0_0, 2000 PINCTRL_GRP_SDIO1_4BIT_0_1, 2001 PINCTRL_GRP_SDIO1_1BIT_0_0, 2002 PINCTRL_GRP_SDIO1_1BIT_0_1, 2003 PINCTRL_GRP_SDIO1_1BIT_0_2, 2004 PINCTRL_GRP_SDIO1_1BIT_0_3, 2005 PINCTRL_GRP_SDIO1_1BIT_0_4, 2006 PINCTRL_GRP_SDIO1_1BIT_0_5, 2007 PINCTRL_GRP_SDIO1_1BIT_0_6, 2008 PINCTRL_GRP_SDIO1_1BIT_0_7, 2009 END_OF_GROUPS, 2010 }), 2011 }, 2012 [PINCTRL_PIN_52] = { 2013 .groups = &((uint16_t []) { 2014 PINCTRL_GRP_ETHERNET2_0, 2015 PINCTRL_GRP_USB0_0, 2016 PINCTRL_GRP_RESERVED, 2017 PINCTRL_GRP_RESERVED, 2018 PINCTRL_GRP_RESERVED, 2019 PINCTRL_GRP_GPIO0_52, 2020 PINCTRL_GRP_CAN1_13, 2021 PINCTRL_GRP_I2C1_13, 2022 PINCTRL_GRP_PJTAG0_4, 2023 PINCTRL_GRP_SPI0_4, 2024 PINCTRL_GRP_TTC1_6_CLK, 2025 PINCTRL_GRP_UART1_13, 2026 PINCTRL_GRP_TRACE0_2_CLK, 2027 END_OF_GROUPS, 2028 }), 2029 }, 2030 [PINCTRL_PIN_53] = { 2031 .groups = &((uint16_t []) { 2032 PINCTRL_GRP_ETHERNET2_0, 2033 PINCTRL_GRP_USB0_0, 2034 PINCTRL_GRP_RESERVED, 2035 PINCTRL_GRP_RESERVED, 2036 PINCTRL_GRP_RESERVED, 2037 PINCTRL_GRP_GPIO0_53, 2038 PINCTRL_GRP_CAN1_13, 2039 PINCTRL_GRP_I2C1_13, 2040 PINCTRL_GRP_PJTAG0_4, 2041 PINCTRL_GRP_SPI0_4_SS2, 2042 PINCTRL_GRP_TTC1_6_WAV, 2043 PINCTRL_GRP_UART1_13, 2044 PINCTRL_GRP_TRACE0_2_CLK, 2045 END_OF_GROUPS, 2046 }), 2047 }, 2048 [PINCTRL_PIN_54] = { 2049 .groups = &((uint16_t []) { 2050 PINCTRL_GRP_ETHERNET2_0, 2051 PINCTRL_GRP_USB0_0, 2052 PINCTRL_GRP_RESERVED, 2053 PINCTRL_GRP_RESERVED, 2054 PINCTRL_GRP_RESERVED, 2055 PINCTRL_GRP_GPIO0_54, 2056 PINCTRL_GRP_CAN0_13, 2057 PINCTRL_GRP_I2C0_13, 2058 PINCTRL_GRP_PJTAG0_4, 2059 PINCTRL_GRP_SPI0_4_SS1, 2060 PINCTRL_GRP_TTC0_6_CLK, 2061 PINCTRL_GRP_UART0_13, 2062 PINCTRL_GRP_TRACE0_2, 2063 END_OF_GROUPS, 2064 }), 2065 }, 2066 [PINCTRL_PIN_55] = { 2067 .groups = &((uint16_t []) { 2068 PINCTRL_GRP_ETHERNET2_0, 2069 PINCTRL_GRP_USB0_0, 2070 PINCTRL_GRP_RESERVED, 2071 PINCTRL_GRP_RESERVED, 2072 PINCTRL_GRP_RESERVED, 2073 PINCTRL_GRP_GPIO0_55, 2074 PINCTRL_GRP_CAN0_13, 2075 PINCTRL_GRP_I2C0_13, 2076 PINCTRL_GRP_PJTAG0_4, 2077 PINCTRL_GRP_SPI0_4_SS0, 2078 PINCTRL_GRP_TTC0_6_WAV, 2079 PINCTRL_GRP_UART0_13, 2080 PINCTRL_GRP_TRACE0_2, 2081 END_OF_GROUPS, 2082 }), 2083 }, 2084 [PINCTRL_PIN_56] = { 2085 .groups = &((uint16_t []) { 2086 PINCTRL_GRP_ETHERNET2_0, 2087 PINCTRL_GRP_USB0_0, 2088 PINCTRL_GRP_RESERVED, 2089 PINCTRL_GRP_RESERVED, 2090 PINCTRL_GRP_RESERVED, 2091 PINCTRL_GRP_GPIO0_56, 2092 PINCTRL_GRP_CAN1_14, 2093 PINCTRL_GRP_I2C1_14, 2094 PINCTRL_GRP_SWDT1_9_CLK, 2095 PINCTRL_GRP_SPI0_4, 2096 PINCTRL_GRP_TTC3_7_CLK, 2097 PINCTRL_GRP_UART1_14, 2098 PINCTRL_GRP_TRACE0_2, 2099 END_OF_GROUPS, 2100 }), 2101 }, 2102 [PINCTRL_PIN_57] = { 2103 .groups = &((uint16_t []) { 2104 PINCTRL_GRP_ETHERNET2_0, 2105 PINCTRL_GRP_USB0_0, 2106 PINCTRL_GRP_RESERVED, 2107 PINCTRL_GRP_RESERVED, 2108 PINCTRL_GRP_RESERVED, 2109 PINCTRL_GRP_GPIO0_57, 2110 PINCTRL_GRP_CAN1_14, 2111 PINCTRL_GRP_I2C1_14, 2112 PINCTRL_GRP_SWDT1_9_RST, 2113 PINCTRL_GRP_SPI0_4, 2114 PINCTRL_GRP_TTC3_7_WAV, 2115 PINCTRL_GRP_UART1_14, 2116 PINCTRL_GRP_TRACE0_2, 2117 END_OF_GROUPS, 2118 }), 2119 }, 2120 [PINCTRL_PIN_58] = { 2121 .groups = &((uint16_t []) { 2122 PINCTRL_GRP_ETHERNET2_0, 2123 PINCTRL_GRP_USB0_0, 2124 PINCTRL_GRP_RESERVED, 2125 PINCTRL_GRP_RESERVED, 2126 PINCTRL_GRP_RESERVED, 2127 PINCTRL_GRP_GPIO0_58, 2128 PINCTRL_GRP_CAN0_14, 2129 PINCTRL_GRP_I2C0_14, 2130 PINCTRL_GRP_PJTAG0_5, 2131 PINCTRL_GRP_SPI1_4, 2132 PINCTRL_GRP_TTC2_7_CLK, 2133 PINCTRL_GRP_UART0_14, 2134 PINCTRL_GRP_TRACE0_2, 2135 END_OF_GROUPS, 2136 }), 2137 }, 2138 [PINCTRL_PIN_59] = { 2139 .groups = &((uint16_t []) { 2140 PINCTRL_GRP_ETHERNET2_0, 2141 PINCTRL_GRP_USB0_0, 2142 PINCTRL_GRP_RESERVED, 2143 PINCTRL_GRP_RESERVED, 2144 PINCTRL_GRP_RESERVED, 2145 PINCTRL_GRP_GPIO0_59, 2146 PINCTRL_GRP_CAN0_14, 2147 PINCTRL_GRP_I2C0_14, 2148 PINCTRL_GRP_PJTAG0_5, 2149 PINCTRL_GRP_SPI1_4_SS2, 2150 PINCTRL_GRP_TTC2_7_WAV, 2151 PINCTRL_GRP_UART0_14, 2152 PINCTRL_GRP_TRACE0_2, 2153 END_OF_GROUPS, 2154 }), 2155 }, 2156 [PINCTRL_PIN_60] = { 2157 .groups = &((uint16_t []) { 2158 PINCTRL_GRP_ETHERNET2_0, 2159 PINCTRL_GRP_USB0_0, 2160 PINCTRL_GRP_RESERVED, 2161 PINCTRL_GRP_RESERVED, 2162 PINCTRL_GRP_RESERVED, 2163 PINCTRL_GRP_GPIO0_60, 2164 PINCTRL_GRP_CAN1_15, 2165 PINCTRL_GRP_I2C1_15, 2166 PINCTRL_GRP_PJTAG0_5, 2167 PINCTRL_GRP_SPI1_4_SS1, 2168 PINCTRL_GRP_TTC1_7_CLK, 2169 PINCTRL_GRP_UART1_15, 2170 PINCTRL_GRP_TRACE0_2, 2171 END_OF_GROUPS, 2172 }), 2173 }, 2174 [PINCTRL_PIN_61] = { 2175 .groups = &((uint16_t []) { 2176 PINCTRL_GRP_ETHERNET2_0, 2177 PINCTRL_GRP_USB0_0, 2178 PINCTRL_GRP_RESERVED, 2179 PINCTRL_GRP_RESERVED, 2180 PINCTRL_GRP_RESERVED, 2181 PINCTRL_GRP_GPIO0_61, 2182 PINCTRL_GRP_CAN1_15, 2183 PINCTRL_GRP_I2C1_15, 2184 PINCTRL_GRP_PJTAG0_5, 2185 PINCTRL_GRP_SPI1_4_SS0, 2186 PINCTRL_GRP_TTC1_7_WAV, 2187 PINCTRL_GRP_UART1_15, 2188 PINCTRL_GRP_TRACE0_2, 2189 END_OF_GROUPS, 2190 }), 2191 }, 2192 [PINCTRL_PIN_62] = { 2193 .groups = &((uint16_t []) { 2194 PINCTRL_GRP_ETHERNET2_0, 2195 PINCTRL_GRP_USB0_0, 2196 PINCTRL_GRP_RESERVED, 2197 PINCTRL_GRP_RESERVED, 2198 PINCTRL_GRP_RESERVED, 2199 PINCTRL_GRP_GPIO0_62, 2200 PINCTRL_GRP_CAN0_15, 2201 PINCTRL_GRP_I2C0_15, 2202 PINCTRL_GRP_SWDT0_9_CLK, 2203 PINCTRL_GRP_SPI1_4, 2204 PINCTRL_GRP_TTC0_7_CLK, 2205 PINCTRL_GRP_UART0_15, 2206 PINCTRL_GRP_TRACE0_2, 2207 END_OF_GROUPS, 2208 }), 2209 }, 2210 [PINCTRL_PIN_63] = { 2211 .groups = &((uint16_t []) { 2212 PINCTRL_GRP_ETHERNET2_0, 2213 PINCTRL_GRP_USB0_0, 2214 PINCTRL_GRP_RESERVED, 2215 PINCTRL_GRP_RESERVED, 2216 PINCTRL_GRP_RESERVED, 2217 PINCTRL_GRP_GPIO0_63, 2218 PINCTRL_GRP_CAN0_15, 2219 PINCTRL_GRP_I2C0_15, 2220 PINCTRL_GRP_SWDT0_9_RST, 2221 PINCTRL_GRP_SPI1_4, 2222 PINCTRL_GRP_TTC0_7_WAV, 2223 PINCTRL_GRP_UART0_15, 2224 PINCTRL_GRP_TRACE0_2, 2225 END_OF_GROUPS, 2226 }), 2227 }, 2228 [PINCTRL_PIN_64] = { 2229 .groups = &((uint16_t []) { 2230 PINCTRL_GRP_ETHERNET3_0, 2231 PINCTRL_GRP_USB1_0, 2232 PINCTRL_GRP_SDIO0_2, 2233 PINCTRL_GRP_RESERVED, 2234 PINCTRL_GRP_RESERVED, 2235 PINCTRL_GRP_GPIO0_64, 2236 PINCTRL_GRP_CAN1_16, 2237 PINCTRL_GRP_I2C1_16, 2238 PINCTRL_GRP_SWDT1_10_CLK, 2239 PINCTRL_GRP_SPI0_5, 2240 PINCTRL_GRP_TTC3_8_CLK, 2241 PINCTRL_GRP_UART1_16, 2242 PINCTRL_GRP_TRACE0_2, 2243 PINCTRL_GRP_SDIO0_4BIT_2_0, 2244 PINCTRL_GRP_SDIO0_4BIT_2_1, 2245 PINCTRL_GRP_SDIO0_1BIT_2_0, 2246 PINCTRL_GRP_SDIO0_1BIT_2_1, 2247 PINCTRL_GRP_SDIO0_1BIT_2_2, 2248 PINCTRL_GRP_SDIO0_1BIT_2_3, 2249 PINCTRL_GRP_SDIO0_1BIT_2_4, 2250 PINCTRL_GRP_SDIO0_1BIT_2_5, 2251 PINCTRL_GRP_SDIO0_1BIT_2_6, 2252 PINCTRL_GRP_SDIO0_1BIT_2_7, 2253 END_OF_GROUPS, 2254 }), 2255 }, 2256 [PINCTRL_PIN_65] = { 2257 .groups = &((uint16_t []) { 2258 PINCTRL_GRP_ETHERNET3_0, 2259 PINCTRL_GRP_USB1_0, 2260 PINCTRL_GRP_SDIO0_2_CD, 2261 PINCTRL_GRP_RESERVED, 2262 PINCTRL_GRP_RESERVED, 2263 PINCTRL_GRP_GPIO0_65, 2264 PINCTRL_GRP_CAN1_16, 2265 PINCTRL_GRP_I2C1_16, 2266 PINCTRL_GRP_SWDT1_10_RST, 2267 PINCTRL_GRP_SPI0_5_SS2, 2268 PINCTRL_GRP_TTC3_8_WAV, 2269 PINCTRL_GRP_UART1_16, 2270 PINCTRL_GRP_TRACE0_2, 2271 END_OF_GROUPS, 2272 }), 2273 }, 2274 [PINCTRL_PIN_66] = { 2275 .groups = &((uint16_t []) { 2276 PINCTRL_GRP_ETHERNET3_0, 2277 PINCTRL_GRP_USB1_0, 2278 PINCTRL_GRP_SDIO0_2, 2279 PINCTRL_GRP_RESERVED, 2280 PINCTRL_GRP_RESERVED, 2281 PINCTRL_GRP_GPIO0_66, 2282 PINCTRL_GRP_CAN0_16, 2283 PINCTRL_GRP_I2C0_16, 2284 PINCTRL_GRP_SWDT0_10_CLK, 2285 PINCTRL_GRP_SPI0_5_SS1, 2286 PINCTRL_GRP_TTC2_8_CLK, 2287 PINCTRL_GRP_UART0_16, 2288 PINCTRL_GRP_TRACE0_2, 2289 PINCTRL_GRP_SDIO0_4BIT_2_0, 2290 PINCTRL_GRP_SDIO0_4BIT_2_1, 2291 PINCTRL_GRP_SDIO0_1BIT_2_0, 2292 PINCTRL_GRP_SDIO0_1BIT_2_1, 2293 PINCTRL_GRP_SDIO0_1BIT_2_2, 2294 PINCTRL_GRP_SDIO0_1BIT_2_3, 2295 PINCTRL_GRP_SDIO0_1BIT_2_4, 2296 PINCTRL_GRP_SDIO0_1BIT_2_5, 2297 PINCTRL_GRP_SDIO0_1BIT_2_6, 2298 PINCTRL_GRP_SDIO0_1BIT_2_7, 2299 END_OF_GROUPS, 2300 }), 2301 }, 2302 [PINCTRL_PIN_67] = { 2303 .groups = &((uint16_t []) { 2304 PINCTRL_GRP_ETHERNET3_0, 2305 PINCTRL_GRP_USB1_0, 2306 PINCTRL_GRP_SDIO0_2, 2307 PINCTRL_GRP_RESERVED, 2308 PINCTRL_GRP_RESERVED, 2309 PINCTRL_GRP_GPIO0_67, 2310 PINCTRL_GRP_CAN0_16, 2311 PINCTRL_GRP_I2C0_16, 2312 PINCTRL_GRP_SWDT0_10_RST, 2313 PINCTRL_GRP_SPI0_5_SS0, 2314 PINCTRL_GRP_TTC2_8_WAV, 2315 PINCTRL_GRP_UART0_16, 2316 PINCTRL_GRP_TRACE0_2, 2317 PINCTRL_GRP_SDIO0_4BIT_2_0, 2318 PINCTRL_GRP_SDIO0_1BIT_2_0, 2319 END_OF_GROUPS, 2320 }), 2321 }, 2322 [PINCTRL_PIN_68] = { 2323 .groups = &((uint16_t []) { 2324 PINCTRL_GRP_ETHERNET3_0, 2325 PINCTRL_GRP_USB1_0, 2326 PINCTRL_GRP_SDIO0_2, 2327 PINCTRL_GRP_RESERVED, 2328 PINCTRL_GRP_RESERVED, 2329 PINCTRL_GRP_GPIO0_68, 2330 PINCTRL_GRP_CAN1_17, 2331 PINCTRL_GRP_I2C1_17, 2332 PINCTRL_GRP_SWDT1_11_CLK, 2333 PINCTRL_GRP_SPI0_5, 2334 PINCTRL_GRP_TTC1_8_CLK, 2335 PINCTRL_GRP_UART1_17, 2336 PINCTRL_GRP_TRACE0_2, 2337 PINCTRL_GRP_SDIO0_4BIT_2_0, 2338 PINCTRL_GRP_SDIO0_1BIT_2_1, 2339 END_OF_GROUPS, 2340 }), 2341 }, 2342 [PINCTRL_PIN_69] = { 2343 .groups = &((uint16_t []) { 2344 PINCTRL_GRP_ETHERNET3_0, 2345 PINCTRL_GRP_USB1_0, 2346 PINCTRL_GRP_SDIO0_2, 2347 PINCTRL_GRP_SDIO1_1_WP, 2348 PINCTRL_GRP_RESERVED, 2349 PINCTRL_GRP_GPIO0_69, 2350 PINCTRL_GRP_CAN1_17, 2351 PINCTRL_GRP_I2C1_17, 2352 PINCTRL_GRP_SWDT1_11_RST, 2353 PINCTRL_GRP_SPI0_5, 2354 PINCTRL_GRP_TTC1_8_WAV, 2355 PINCTRL_GRP_UART1_17, 2356 PINCTRL_GRP_TRACE0_2, 2357 PINCTRL_GRP_SDIO0_4BIT_2_0, 2358 PINCTRL_GRP_SDIO0_1BIT_2_2, 2359 END_OF_GROUPS, 2360 }), 2361 }, 2362 [PINCTRL_PIN_70] = { 2363 .groups = &((uint16_t []) { 2364 PINCTRL_GRP_ETHERNET3_0, 2365 PINCTRL_GRP_USB1_0, 2366 PINCTRL_GRP_SDIO0_2, 2367 PINCTRL_GRP_SDIO1_1_PC, 2368 PINCTRL_GRP_RESERVED, 2369 PINCTRL_GRP_GPIO0_70, 2370 PINCTRL_GRP_CAN0_17, 2371 PINCTRL_GRP_I2C0_17, 2372 PINCTRL_GRP_SWDT0_11_CLK, 2373 PINCTRL_GRP_SPI1_5, 2374 PINCTRL_GRP_TTC0_8_CLK, 2375 PINCTRL_GRP_UART0_17, 2376 PINCTRL_GRP_RESERVED, 2377 PINCTRL_GRP_SDIO0_4BIT_2_0, 2378 PINCTRL_GRP_SDIO0_1BIT_2_3, 2379 END_OF_GROUPS, 2380 }), 2381 }, 2382 [PINCTRL_PIN_71] = { 2383 .groups = &((uint16_t []) { 2384 PINCTRL_GRP_ETHERNET3_0, 2385 PINCTRL_GRP_USB1_0, 2386 PINCTRL_GRP_SDIO0_2, 2387 PINCTRL_GRP_SDIO1_4BIT_1_0, 2388 PINCTRL_GRP_RESERVED, 2389 PINCTRL_GRP_GPIO0_71, 2390 PINCTRL_GRP_CAN0_17, 2391 PINCTRL_GRP_I2C0_17, 2392 PINCTRL_GRP_SWDT0_11_RST, 2393 PINCTRL_GRP_SPI1_5_SS2, 2394 PINCTRL_GRP_TTC0_8_WAV, 2395 PINCTRL_GRP_UART0_17, 2396 PINCTRL_GRP_RESERVED, 2397 PINCTRL_GRP_SDIO0_2, 2398 PINCTRL_GRP_SDIO0_4BIT_2_1, 2399 PINCTRL_GRP_SDIO0_1BIT_2_4, 2400 PINCTRL_GRP_SDIO1_1BIT_1_0, 2401 END_OF_GROUPS, 2402 }), 2403 }, 2404 [PINCTRL_PIN_72] = { 2405 .groups = &((uint16_t []) { 2406 PINCTRL_GRP_ETHERNET3_0, 2407 PINCTRL_GRP_USB1_0, 2408 PINCTRL_GRP_SDIO0_2, 2409 PINCTRL_GRP_SDIO1_4BIT_1_0, 2410 PINCTRL_GRP_RESERVED, 2411 PINCTRL_GRP_GPIO0_72, 2412 PINCTRL_GRP_CAN1_18, 2413 PINCTRL_GRP_I2C1_18, 2414 PINCTRL_GRP_SWDT1_12_CLK, 2415 PINCTRL_GRP_SPI1_5_SS1, 2416 PINCTRL_GRP_RESERVED, 2417 PINCTRL_GRP_UART1_18, 2418 PINCTRL_GRP_RESERVED, 2419 PINCTRL_GRP_SDIO0_4BIT_2_1, 2420 PINCTRL_GRP_SDIO0_1BIT_2_5, 2421 PINCTRL_GRP_SDIO1_1BIT_1_1, 2422 END_OF_GROUPS, 2423 }), 2424 }, 2425 [PINCTRL_PIN_73] = { 2426 .groups = &((uint16_t []) { 2427 PINCTRL_GRP_ETHERNET3_0, 2428 PINCTRL_GRP_USB1_0, 2429 PINCTRL_GRP_SDIO0_2, 2430 PINCTRL_GRP_SDIO1_4BIT_1_0, 2431 PINCTRL_GRP_RESERVED, 2432 PINCTRL_GRP_GPIO0_73, 2433 PINCTRL_GRP_CAN1_18, 2434 PINCTRL_GRP_I2C1_18, 2435 PINCTRL_GRP_SWDT1_12_RST, 2436 PINCTRL_GRP_SPI1_5_SS0, 2437 PINCTRL_GRP_RESERVED, 2438 PINCTRL_GRP_UART1_18, 2439 PINCTRL_GRP_RESERVED, 2440 PINCTRL_GRP_SDIO0_4BIT_2_1, 2441 PINCTRL_GRP_SDIO0_1BIT_2_6, 2442 PINCTRL_GRP_SDIO1_1BIT_1_2, 2443 END_OF_GROUPS, 2444 }), 2445 }, 2446 [PINCTRL_PIN_74] = { 2447 .groups = &((uint16_t []) { 2448 PINCTRL_GRP_ETHERNET3_0, 2449 PINCTRL_GRP_USB1_0, 2450 PINCTRL_GRP_SDIO0_2, 2451 PINCTRL_GRP_SDIO1_4BIT_1_0, 2452 PINCTRL_GRP_RESERVED, 2453 PINCTRL_GRP_GPIO0_74, 2454 PINCTRL_GRP_CAN0_18, 2455 PINCTRL_GRP_I2C0_18, 2456 PINCTRL_GRP_SWDT0_12_CLK, 2457 PINCTRL_GRP_SPI1_5, 2458 PINCTRL_GRP_RESERVED, 2459 PINCTRL_GRP_UART0_18, 2460 PINCTRL_GRP_RESERVED, 2461 PINCTRL_GRP_SDIO0_4BIT_2_1, 2462 PINCTRL_GRP_SDIO0_1BIT_2_7, 2463 PINCTRL_GRP_SDIO1_1BIT_1_3, 2464 END_OF_GROUPS, 2465 }), 2466 }, 2467 [PINCTRL_PIN_75] = { 2468 .groups = &((uint16_t []) { 2469 PINCTRL_GRP_ETHERNET3_0, 2470 PINCTRL_GRP_USB1_0, 2471 PINCTRL_GRP_SDIO0_2_PC, 2472 PINCTRL_GRP_SDIO1_4BIT_1_0, 2473 PINCTRL_GRP_RESERVED, 2474 PINCTRL_GRP_GPIO0_75, 2475 PINCTRL_GRP_CAN0_18, 2476 PINCTRL_GRP_I2C0_18, 2477 PINCTRL_GRP_SWDT0_12_RST, 2478 PINCTRL_GRP_SPI1_5, 2479 PINCTRL_GRP_RESERVED, 2480 PINCTRL_GRP_UART0_18, 2481 PINCTRL_GRP_RESERVED, 2482 PINCTRL_GRP_SDIO1_1BIT_1_0, 2483 PINCTRL_GRP_SDIO1_1BIT_1_1, 2484 PINCTRL_GRP_SDIO1_1BIT_1_2, 2485 PINCTRL_GRP_SDIO1_1BIT_1_3, 2486 END_OF_GROUPS, 2487 }), 2488 }, 2489 [PINCTRL_PIN_76] = { 2490 .groups = &((uint16_t []) { 2491 PINCTRL_GRP_RESERVED, 2492 PINCTRL_GRP_RESERVED, 2493 PINCTRL_GRP_SDIO0_2_WP, 2494 PINCTRL_GRP_SDIO1_4BIT_1_0, 2495 PINCTRL_GRP_RESERVED, 2496 PINCTRL_GRP_GPIO0_76, 2497 PINCTRL_GRP_CAN1_19, 2498 PINCTRL_GRP_I2C1_19, 2499 PINCTRL_GRP_MDIO0_0, 2500 PINCTRL_GRP_MDIO1_1, 2501 PINCTRL_GRP_MDIO2_0, 2502 PINCTRL_GRP_MDIO3_0, 2503 PINCTRL_GRP_RESERVED, 2504 PINCTRL_GRP_SDIO1_1BIT_1_0, 2505 PINCTRL_GRP_SDIO1_1BIT_1_1, 2506 PINCTRL_GRP_SDIO1_1BIT_1_2, 2507 PINCTRL_GRP_SDIO1_1BIT_1_3, 2508 END_OF_GROUPS, 2509 }), 2510 }, 2511 [PINCTRL_PIN_77] = { 2512 .groups = &((uint16_t []) { 2513 PINCTRL_GRP_RESERVED, 2514 PINCTRL_GRP_RESERVED, 2515 PINCTRL_GRP_RESERVED, 2516 PINCTRL_GRP_SDIO1_1_CD, 2517 PINCTRL_GRP_RESERVED, 2518 PINCTRL_GRP_GPIO0_77, 2519 PINCTRL_GRP_CAN1_19, 2520 PINCTRL_GRP_I2C1_19, 2521 PINCTRL_GRP_MDIO0_0, 2522 PINCTRL_GRP_MDIO1_1, 2523 PINCTRL_GRP_MDIO2_0, 2524 PINCTRL_GRP_MDIO3_0, 2525 PINCTRL_GRP_RESERVED, 2526 END_OF_GROUPS, 2527 }), 2528 }, 2529 }; 2530 2531 /** 2532 * pm_api_pinctrl_get_num_pins() - PM call to request number of pins 2533 * @npins Number of pins 2534 * 2535 * This function is used by master to get number of pins 2536 * 2537 * @return Returns success. 2538 */ 2539 enum pm_ret_status pm_api_pinctrl_get_num_pins(unsigned int *npins) 2540 { 2541 *npins = MAX_PIN; 2542 2543 return PM_RET_SUCCESS; 2544 } 2545 2546 /** 2547 * pm_api_pinctrl_get_num_functions() - PM call to request number of functions 2548 * @nfuncs Number of functions 2549 * 2550 * This function is used by master to get number of functions 2551 * 2552 * @return Returns success. 2553 */ 2554 enum pm_ret_status pm_api_pinctrl_get_num_functions(unsigned int *nfuncs) 2555 { 2556 *nfuncs = MAX_FUNCTION; 2557 2558 return PM_RET_SUCCESS; 2559 } 2560 2561 /** 2562 * pm_api_pinctrl_get_num_func_groups() - PM call to request number of 2563 * function groups 2564 * @fid Function Id 2565 * @ngroups Number of function groups 2566 * 2567 * This function is used by master to get number of function groups 2568 * 2569 * @return Returns success. 2570 */ 2571 enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid, 2572 unsigned int *ngroups) 2573 { 2574 int i = 0; 2575 uint16_t *grps; 2576 2577 if (fid >= MAX_FUNCTION) 2578 return PM_RET_ERROR_ARGS; 2579 2580 *ngroups = 0; 2581 2582 grps = *pinctrl_functions[fid].groups; 2583 if (grps == NULL) 2584 return PM_RET_SUCCESS; 2585 2586 while (grps[i++] != (uint16_t)END_OF_GROUPS) 2587 (*ngroups)++; 2588 2589 return PM_RET_SUCCESS; 2590 } 2591 2592 /** 2593 * pm_api_pinctrl_get_function_name() - PM call to request a function name 2594 * @fid Function ID 2595 * @name Name of function (max 16 bytes) 2596 * 2597 * This function is used by master to get name of function specified 2598 * by given function ID. 2599 */ 2600 void pm_api_pinctrl_get_function_name(unsigned int fid, char *name) 2601 { 2602 if (fid >= MAX_FUNCTION) 2603 memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN); 2604 else 2605 memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN); 2606 } 2607 2608 /** 2609 * pm_api_pinctrl_get_function_groups() - PM call to request first 6 function 2610 * groups of function Id 2611 * @fid Function ID 2612 * @index Index of next function groups 2613 * @groups Function groups 2614 * 2615 * This function is used by master to get function groups specified 2616 * by given function Id. This API will return 6 function groups with 2617 * a single response. To get other function groups, master should call 2618 * same API in loop with new function groups index till error is returned. 2619 * 2620 * E.g First call should have index 0 which will return function groups 2621 * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return 2622 * function groups 6, 7, 8, 9, 10 and 11 and so on. 2623 * 2624 * Return: Returns status, either success or error+reason. 2625 */ 2626 enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid, 2627 unsigned int index, 2628 uint16_t *groups) 2629 { 2630 unsigned int i; 2631 uint16_t *grps; 2632 2633 if (fid >= MAX_FUNCTION) 2634 return PM_RET_ERROR_ARGS; 2635 2636 memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); 2637 2638 grps = *pinctrl_functions[fid].groups; 2639 if (grps == NULL) 2640 return PM_RET_SUCCESS; 2641 2642 /* Skip groups till index */ 2643 for (i = 0; i < index; i++) 2644 if (grps[i] == (uint16_t)END_OF_GROUPS) 2645 return PM_RET_SUCCESS; 2646 2647 for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { 2648 groups[i] = grps[index + i]; 2649 if (groups[i] == (uint16_t)END_OF_GROUPS) 2650 break; 2651 } 2652 2653 return PM_RET_SUCCESS; 2654 } 2655 2656 /** 2657 * pm_api_pinctrl_get_pin_groups() - PM call to request first 6 pin 2658 * groups of pin 2659 * @pin Pin 2660 * @index Index of next pin groups 2661 * @groups pin groups 2662 * 2663 * This function is used by master to get pin groups specified 2664 * by given pin Id. This API will return 6 pin groups with 2665 * a single response. To get other pin groups, master should call 2666 * same API in loop with new pin groups index till error is returned. 2667 * 2668 * E.g First call should have index 0 which will return pin groups 2669 * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return 2670 * pin groups 6, 7, 8, 9, 10 and 11 and so on. 2671 * 2672 * Return: Returns status, either success or error+reason. 2673 */ 2674 enum pm_ret_status pm_api_pinctrl_get_pin_groups(unsigned int pin, 2675 unsigned int index, 2676 uint16_t *groups) 2677 { 2678 unsigned int i; 2679 uint16_t *grps; 2680 2681 if (pin >= MAX_PIN) 2682 return PM_RET_ERROR_ARGS; 2683 2684 memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); 2685 2686 grps = *zynqmp_pin_groups[pin].groups; 2687 if (!grps) 2688 return PM_RET_SUCCESS; 2689 2690 /* Skip groups till index */ 2691 for (i = 0; i < index; i++) 2692 if (grps[i] == (uint16_t)END_OF_GROUPS) 2693 return PM_RET_SUCCESS; 2694 2695 for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { 2696 groups[i] = grps[index + i]; 2697 if (groups[i] == (uint16_t)END_OF_GROUPS) 2698 break; 2699 } 2700 2701 return PM_RET_SUCCESS; 2702 } 2703 2704 /** 2705 * pm_api_pinctrl_set_config() - Set configuration parameter for given pin 2706 * @pin: Pin for which configuration is to be set 2707 * @param: Configuration parameter to be set 2708 * @value: Value to be set for configuration parameter 2709 * 2710 * This function sets value of requested configuration parameter for given pin. 2711 * 2712 * @return Returns status, either success or error+reason 2713 */ 2714 enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin, 2715 unsigned int param, 2716 unsigned int value) 2717 { 2718 enum pm_ret_status ret; 2719 unsigned int ctrlreg, mask, val, offset; 2720 2721 if (param >= PINCTRL_CONFIG_MAX) 2722 return PM_RET_ERROR_NOTSUPPORTED; 2723 2724 if (pin >= PINCTRL_NUM_MIOS) 2725 return PM_RET_ERROR_ARGS; 2726 2727 mask = 1 << PINCTRL_PIN_OFFSET(pin); 2728 2729 switch (param) { 2730 case PINCTRL_CONFIG_SLEW_RATE: 2731 if (value != PINCTRL_SLEW_RATE_FAST && 2732 value != PINCTRL_SLEW_RATE_SLOW) 2733 return PM_RET_ERROR_ARGS; 2734 2735 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2736 PINCTRL_SLEWCTRL_REG_OFFSET, 2737 pin); 2738 val = value << PINCTRL_PIN_OFFSET(pin); 2739 ret = pm_mmio_write(ctrlreg, mask, val); 2740 break; 2741 case PINCTRL_CONFIG_BIAS_STATUS: 2742 if (value != PINCTRL_BIAS_ENABLE && 2743 value != PINCTRL_BIAS_DISABLE) 2744 return PM_RET_ERROR_ARGS; 2745 2746 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2747 PINCTRL_PULLSTAT_REG_OFFSET, 2748 pin); 2749 2750 offset = PINCTRL_PIN_OFFSET(pin); 2751 if (ctrlreg == IOU_SLCR_BANK1_CTRL5) 2752 offset = (offset < 12U) ? 2753 (offset + 14U) : (offset - 12U); 2754 2755 val = value << offset; 2756 mask = 1 << offset; 2757 ret = pm_mmio_write(ctrlreg, mask, val); 2758 break; 2759 case PINCTRL_CONFIG_PULL_CTRL: 2760 2761 if (value != PINCTRL_BIAS_PULL_DOWN && 2762 value != PINCTRL_BIAS_PULL_UP) 2763 return PM_RET_ERROR_ARGS; 2764 2765 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2766 PINCTRL_PULLSTAT_REG_OFFSET, 2767 pin); 2768 2769 offset = PINCTRL_PIN_OFFSET(pin); 2770 if (ctrlreg == IOU_SLCR_BANK1_CTRL5) 2771 offset = (offset < 12U) ? 2772 (offset + 14U) : (offset - 12U); 2773 2774 val = PINCTRL_BIAS_ENABLE << offset; 2775 ret = pm_mmio_write(ctrlreg, 1 << offset, val); 2776 if (ret != PM_RET_SUCCESS) 2777 return ret; 2778 2779 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2780 PINCTRL_PULLCTRL_REG_OFFSET, 2781 pin); 2782 val = value << PINCTRL_PIN_OFFSET(pin); 2783 ret = pm_mmio_write(ctrlreg, mask, val); 2784 break; 2785 case PINCTRL_CONFIG_SCHMITT_CMOS: 2786 if (value != PINCTRL_INPUT_TYPE_CMOS && 2787 value != PINCTRL_INPUT_TYPE_SCHMITT) 2788 return PM_RET_ERROR_ARGS; 2789 2790 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2791 PINCTRL_SCHCMOS_REG_OFFSET, 2792 pin); 2793 2794 val = value << PINCTRL_PIN_OFFSET(pin); 2795 ret = pm_mmio_write(ctrlreg, mask, val); 2796 break; 2797 case PINCTRL_CONFIG_DRIVE_STRENGTH: 2798 if (value > PINCTRL_DRIVE_STRENGTH_12MA) 2799 return PM_RET_ERROR_ARGS; 2800 2801 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2802 PINCTRL_DRVSTRN0_REG_OFFSET, 2803 pin); 2804 val = (value >> 1) << PINCTRL_PIN_OFFSET(pin); 2805 ret = pm_mmio_write(ctrlreg, mask, val); 2806 if (ret) 2807 return ret; 2808 2809 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2810 PINCTRL_DRVSTRN1_REG_OFFSET, 2811 pin); 2812 val = (value & 0x01U) << PINCTRL_PIN_OFFSET(pin); 2813 ret = pm_mmio_write(ctrlreg, mask, val); 2814 break; 2815 default: 2816 ERROR("Invalid parameter %u\n", param); 2817 ret = PM_RET_ERROR_NOTSUPPORTED; 2818 break; 2819 } 2820 2821 return ret; 2822 } 2823 2824 /** 2825 * pm_api_pinctrl_get_config() - Get configuration parameter value for given pin 2826 * @pin: Pin for which configuration is to be read 2827 * @param: Configuration parameter to be read 2828 * @value: buffer to store value of configuration parameter 2829 * 2830 * This function reads value of requested configuration parameter for given pin. 2831 * 2832 * @return Returns status, either success or error+reason 2833 */ 2834 enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin, 2835 unsigned int param, 2836 unsigned int *value) 2837 { 2838 enum pm_ret_status ret; 2839 unsigned int ctrlreg, val; 2840 2841 if (param >= PINCTRL_CONFIG_MAX) 2842 return PM_RET_ERROR_NOTSUPPORTED; 2843 2844 if (pin >= PINCTRL_NUM_MIOS) 2845 return PM_RET_ERROR_ARGS; 2846 2847 switch (param) { 2848 case PINCTRL_CONFIG_SLEW_RATE: 2849 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2850 PINCTRL_SLEWCTRL_REG_OFFSET, 2851 pin); 2852 2853 ret = pm_mmio_read(ctrlreg, &val); 2854 if (ret != PM_RET_SUCCESS) 2855 return ret; 2856 2857 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 2858 break; 2859 case PINCTRL_CONFIG_BIAS_STATUS: 2860 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2861 PINCTRL_PULLSTAT_REG_OFFSET, 2862 pin); 2863 2864 ret = pm_mmio_read(ctrlreg, &val); 2865 if (ret) 2866 return ret; 2867 2868 if (ctrlreg == IOU_SLCR_BANK1_CTRL5) 2869 val = ((val & 0x3FFF) << 12) | ((val >> 14) & 0xFFF); 2870 2871 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 2872 break; 2873 case PINCTRL_CONFIG_PULL_CTRL: 2874 2875 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2876 PINCTRL_PULLCTRL_REG_OFFSET, 2877 pin); 2878 2879 ret = pm_mmio_read(ctrlreg, &val); 2880 if (ret) 2881 return ret; 2882 2883 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 2884 break; 2885 case PINCTRL_CONFIG_SCHMITT_CMOS: 2886 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2887 PINCTRL_SCHCMOS_REG_OFFSET, 2888 pin); 2889 2890 ret = pm_mmio_read(ctrlreg, &val); 2891 if (ret) 2892 return ret; 2893 2894 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 2895 break; 2896 case PINCTRL_CONFIG_DRIVE_STRENGTH: 2897 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2898 PINCTRL_DRVSTRN0_REG_OFFSET, 2899 pin); 2900 ret = pm_mmio_read(ctrlreg, &val); 2901 if (ret) 2902 return ret; 2903 2904 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val) << 1; 2905 2906 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2907 PINCTRL_DRVSTRN1_REG_OFFSET, 2908 pin); 2909 ret = pm_mmio_read(ctrlreg, &val); 2910 if (ret) 2911 return ret; 2912 2913 *value |= PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 2914 break; 2915 case PINCTRL_CONFIG_VOLTAGE_STATUS: 2916 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2917 PINCTRL_VOLTAGE_STAT_REG_OFFSET, 2918 pin); 2919 2920 ret = pm_mmio_read(ctrlreg, &val); 2921 if (ret) 2922 return ret; 2923 2924 *value = val & PINCTRL_VOLTAGE_STATUS_MASK; 2925 break; 2926 default: 2927 return PM_RET_ERROR_NOTSUPPORTED; 2928 } 2929 2930 return PM_RET_SUCCESS; 2931 } 2932