feat(fvp): add SoC name support to FVP

This patch adds support in the FVP platform for the SoC name
field in SMCCC_ARCH_SOC_ID. The returned string is formatted as:

"Arm Platform Revision <SoC Re

feat(fvp): add SoC name support to FVP

This patch adds support in the FVP platform for the SoC name
field in SMCCC_ARCH_SOC_ID. The returned string is formatted as:

"Arm Platform Revision <SoC Revision>"

This adheres to the guideline that the SoC name must not expose
information beyond what is already captured in <SoC Version, SoC
Revision>.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I83da745a754c6fc8f9fa27ee8d8024d6692d3409

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feat(smccc): add SoC name support to SMCCC_ARCH_SOC_ID

This patch adds support for getting the SoC name string
using the SMCCC_ARCH_SOC_ID interface. The SoC name query
was introduced in SMCCC versi

feat(smccc): add SoC name support to SMCCC_ARCH_SOC_ID

This patch adds support for getting the SoC name string
using the SMCCC_ARCH_SOC_ID interface. The SoC name query
was introduced in SMCCC version 1.6. It is available only
through SMC64 calls.

A new function ID, SMCCC_GET_SOC_NAME, is added. It returns
the SoC name as a null-terminated ASCII string, spread across
registers X1 to X17 in little endian order.
The total length is 136 bytes, including the null byte.
Any space after the null terminator is filled
with zeros.

A platform hook plat_get_soc_name() is added to return the
SoC name. A weak default version is also provided that returns
SMC_ARCH_CALL_NOT_SUPPORTED for platforms that do not support
this feature.

The name should follow the SMCCC rule that it must not expose
any information that is not already reported
by the SoC version and revision calls.

Reference: https://developer.arm.com/documentation/den0028/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idc69997c509bcbfb1cecb38ed1003b29627ade4b

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Merge "feat(mt8189): add support display driver" into integration

fix(intel): configure usb3 system manager reg in TFA

Reset pulse override bit needs to be set for successful
reset staggering pulse generation.

The bit one of power over-current field actually refl

fix(intel): configure usb3 system manager reg in TFA

Reset pulse override bit needs to be set for successful
reset staggering pulse generation.

The bit one of power over-current field actually reflects
PIPE power present signal. This bit needs to be set to
avoid providing false information about VBus to the
HPS controller.

Change-Id: I123e2ec7c8ceaa15f47f90460fae5a325741dd10
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update TFA to patch for Linux 6.12 rebase warning message

On MMU-500 r2p0+ (used in newer SoCFPGA platforms),
we need to clear the SMMU_sACR.CACHE_LOCK bit
so the normal world can write

fix(intel): update TFA to patch for Linux 6.12 rebase warning message

On MMU-500 r2p0+ (used in newer SoCFPGA platforms),
we need to clear the SMMU_sACR.CACHE_LOCK bit
so the normal world can write to SMMU_CBn_ACTLR.

Change-Id: I0d0d227950508a2969fe0fe2eddbe6894efe54bc
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(juno): support StandaloneMm

Support StandaloneMm in Juno platform.
When Juno using StandaloneMm, last 2MB area of norflash0 is used by
StandaloneMm only and that area shouldn't be accessed by n

feat(juno): support StandaloneMm

Support StandaloneMm in Juno platform.
When Juno using StandaloneMm, last 2MB area of norflash0 is used by
StandaloneMm only and that area shouldn't be accessed by normal world.
For this, add last 2MB area of norflash0 in TZC setting.

Change-Id: Ice63f13c34f452f2b8cb93ee88dc666632b84248
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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fix(imx8m): don't reconfigure default region0

The current code and comments can be read as: "The TZC-380 region 0 can
be configured in size and attributes". This is not true, only the
attributes can

fix(imx8m): don't reconfigure default region0

The current code and comments can be read as: "The TZC-380 region 0 can
be configured in size and attributes". This is not true, only the
attributes can be set.

The TZC-380 region 0 is the TZC default (fallback) region. This region
is used if access to a certain DRAM address was done which isn't covered
by any other region (see [1] for more information). Region 0 covers the
complete AXI space from 0x0 to AXI-bus width. The access is secure-only
after reset.

The TZC-380 is not memory alias aware (see [1] for more information) and
due to the DDR controller, the i.MX8M allows memory alias access.

Configuring region 0 as secure + non-secure RW access opens the
potential security risk of allowing access to secure only memory e.g.
TEE memory area if the TEE didn't configure all memory aliases for its
memory. In such case region 0 is used as fallback if an attackers access
the TEE memory via memory aliases.

To fix this don't touch the TZC-380 at all. The TZC-380 is bypassed
by default if a platform doesn't require a TEE. If the platform requires
a TEE, the TEE is the one which knows the secure areas so let the TEE
configure the TZC-380 accordingly.

Furthmore, since commits:
- 0324081af010 ("feat(imx8mp): restrict peripheral access to secure
world")
- 1156c76361c1 ("feat(imx8mm): restrict peripheral access to secure
world")
the access is limited to the TEE too.

[1] https://developer.arm.com/documentation/ddi0431/c

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I0a0f9b5ad0017f38d767f583d7765a2f79861589

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fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a diff

fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I04089721d124a2701e10d3f6e0ed8f82e3f6e0b3
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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feat(psci): make pabandon support generic

Support for aborted powerdowns does not require much dedicated code.
Rather, it is largely a matter of orchestrating things to happen in the
right order.

T

feat(psci): make pabandon support generic

Support for aborted powerdowns does not require much dedicated code.
Rather, it is largely a matter of orchestrating things to happen in the
right order.

The only exception to this are older secure world dispatchers, which
assume that a CPU_SUSPEND call will be terminal and therefore can
clobber context. This was patched over in common code and hidden behind
a flag. This patch moves this to the dispatchers themselves.

Dispatchers that don't register svc_suspend{_finish} are unaffected.
Those that do must save the NS context before clobbering it and
restoring in only in case of a pabandon. Due to this operation being
non-trivial, this patch makes the assumption that these dispatchers will
only be present on hardware that does not support pabandon and therefore
does not add any contexting for them. In case this assumption ever
changes, asserts are added that should alert us of this change.

Change-Id: I94a907515b782b4d2136c0d274246cfe1d567c0e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(platforms): remove usage of psci_power_down_wfi

The callers in PSCI will now call wfi() after calling the
pwr_domain_pwr_down() platform hook (previously they were mutually
exclusive). As s

refactor(platforms): remove usage of psci_power_down_wfi

The callers in PSCI will now call wfi() after calling the
pwr_domain_pwr_down() platform hook (previously they were mutually
exclusive). As such, there is no need for platforms to do this
themselves. In fact, it is strongly advisable for platforms not to do
this themselves so that the PSCI can apply any relevant errata
mitigations.

Change-Id: Ic9702edef7503996be24d984e29dfcc13bc3fcba
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(mt8189): add support display driver

After a suspend/resume cycle, the display's register state reverts to
its default state. Therefore, display must set the register state
to normal, allowing t

feat(mt8189): add support display driver

After a suspend/resume cycle, the display's register state reverts to
its default state. Therefore, display must set the register state
to normal, allowing the GCE and CPU to have the authority to configure
this register.

Signed-off-by: xiandong.wang <xiandong.wang@mediatek.com>
Change-Id: I124eb0eae17d7ab263c23374b70c3b6155dc7c3a

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refactor(mediatek): move mtcmos driver to common

Move mtcmos driver to common.

Signed-off-by: irving-ch-lin <irving-ch.lin@mediatek.com>
Change-Id: Id7e0b4ca7596d75ee94bd8d8a855d1bb60f66bdc

feat(stm32mp2): prepare DDR secure area encryption

The RISAF4 defines the DDR secure areas with specific security setup
(encryption). Its master key needs to be written before any activation.
This i

feat(stm32mp2): prepare DDR secure area encryption

The RISAF4 defines the DDR secure areas with specific security setup
(encryption). Its master key needs to be written before any activation.
This is done only if SoC supports encryption.

Change-Id: I38e6af65cadf9678a75be1b861ee0c5beea5bcb9
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(stm32mp2): add some platform helpers

Update STM32MP2 the platform files.
Implement the helpers for STM32MP2, as we have them for STM32MP1:
stm32mp_is_single_core, stm32mp_check_closed_device an

feat(stm32mp2): add some platform helpers

Update STM32MP2 the platform files.
Implement the helpers for STM32MP2, as we have them for STM32MP1:
stm32mp_is_single_core, stm32mp_check_closed_device and
stm32mp_is_auth_supported

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I1554efdb05338f07b292e77175db5a564cc25c78

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feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(t

feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(through FCONF compliance) or statically.

The driver is enabled as BL2 sources. Add driver-related platform
services.
RISAF base addresses and key size are set in platform definitions.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iae99985e8db7cb2b27f9ca25669e74c8e08792d2

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Merge changes I801cea04,I4abb6c9d,I3c1cc0ec,I1b6f69ad,Ic4086a1f into integration

* changes:
refactor(build): pass TF_CFLAGS to the assembler
refactor(build): absorb CFLAGS into TF_CFLAGS
refac

Merge changes I801cea04,I4abb6c9d,I3c1cc0ec,I1b6f69ad,Ic4086a1f into integration

* changes:
refactor(build): pass TF_CFLAGS to the assembler
refactor(build): absorb CFLAGS into TF_CFLAGS
refactor(build): use a standard rule to run the preprocessor
refactor(build): place all cflags setting in one place
refactor(build): simplify ENABLE_LTO checking

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feat(stm32mp1): prepare DDR secure area encryption for STM32MP13

The Memory Cipher Engine (MCE) defines the DDR secure area with
specific security setup (encryption).
Its master key is randomly gene

feat(stm32mp1): prepare DDR secure area encryption for STM32MP13

The Memory Cipher Engine (MCE) defines the DDR secure area with
specific security setup (encryption).
Its master key is randomly generated (using RNG driver).
Initialize and configure MCE IP on platform side only if
authentication is supported at SoC level.

Change-Id: I034f45b0fd547d924cbc92c42298e1f3b1e7343c
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp1): enable MCE driver for STM32MP13

Enabled as BL2 sources.
Add MCE base address and key size in platform definitions.

Change-Id: Icb7d9d7a56806a86e6d0a76640a375a5b5e88a2a
Signed-off-by

feat(stm32mp1): enable MCE driver for STM32MP13

Enabled as BL2 sources.
Add MCE base address and key size in platform definitions.

Change-Id: Icb7d9d7a56806a86e6d0a76640a375a5b5e88a2a
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(st): add RNG minor version

Some specific configurations (NIST/HTCR) can depend on the RNG IP minor
version used.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I3608

feat(st): add RNG minor version

Some specific configurations (NIST/HTCR) can depend on the RNG IP minor
version used.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I3608bd5cad77616bf0c031c66a8312b65d3e68c5

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feat(stm32mp2): add HASH and RNG compilation

Add the drivers compilation in STM32MP2 platform.mk.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9916d1c3da3f9f68ea4d52ca15ea7892

feat(stm32mp2): add HASH and RNG compilation

Add the drivers compilation in STM32MP2 platform.mk.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9916d1c3da3f9f68ea4d52ca15ea7892eff66c99

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refactor(build): use a standard rule to run the preprocessor

There are a few, functionally identical, ways to call the preprocessor
on a non-C file, depending on the file. They differ in subtle, not

refactor(build): use a standard rule to run the preprocessor

There are a few, functionally identical, ways to call the preprocessor
on a non-C file, depending on the file. They differ in subtle, not
entirely correct, ways - one is missing a dependency to the makefiles,
another generates its .d inline, and the prints are different. That has
resulted in platforms reimplementing this functionality, making the
build brittle - a change to the overall build system doesn't propagate.
So add a MAKE_PRE macro that will make a rule with all the bells and
whistles to run the preprocessor on an arbitrary file.

This patch converts the arm platforms' cot_descriptors DTS rules. The
files are renamed to fit with the build rule and all extra flags are
dropped. Those flags are only necessary for building BL2 c files, which
will be passed to the output C file. Only the DTS flags are needed for
the preprocessing step, which will be passed automatically.

Change-Id: I3c1cc0ecf93b87d828f868214928c1bc9bcb5758
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(mt8189): add reset and poweroff function for PSCI call

Add reset and poweroff function for PSCI call.

Change-Id: I8bdf79e81f2fa1920d02af904d53eb610825d5e2
Signed-off-by: Gavin Liu <gavin.liu@m

feat(mt8189): add reset and poweroff function for PSCI call

Add reset and poweroff function for PSCI call.

Change-Id: I8bdf79e81f2fa1920d02af904d53eb610825d5e2
Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>

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feat(mt8189): link prebuilt library

If MTKLIB_PATH is provided, the build will use the library provided
by MTKLIB_PATH. Otherwise, it will use stub implementation.

Signed-off-by: Gavin Liu <gavin.l

feat(mt8189): link prebuilt library

If MTKLIB_PATH is provided, the build will use the library provided
by MTKLIB_PATH. Otherwise, it will use stub implementation.

Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>
Change-Id: I0eebfdf69ab1d4f7788b3cc6de26e47587f6b906

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Merge "feat(st): use and override default MBedTLS config" into integration

fix(xilinx): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a d

fix(xilinx): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I1640a5f40f9471abf4023234ebdbc47018473c56
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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