feat(mt8189): enable DCM to support LP mode

Move the mt8188 DCM driver to common code to support both mt8188 and
mt8189 platforms. This promotes better code sharing and improves
maintainability.

En

feat(mt8189): enable DCM to support LP mode

Move the mt8188 DCM driver to common code to support both mt8188 and
mt8189 platforms. This promotes better code sharing and improves
maintainability.

Enable Dynamic Clock Management (DCM) for MT8189 to optimize power
efficiency during low power (LP) mode. When activated, DCM automatically
disables unused clocks when the bus is idle and resumes them as needed
during bus activity.

Signed-off-by: Rabio-Wang <guanghui.wang@mediatek.com>
Change-Id: I2f9665156c0118cd04109a3cedec4c63381e47c1

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feat(fvp): add the GICv5 config

The GICv5 FVP needs a gic_config.yaml file to fully configure the
platform. The device tree that is provided is tied to this configuration
and one does not come in th

feat(fvp): add the GICv5 config

The GICv5 FVP needs a gic_config.yaml file to fully configure the
platform. The device tree that is provided is tied to this configuration
and one does not come in the public package. So add a gic_config.yaml to
have an easy means of fully defining the platform with what we expect.
The provided yaml will also boot Linux.

Change-Id: Ib4994807fe397a86f730bd18b163e55453988b5d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sasc

feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Co-developed-by: Lorenzo Pieralisi <lorenzo.pieralisi2@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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chore(fvp): remove redundant tsp manifest definitions

They are never consumed as the macros that use them are not used.

Change-Id: Ifcc0e7875f0dd3a842c80e3180119cd8f6818c87
Signed-off-by: Boyan Kar

chore(fvp): remove redundant tsp manifest definitions

They are never consumed as the macros that use them are not used.

Change-Id: Ifcc0e7875f0dd3a842c80e3180119cd8f6818c87
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(mt8189): fix mt_spm_pmic coverity

The original VCORE_TO_PMIC_VAL(VCORE_0_35V) returns negative number
(VCORE_BASE_UV = 40V) and cause min voltage underflow
(-7 -> 4294967289).

Set_vcore_lp_volt

fix(mt8189): fix mt_spm_pmic coverity

The original VCORE_TO_PMIC_VAL(VCORE_0_35V) returns negative number
(VCORE_BASE_UV = 40V) and cause min voltage underflow
(-7 -> 4294967289).

Set_vcore_lp_volt will become dead code and the below condition is
not met: vol >= 4294967289 and vol <= 56(VCORE_0_75V).

Change min voltage to VCORE_0_45V suggested by designer.

Signed-off-by: irving-ch-lin <irving-ch.lin@mediatek.com>
Change-Id: I8fb33d52d58ba084cc4299ea1f9327c71e4ea9eb

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Merge "feat(mt8189): add mcdi driver" into integration

fix(versal-net): add fallback on handoff failure

On the Versal-Net platform, booting can fail during ELF loading due to
the absence of a PLM handoff, preventing the system from booting
further.

To

fix(versal-net): add fallback on handoff failure

On the Versal-Net platform, booting can fail during ELF loading due to
the absence of a PLM handoff, preventing the system from booting
further.

To address this, a fallback mechanism has been introduced that allows
the boot process to continue even if the PLM handoff is not provided
only in debug builds with jtag boot mode.

Change-Id: Ib8d92ab8400b7a63b05ae8c77b40b30fe7abaab8
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(mt8189): add mt8189 mtcmos platform data

Add mt8189 mtcmos platform data.

Signed-off-by: irving-ch-lin <irving-ch.lin@mediatek.com>
Change-Id: I8c979522c6105faac40e0e8f5438718063eba1a4

refactor(mt8196): refactor mtcmos driver to support per platform data

Change for seperating platform in mtcmos control:
1. Pass bus protect steps table to spm_mtcmos_ctrl_bus_prot
2. Pass has_sram f

refactor(mt8196): refactor mtcmos driver to support per platform data

Change for seperating platform in mtcmos control:
1. Pass bus protect steps table to spm_mtcmos_ctrl_bus_prot
2. Pass has_sram flags for sram control
3. Use rtff_save_flag for chip without hw RTFF_SAVE_FLAG

Add mt8196 platform data:
1. RTFF related control bit in register
2. PWR_CON address
3. bus protect steps tables

Signed-off-by: irving-ch-lin <irving-ch.lin@mediatek.com>
Change-Id: I7b39bf5b590cc5cc53f4f3625a7d5a7b4de7cdcb

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feat(mt8189): add mcdi driver

Minor hardware changes require minor driver updates.

Signed-off-by: Kai Liang <kai.liang@mediatek.corp-partner.google.com>
Change-Id: Ifd8f248f0ab18a5e6a4e27fce3b3f345

feat(mt8189): add mcdi driver

Minor hardware changes require minor driver updates.

Signed-off-by: Kai Liang <kai.liang@mediatek.corp-partner.google.com>
Change-Id: Ifd8f248f0ab18a5e6a4e27fce3b3f345bb50d901

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Merge changes Iab4a77a6,I38c32fa3 into integration

* changes:
feat(mt8189): add support for PTP3
refactor(mediatek): move ptp3_plat.h to common code

fix(intel): select the DFI interface based on the hand-off data

Select the DFI interface based on the hand-off power
gate enable data, whether NAND or SDMMC controller is
selected based on this data

fix(intel): select the DFI interface based on the hand-off data

Select the DFI interface based on the hand-off power
gate enable data, whether NAND or SDMMC controller is
selected based on this data.

Change-Id: I097b7f84874368a5ed265d8fa7fff193f430b245
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix iossm driver timeout in agilex5

bl2_plat_setup.c: check return value for
agilex5_ddr_init. If init fail, it will go into
panic. This will help future debug to root cause
the actual i

fix(intel): fix iossm driver timeout in agilex5

bl2_plat_setup.c: check return value for
agilex5_ddr_init. If init fail, it will go into
panic. This will help future debug to root cause
the actual issue.

agilex5_iossm_mailbox.c: corrected divisor
for read_count in inline_ecc_bist_mem_init. Wrong
divisor will cause read_count to be 0. The same
value is also used in out_of_band_ecc_bist_mem_init.

Change-Id: I4c85d251b7e88f3176902917450572adb574b33a
Signed-off-by: Goh Shun Jing <shun.jing.goh@altera.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): set BIT2 of system manager MPFE Interface Select

Set BIT2 of system manager MPFE Interface Select register to
access the EMIF_1.

Change-Id: I6bb2776e5320bde326c6bf97cb785389cad5fb90
Sig

fix(intel): set BIT2 of system manager MPFE Interface Select

Set BIT2 of system manager MPFE Interface Select register to
access the EMIF_1.

Change-Id: I6bb2776e5320bde326c6bf97cb785389cad5fb90
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): unexpected DDR reset type value observed on Agilex5

Redesign the reset type detection logic in the DDR driver.
Implement a more robust and comprehensive check that accurately
distinguish

fix(intel): unexpected DDR reset type value observed on Agilex5

Redesign the reset type detection logic in the DDR driver.
Implement a more robust and comprehensive check that accurately
distinguishes all possible DDR_RESET_TYPE values, including 0x4
and any future additions.

Change-Id: I8f1abdc8269b0de68733e5fcb3f12b4a5640770e
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): flush the mailbox response buffer in SiPSVC V3

In SiPSVC V3, the user suppiled buffer will be directly used
for collecting the response from SDM mailbox - this way we
can avoid keeping t

fix(intel): flush the mailbox response buffer in SiPSVC V3

In SiPSVC V3, the user suppiled buffer will be directly used
for collecting the response from SDM mailbox - this way we
can avoid keeping the response local copy in the TF-A and
improve performance. Once the response is collected in the
user buffer, we need to FLUSH to maintain coherency.

Change-Id: I265ce177fe42d7ab647c875d52286de4b998672d
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update the RSU version logic read

Update the RSU version logic read, keep the version
with backward compatible as SiPSVC V1.

Change-Id: Ibb0f3bb631c7759e65ac028a9e52006f2f057e6f
Signed-

fix(intel): update the RSU version logic read

Update the RSU version logic read, keep the version
with backward compatible as SiPSVC V1.

Change-Id: Ibb0f3bb631c7759e65ac028a9e52006f2f057e6f
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
ref

Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
refactor(versal-net): use the generic GIC driver

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feat(mt8189): add support for PTP3

Use common PTP3 driver to protect CPU from excessive voltage drop in CPU
heavy loading.

Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Chan

feat(mt8189): add support for PTP3

Use common PTP3 driver to protect CPU from excessive voltage drop in CPU
heavy loading.

Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: Iab4a77a6d1816a520f3fe112ef94efdc5789f6c8

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refactor(mediatek): move ptp3_plat.h to common code

To improve code reusability, move the common code from
mt8188/ptp3_plat.h and mt8195/ptp3_plat.h into ptp3_common.h. Place the
platform-specific c

refactor(mediatek): move ptp3_plat.h to common code

To improve code reusability, move the common code from
mt8188/ptp3_plat.h and mt8195/ptp3_plat.h into ptp3_common.h. Place the
platform-specific code in ptp3_plat_v1.h for mt8195 and ptp3_plat_v2.h
for mt8188.

Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: I38c32fa3ad03f9dc7a653ed89da335d26f70f75b

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fix(intel): update generic mailbox command filter method

Update generic mailbox command filter method, filter the
commands based on the mailbox spec command ID and not on
the SMC function ID.

Chang

fix(intel): update generic mailbox command filter method

Update generic mailbox command filter method, filter the
commands based on the mailbox spec command ID and not on
the SMC function ID.

Change-Id: Icceecc4c41858254d1a44e83552561f0b7c313ac
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): solve agilex warm reset issue" into integration

Merge "fix(intel): support DDR In-line and Out-of-Band ECC handling" into integration

Merge "feat(intel): move common functions to common lib files" into integration

Merge "fix(intel): add 5us delay before Linux reconfig to avoid HNOC hang" into integration