| 2512d048 | 02-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(plat/imx8m): add SiP call for secondary boot" into integration |
| 5a91c439 | 14-May-2021 |
Pali Rohár <pali@kernel.org> |
fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal cl
fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).
The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.
Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
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| 203d48ad | 01-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART macros" into integration |
| 94869f0f | 01-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "refactor(plat/marvell/uart): remove unused macros" into integration |
| 73a3db71 | 01-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(morello): initialise CNTFRQ in Non Secure CNTBaseN" into integration |
| 31336258 | 14-May-2021 |
Pali Rohár <pali@kernel.org> |
refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART macros
Macros PLAT_MARVELL_BOOT_UART* and PLAT_MARVELL_CRASH_UART* are defined
to same values. De-duplicate them into PLAT_MARVELL_UART* m
refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART macros
Macros PLAT_MARVELL_BOOT_UART* and PLAT_MARVELL_CRASH_UART* are defined
to same values. De-duplicate them into PLAT_MARVELL_UART* macros.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iae5daf7cad6a971e6f3dbe561df3d0174106ca7f
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| 6b557f48 | 14-May-2021 |
Pali Rohár <pali@kernel.org> |
refactor(plat/marvell/uart): remove unused macros
Macros PLAT_MARVELL_BL31_RUN_UART* are not used since commit
d7c4420cb8a7 ("plat/marvell: Migrate to multi-console API").
Remove them.
Signed-off-
refactor(plat/marvell/uart): remove unused macros
Macros PLAT_MARVELL_BL31_RUN_UART* are not used since commit
d7c4420cb8a7 ("plat/marvell: Migrate to multi-console API").
Remove them.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5ec959ef4de87dcfb332c017ad2599bf8af6ffc3
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| 4fe55a2f | 01-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation" into integration |
| fb88c71d | 01-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(plat/mdeiatek/mt8195): add display port control in SiP service" into integration |
| e4622d3c | 01-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(plat/zynqmp): add support for XCK26 silicon" into integration |
| 7f2d23d9 | 20-May-2021 |
Manoj Kumar <manoj.kumar3@arm.com> |
fix(morello): initialise CNTFRQ in Non Secure CNTBaseN
Morello exhibits the behavior similar to Juno wherein CNTBaseN.CNTFRQ
can be written but does not reflect the value of the CNTFRQ register
in C
fix(morello): initialise CNTFRQ in Non Secure CNTBaseN
Morello exhibits the behavior similar to Juno wherein CNTBaseN.CNTFRQ
can be written but does not reflect the value of the CNTFRQ register
in CNTCTLBase frame. This doesn't follow ARM ARM in that the value
updated in CNTCTLBase.CNTFRQ is not reflected in CNTBaseN.CNTFRQ.
Hence enable the workaround (applied to Juno) for Morello that updates
the CNTFRQ register in the Non Secure CNTBaseN frame.
Change-Id: Iabe53bf3c25152052107e08321323e4bde5fbef4
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
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| 6c4973b0 | 28-Apr-2021 |
Jiaxin Yu <jiaxin.yu@mediatek.com> |
feat(plat/mediatek/mpu): add MPU support for DSP
Forbidden domain D4(DSP) access 0x40000000~0x1FFFF0000.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Change-Id: If409df10cecbcccc493d7958ab2765
feat(plat/mediatek/mpu): add MPU support for DSP
Forbidden domain D4(DSP) access 0x40000000~0x1FFFF0000.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Change-Id: If409df10cecbcccc493d7958ab2765fd110d9009
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| b35f8f2d | 31-May-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(tc0): add support for trusted services" into integration |
| 7a30e08b | 22-Apr-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(plat/zynqmp): add support for XCK26 silicon
Add support for XCK26 silicon which is available on SOM board.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav
feat(plat/zynqmp): add support for XCK26 silicon
Add support for XCK26 silicon which is available on SOM board.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ic98213328702903af8a79f487a2868f3e6d60338
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| 2ea8d419 | 28-May-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs" into integration |
| c6ac4df6 | 18-May-2021 |
johpow01 <john.powell@arm.com> |
fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs
This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.
Signed-off-by: John
fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs
This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I056d3114210db71c2840a24562b51caf2546e195
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| 66a77528 | 13-May-2021 |
Pali Rohár <pali@kernel.org> |
fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation
UART parent clock is by default the platform's xtal clock, which is
25 MHz.
The value defined in the driver, though,
fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation
UART parent clock is by default the platform's xtal clock, which is
25 MHz.
The value defined in the driver, though, is 25.8048 MHz. This is a hack
for the suboptimal divisor calculation
Divisor = UART clock / (16 * baudrate)
which does not use rounding division, resulting in a suboptimal value
for divisor if the correct parent clock rate was used.
Change the code for divisor calculation to
Divisor = Round(UART clock / (16 * baudrate))
and change the parent clock rate value to 25 MHz.
The final UART divisor for default baudrate 115200 is not affected by
this change.
(Note that the parent clock rate should not be defined via a macro,
since the xtal clock can also be 40 MHz. This is outside of the scope of
this fix, though.)
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
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| 0f7d2e89 | 27-May-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(plat/mediatek/pmic_wrap): update idle flow" into integration |
| 99d37c8c | 22-Mar-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(plat/imx): do not keep mmc_device_info in stack
Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform wh
fix(plat/imx): do not keep mmc_device_info in stack
Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].
[1] 13f3c5166f1 ("mmc:prevent accessing to the released space in case of wrong usage")
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iba0424a5787f9e510a60696d4033db1b49b243b2
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| 46b90333 | 20-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(plat/nvidia): use SOC_ID defines
Use the macros that are now defined in include/lib/smccc.h.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ibe3c17acd2482b7779318c8a922a
refactor(plat/nvidia): use SOC_ID defines
Use the macros that are now defined in include/lib/smccc.h.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ibe3c17acd2482b7779318c8a922a138dcace5554
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| 48648c09 | 20-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(plat/mediatek): use SOC_ID defines
Use the macros that are now defined in include/lib/smccc.h.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ie1dbc54569086f6a74206b873f
refactor(plat/mediatek): use SOC_ID defines
Use the macros that are now defined in include/lib/smccc.h.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ie1dbc54569086f6a74206b873fee664b4cdeea36
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| dfff4686 | 20-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(plat/arm): use SOC_ID defines
Use the macros that are now defined in include/lib/smccc.h.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I688a76277b729672835d51fafb68d1d
refactor(plat/arm): use SOC_ID defines
Use the macros that are now defined in include/lib/smccc.h.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I688a76277b729672835d51fafb68d1d6205b6ae4
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| 3d201787 | 08-Mar-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(plat/st): implement platform functions for SMCCC_ARCH_SOC_ID
The JEDEC information for STMicroelectronics is:
JEDEC_ST_MFID U(0x20)
JEDEC_ST_BKID U(0x0)
And rely on platform functions to get ch
feat(plat/st): implement platform functions for SMCCC_ARCH_SOC_ID
The JEDEC information for STMicroelectronics is:
JEDEC_ST_MFID U(0x20)
JEDEC_ST_BKID U(0x0)
And rely on platform functions to get chip IP and revision.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4fa4ac8bb5583b1871b768decc9fe08e8966ff54
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| 92661e01 | 10-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(plat/st): export functions to get SoC information
Three functions are exported to get SoC version, SoC device ID, and SoC
name. Those functions are based on reworked existing static functio
refactor(plat/st): export functions to get SoC information
Three functions are exported to get SoC version, SoC device ID, and SoC
name. Those functions are based on reworked existing static functions.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I1f3949062bb488286a9e7a38ffcd1457953dac56
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| 7bd64c70 | 20-Apr-2021 |
Pranav Madhu <pranav.madhu@arm.com> |
feat(plat/sgi): enable use of PSCI extended state ID format
The SGI/RD platforms have been using PSCI state ID format as defined in
PSCI version prior to 1.0. This is being changed and the PSCI exte
feat(plat/sgi): enable use of PSCI extended state ID format
The SGI/RD platforms have been using PSCI state ID format as defined in
PSCI version prior to 1.0. This is being changed and the PSCI extended
state ID format as defined in PSCI version 1.1 is being adapted. In
addition to this, the use of Arm recommended PSCI state ID encoding is
enabled as well.
Change-Id: I2be8a9820987a96b23f4281563b6fa22db48fa5f
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
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