1 /* 2 * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP_COMMON_H 8 #define STM32MP_COMMON_H 9 10 #include <stdbool.h> 11 12 #include <platform_def.h> 13 14 /* Functions to save and get boot context address given by ROM code */ 15 void stm32mp_save_boot_ctx_address(uintptr_t address); 16 uintptr_t stm32mp_get_boot_ctx_address(void); 17 18 bool stm32mp_is_single_core(void); 19 bool stm32mp_is_closed_device(void); 20 21 /* Return the base address of the DDR controller */ 22 uintptr_t stm32mp_ddrctrl_base(void); 23 24 /* Return the base address of the DDR PHY */ 25 uintptr_t stm32mp_ddrphyc_base(void); 26 27 /* Return the base address of the PWR peripheral */ 28 uintptr_t stm32mp_pwr_base(void); 29 30 /* Return the base address of the RCC peripheral */ 31 uintptr_t stm32mp_rcc_base(void); 32 33 /* Check MMU status to allow spinlock use */ 34 bool stm32mp_lock_available(void); 35 36 /* Get IWDG platform instance ID from peripheral IO memory base address */ 37 uint32_t stm32_iwdg_get_instance(uintptr_t base); 38 39 /* Return bitflag mask for expected IWDG configuration from OTP content */ 40 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst); 41 42 #if defined(IMAGE_BL2) 43 /* Update OTP shadow registers with IWDG configuration from device tree */ 44 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags); 45 #endif 46 47 /* 48 * Platform util functions for the GPIO driver 49 * @bank: Target GPIO bank ID as per DT bindings 50 * 51 * Platform shall implement these functions to provide to stm32_gpio 52 * driver the resource reference for a target GPIO bank. That are 53 * memory mapped interface base address, interface offset (see below) 54 * and clock identifier. 55 * 56 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 57 * check DT configuration matches platform implementation of the banks 58 * description. 59 */ 60 uintptr_t stm32_get_gpio_bank_base(unsigned int bank); 61 unsigned long stm32_get_gpio_bank_clock(unsigned int bank); 62 uint32_t stm32_get_gpio_bank_offset(unsigned int bank); 63 64 /* Return node offset for target GPIO bank ID @bank or a FDT error code */ 65 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank); 66 67 /* Get the chip revision */ 68 uint32_t stm32mp_get_chip_version(void); 69 /* Get the chip device ID */ 70 uint32_t stm32mp_get_chip_dev_id(void); 71 72 /* Get SOC name */ 73 #define STM32_SOC_NAME_SIZE 20 74 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]); 75 76 /* Print CPU information */ 77 void stm32mp_print_cpuinfo(void); 78 79 /* Print board information */ 80 void stm32mp_print_boardinfo(void); 81 82 /* 83 * Util for clock gating and to get clock rate for stm32 and platform drivers 84 * @id: Target clock ID, ID used in clock DT bindings 85 */ 86 bool stm32mp_clk_is_enabled(unsigned long id); 87 void stm32mp_clk_enable(unsigned long id); 88 void stm32mp_clk_disable(unsigned long id); 89 unsigned long stm32mp_clk_get_rate(unsigned long id); 90 91 /* Initialise the IO layer and register platform IO devices */ 92 void stm32mp_io_setup(void); 93 94 /* 95 * Check that the STM32 header of a .stm32 binary image is valid 96 * @param header: pointer to the stm32 image header 97 * @param buffer: address of the binary image (payload) 98 * @return: 0 on success, negative value in case of error 99 */ 100 int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer); 101 102 /* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */ 103 int stm32mp_map_ddr_non_cacheable(void); 104 int stm32mp_unmap_ddr(void); 105 106 #endif /* STM32MP_COMMON_H */ 107