fix(plat/marvell/a8k): Add missing build dependency for BLE target

BLE source files depend on external Marvell mv-ddr-marvell tree
(specified in $(MV_DDR_PATH) variable) and its header files. Add
de

fix(plat/marvell/a8k): Add missing build dependency for BLE target

BLE source files depend on external Marvell mv-ddr-marvell tree
(specified in $(MV_DDR_PATH) variable) and its header files. Add
dependency on $(MV_DDR_LIB) target which checks that variable
$(MV_DDR_PATH) is correctly set and ensures that make completes
compilation of mv-ddr-marvell tree.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I73968b24c45d9af1e3500b8db7a24bb4eb2bfa47

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fix(plat/marvell/a8k): Correctly set include directories for individual targets

Do not set all include directories, including those for external targets
in one PLAT_INCLUDES variable.

Instead split

fix(plat/marvell/a8k): Correctly set include directories for individual targets

Do not set all include directories, including those for external targets
in one PLAT_INCLUDES variable.

Instead split them into variables:
* $(PLAT_INCLUDES) for all TF-A BL images
* BLE target specific $(PLAT_INCLUDES) only for Marvell BLE image
* $(MV_DDR_INCLUDES) for targets in external Marvell mv-ddr-marvell tree

Include directory $(CURDIR)/drivers/marvell is required by TF-A BL
images, so move it from ble.mk to a8k_common.mk.

Include directory $(MV_DDR_PATH) is needed only by Marvell BLE image, so
move it into BLE target specific $(PLAT_INCLUDES) variable.

And remaining include directories specified in ble.mk are needed only
for building external dependences from Marvell mv-ddr tree, so move them
into $(MV_DDR_INCLUDES) variable and correctly use it in $(MV_DDR_LIB)
target.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I331f7de675dca2bc70733d56b768f00d56ae4a67

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fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set

Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded a

fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set

Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded at some
specific location and require user to specify correct path to mv_ddr
source code via MV_DDR_PATH build option.

TF-A code for Armada 37x0 platform also depends on mv_ddr source code
and already requires passing correct MV_DDR_PATH build option.

So for A8K implement same checks for validity of MV_DDR_PATH option as
are already used by TF-A code for Armada 37x0 platform.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a

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feat(plat/rcar3): add a DRAM size setting for M3N

This commit adds a DRAM size setting when building with
RCAR_DRAM_LPDDR4_MEMCONF=2 for M3N Ver.1.1 4GB DRAM.

Signed-off-by: Toshiyuki Ogasahara <to

feat(plat/rcar3): add a DRAM size setting for M3N

This commit adds a DRAM size setting when building with
RCAR_DRAM_LPDDR4_MEMCONF=2 for M3N Ver.1.1 4GB DRAM.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ib7fea862ab2e0bcafaf39ec030384f0fddda9b96

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feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0

Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-

feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0

Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I44b9e5a992e8a44cfeafad6d2c1a97aa59baca4e

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feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB

Add new board revision for 8GB 1rank of Salvator-XS/H3ULCB

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Si

feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB

Add new board revision for 8GB 1rank of Salvator-XS/H3ULCB

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I9e0ef7340d92de9c892fc5bd04abe24ad6ee4286

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fix(drivers/rcar3): fix CPG registers redefinition

This commit deletes the value of the redefined CPG register.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by

fix(drivers/rcar3): fix CPG registers redefinition

This commit deletes the value of the redefined CPG register.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de

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fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0

The DRAM channel 0 memory area in 32bit space is limited to 2 GiB window.
Furthermore, the first 128 MiB of this memory win

fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0

The DRAM channel 0 memory area in 32bit space is limited to 2 GiB window.
Furthermore, the first 128 MiB of this memory window are reserved and not
accessible by the system software, hence the 32bit area memory node is
limited to range 0x4800_0000..0xbfff_ffff.

In case there are more than 2 GiB of DRAM populated in channel 0, it is
necessary to generate two memory nodes, once covering the 2 GiB - 128 MiB
area in the 32bit space, and another covering the rest of the memory in
64bit space. This patch implements handling of such a case.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I3495241fb938e355352e817afaca8f01d04c81d2

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refactor(plat/rcar3): factor out DT memory node generation

Move the code that adds single new memory@ node into the DT fragment passed
to system software into separate function. Adjust the failure m

refactor(plat/rcar3): factor out DT memory node generation

Move the code that adds single new memory@ node into the DT fragment passed
to system software into separate function. Adjust the failure message to be
more specific and print the address range of node which failed to be added.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie42cd7756b045271f070bca93c524fff6238f5a2

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feat(plat/rcar3): add optional support for gzip-compressed BL33

The BL33 size on this platform is limited to 1 MiB, add optional
support for decompressing and starting gzip-compressed BL33, which
ma

feat(plat/rcar3): add optional support for gzip-compressed BL33

The BL33 size on this platform is limited to 1 MiB, add optional
support for decompressing and starting gzip-compressed BL33, which
may help with this size limitation. This functionality is disabled
by default, set RCAR_GEN3_BL33_GZIP=1 during build to enable it.

The BL33 at 0x50000000 should then be gzip compressed, however if
the BL33 does not have a valid gzip header, it is copied to the
correct location and started as-is, this is a fallback for legacy
systems and systems which update to gzip-compressed BL33.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id93f1c7e6f17db1ffb952ea086562993473f6efa

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fix(plat/xilinx/versal): use sync method for blocking calls

All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are

fix(plat/xilinx/versal): use sync method for blocking calls

All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are not reading
status from IPI payload data. Use sync method which
reads actual return status from IPI payload.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I6f568b85d0da639c264f507122e3015807d8423d

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fix(plat/xilinx/zynqmp): use sync method for blocking calls

All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are

fix(plat/xilinx/zynqmp): use sync method for blocking calls

All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are not reading
status from IPI payload data. Use sync method which
reads actual return status from IPI payload.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I78f9c061a80cee6d524ade4ef124ca88ce1848cf

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Merge "feat(plat/zynqmp): extend DT description by TF-A" into integration

Merge changes from topic "stm32_io_update" into integration

* changes:
refactor(plat/st): add stm32image_io_setup
fix(plat/st): panic if boot interface is wrong

refactor(plat/arm): use mmio* functions to read/write NVFLAGS registers

Used mmio* functions to read/write NVFLAGS registers to avoid
possibile reordering of instructions by compiler.

Change-Id: Ia

refactor(plat/arm): use mmio* functions to read/write NVFLAGS registers

Used mmio* functions to read/write NVFLAGS registers to avoid
possibile reordering of instructions by compiler.

Change-Id: Iae50ac30e5413259cf8554f0fff47512ad83b0fd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(plat/arm): mark the flash region as read-only

In the FVP platform, BL1 uses flash only for read purpose
hence marked this flash region as read-only.

Change-Id: I3b57130fd4f3b4df522ac075f66

refactor(plat/arm): mark the flash region as read-only

In the FVP platform, BL1 uses flash only for read purpose
hence marked this flash region as read-only.

Change-Id: I3b57130fd4f3b4df522ac075f66e9799f237ebb7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(plat/arm): update NV flags on image load/authentication failure

Erasing the FIP TOC header present in a flash is replaced by updating NV
flags with an error code on image load/authenticatio

refactor(plat/arm): update NV flags on image load/authentication failure

Erasing the FIP TOC header present in a flash is replaced by updating NV
flags with an error code on image load/authentication failure.
BL1 component uses these NV flags to detect whether a firmware update is
needed or not.
These NV flags get cleared once the firmware update gets completed.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6232a0db07c89b2373b7b9d28acd37df6203d914

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feat(plat/mediatek/mt8195): add DCM driver

DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.

1. Add MCUSYS related DCM drivers.
2. Enable M

feat(plat/mediatek/mt8195): add DCM driver

DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.

1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.

Change-Id: I3237199bc217bd3682f51d31284db5fd0324b396
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>

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Merge changes from topic "st_fixes" into integration

* changes:
fix(tools/stm32image): improve the tool
fix(plat/st): add STM32IMAGE_SRC

refactor(plat/qemu): increase the non-secure DRAM size

In the qemu memory map 1GB and up is RAM. Change the
size of NS DRAM to 3GB to support VM's with more
memory requirements.

Signed-off-by: Ruch

refactor(plat/qemu): increase the non-secure DRAM size

In the qemu memory map 1GB and up is RAM. Change the
size of NS DRAM to 3GB to support VM's with more
memory requirements.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Change-Id: If15cf3b9d3e2e7876c40ce888f22e887893fe696

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Merge changes from topic "sb/measured-boot" into integration

* changes:
refactor(plat/fvp): tidy up list of images to measure
docs: explain Measured Boot dependency on Trusted Boot

Merge changes Ib8502f9b,I388fd231,I7bd37912,I3a186ed7 into integration

* changes:
feat(plat/mediatek/mt8195): add SPM suspend driver
feat(plat/mediatek/mt8195): support MCUSYS off when system su

Merge changes Ib8502f9b,I388fd231,I7bd37912,I3a186ed7 into integration

* changes:
feat(plat/mediatek/mt8195): add SPM suspend driver
feat(plat/mediatek/mt8195): support MCUSYS off when system suspend
feat(plat/mediatek/mt8195): add support for PTP3
fix(plat/mediatek/mt8195): extend MMU region size

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Merge "feat(spm): add Ivy partition to tb fw config" into integration

feat(plat/mediatek/mt8195): add SPM suspend driver

Support DRAM/MAINPLL/26M off when system suspend.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Ib850

feat(plat/mediatek/mt8195): add SPM suspend driver

Support DRAM/MAINPLL/26M off when system suspend.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Ib8502f9b0b4e47aa405e5449f0b6d483bd3f5d77

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feat(plat/mediatek/mt8195): support MCUSYS off when system suspend

Add drivers to support MCUSYS off when system suspend.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.

feat(plat/mediatek/mt8195): support MCUSYS off when system suspend

Add drivers to support MCUSYS off when system suspend.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: I388fd2318f471083158992464ecdf2181fc7d87a

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