1 /* 2 * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/desc_image_load.h> 18 #include <common/image_decompress.h> 19 #include <drivers/console.h> 20 #include <drivers/io/io_driver.h> 21 #include <drivers/io/io_storage.h> 22 #include <lib/mmio.h> 23 #include <lib/xlat_tables/xlat_tables_defs.h> 24 #include <plat/common/platform.h> 25 #if RCAR_GEN3_BL33_GZIP == 1 26 #include <tf_gunzip.h> 27 #endif 28 29 #include "avs_driver.h" 30 #include "boot_init_dram.h" 31 #include "cpg_registers.h" 32 #include "board.h" 33 #include "emmc_def.h" 34 #include "emmc_hal.h" 35 #include "emmc_std.h" 36 37 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 38 #include "iic_dvfs.h" 39 #endif 40 41 #include "io_common.h" 42 #include "io_rcar.h" 43 #include "qos_init.h" 44 #include "rcar_def.h" 45 #include "rcar_private.h" 46 #include "rcar_version.h" 47 #include "rom_api.h" 48 49 #if RCAR_BL2_DCACHE == 1 50 /* 51 * Following symbols are only used during plat_arch_setup() only 52 * when RCAR_BL2_DCACHE is enabled. 53 */ 54 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 55 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 56 57 #if USE_COHERENT_MEM 58 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 59 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 60 #endif 61 62 #endif 63 64 extern void plat_rcar_gic_driver_init(void); 65 extern void plat_rcar_gic_init(void); 66 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 67 extern void bl2_system_cpg_init(void); 68 extern void bl2_secure_setting(void); 69 extern void bl2_cpg_init(void); 70 extern void rcar_io_emmc_setup(void); 71 extern void rcar_io_setup(void); 72 extern void rcar_swdt_release(void); 73 extern void rcar_swdt_init(void); 74 extern void rcar_rpc_init(void); 75 extern void rcar_pfc_init(void); 76 extern void rcar_dma_init(void); 77 78 static void bl2_init_generic_timer(void); 79 80 /* R-Car Gen3 product check */ 81 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 82 #define TARGET_PRODUCT PRR_PRODUCT_H3 83 #define TARGET_NAME "R-Car H3" 84 #elif RCAR_LSI == RCAR_M3 85 #define TARGET_PRODUCT PRR_PRODUCT_M3 86 #define TARGET_NAME "R-Car M3" 87 #elif RCAR_LSI == RCAR_M3N 88 #define TARGET_PRODUCT PRR_PRODUCT_M3N 89 #define TARGET_NAME "R-Car M3N" 90 #elif RCAR_LSI == RCAR_V3M 91 #define TARGET_PRODUCT PRR_PRODUCT_V3M 92 #define TARGET_NAME "R-Car V3M" 93 #elif RCAR_LSI == RCAR_E3 94 #define TARGET_PRODUCT PRR_PRODUCT_E3 95 #define TARGET_NAME "R-Car E3" 96 #elif RCAR_LSI == RCAR_D3 97 #define TARGET_PRODUCT PRR_PRODUCT_D3 98 #define TARGET_NAME "R-Car D3" 99 #elif RCAR_LSI == RCAR_AUTO 100 #define TARGET_NAME "R-Car H3/M3/M3N/V3M" 101 #endif 102 103 #if (RCAR_LSI == RCAR_E3) 104 #define GPIO_INDT (GPIO_INDT6) 105 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 106 #else 107 #define GPIO_INDT (GPIO_INDT1) 108 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 109 #endif 110 111 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 112 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 113 assert_bl31_params_do_not_fit_in_shared_memory); 114 115 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 116 117 /* FDT with DRAM configuration */ 118 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 119 static void *fdt = (void *)fdt_blob; 120 121 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 122 char *string) 123 { 124 /* Just need enough space to store 64 bit decimal integer */ 125 char num_buf[20]; 126 int i = 0; 127 unsigned int rem; 128 129 do { 130 rem = unum % radix; 131 if (rem < 0xa) 132 num_buf[i] = '0' + rem; 133 else 134 num_buf[i] = 'a' + (rem - 0xa); 135 i++; 136 unum /= radix; 137 } while (unum > 0U); 138 139 while (--i >= 0) 140 *string++ = num_buf[i]; 141 *string = 0; 142 } 143 144 #if (RCAR_LOSSY_ENABLE == 1) 145 typedef struct bl2_lossy_info { 146 uint32_t magic; 147 uint32_t a0; 148 uint32_t b0; 149 } bl2_lossy_info_t; 150 151 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 152 uint64_t end_addr, uint32_t format, 153 uint32_t enable, int fcnlnode) 154 { 155 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 156 char nodename[40] = { 0 }; 157 int ret, node; 158 159 /* Ignore undefined addresses */ 160 if (start_addr == 0 && end_addr == 0) 161 return; 162 163 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 164 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 165 166 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 167 if (ret < 0) { 168 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 169 panic(); 170 } 171 172 ret = fdt_setprop_string(fdt, node, "compatible", 173 "renesas,lossy-decompression"); 174 if (ret < 0) { 175 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 176 panic(); 177 } 178 179 ret = fdt_appendprop_string(fdt, node, "compatible", 180 "shared-dma-pool"); 181 if (ret < 0) { 182 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 183 panic(); 184 } 185 186 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 187 if (ret < 0) { 188 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 189 panic(); 190 } 191 192 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 193 if (ret < 0) { 194 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 195 panic(); 196 } 197 198 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 199 if (ret < 0) { 200 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 201 panic(); 202 } 203 204 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 205 if (ret < 0) { 206 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 207 panic(); 208 } 209 } 210 211 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 212 uint64_t end_addr, uint32_t format, 213 uint32_t enable, int fcnlnode) 214 { 215 bl2_lossy_info_t info; 216 uint32_t reg; 217 218 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 219 220 reg = format | (start_addr >> 20); 221 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 222 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 223 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 224 225 info.magic = 0x12345678U; 226 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 227 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 228 229 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 230 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 231 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 232 233 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 234 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 235 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 236 } 237 #endif 238 239 void bl2_plat_flush_bl31_params(void) 240 { 241 uint32_t product_cut, product, cut; 242 uint32_t boot_dev, boot_cpu; 243 uint32_t lcs, reg, val; 244 245 reg = mmio_read_32(RCAR_MODEMR); 246 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 247 248 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 249 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 250 emmc_terminate(); 251 252 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 253 bl2_secure_setting(); 254 255 reg = mmio_read_32(RCAR_PRR); 256 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 257 product = reg & PRR_PRODUCT_MASK; 258 cut = reg & PRR_CUT_MASK; 259 260 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut) 261 goto tlb; 262 263 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut) 264 goto tlb; 265 266 if (product == PRR_PRODUCT_D3) 267 goto tlb; 268 269 /* Disable MFIS write protection */ 270 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 271 272 tlb: 273 reg = mmio_read_32(RCAR_MODEMR); 274 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 275 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 276 boot_cpu != MODEMR_BOOT_CPU_CA53) 277 goto mmu; 278 279 if (product_cut == PRR_PRODUCT_H3_CUT20) { 280 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 281 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 282 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 283 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 284 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 285 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 286 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 287 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 288 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 289 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 290 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 291 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 292 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 293 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 294 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 295 } 296 297 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 298 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 299 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 300 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 301 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 302 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 303 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 304 305 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 306 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 307 } 308 309 mmu: 310 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 311 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 312 313 val = rcar_rom_get_lcs(&lcs); 314 if (val) { 315 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 316 panic(); 317 } 318 319 if (lcs == LCS_SE) 320 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 321 322 rcar_swdt_release(); 323 bl2_system_cpg_init(); 324 325 #if RCAR_BL2_DCACHE == 1 326 /* Disable data cache (clean and invalidate) */ 327 disable_mmu_el3(); 328 #endif 329 } 330 331 static uint32_t is_ddr_backup_mode(void) 332 { 333 #if RCAR_SYSTEM_SUSPEND 334 static uint32_t reason = RCAR_COLD_BOOT; 335 static uint32_t once; 336 337 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 338 uint8_t data; 339 #endif 340 if (once) 341 return reason; 342 343 once = 1; 344 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 345 return reason; 346 347 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 348 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 349 ERROR("BL2: REG Keep10 READ ERROR.\n"); 350 panic(); 351 } 352 353 if (KEEP10_MAGIC != data) 354 reason = RCAR_WARM_BOOT; 355 #else 356 reason = RCAR_WARM_BOOT; 357 #endif 358 return reason; 359 #else 360 return RCAR_COLD_BOOT; 361 #endif 362 } 363 364 #if RCAR_GEN3_BL33_GZIP == 1 365 void bl2_plat_preload_setup(void) 366 { 367 image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip); 368 } 369 #endif 370 371 int bl2_plat_handle_pre_image_load(unsigned int image_id) 372 { 373 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 374 bl_mem_params_node_t *bl_mem_params; 375 376 bl_mem_params = get_bl_mem_params_node(image_id); 377 378 #if RCAR_GEN3_BL33_GZIP == 1 379 if (image_id == BL33_IMAGE_ID) { 380 image_decompress_prepare(&bl_mem_params->image_info); 381 } 382 #endif 383 384 if (image_id != BL31_IMAGE_ID) 385 return 0; 386 387 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 388 goto cold_boot; 389 390 *boot_kind = RCAR_WARM_BOOT; 391 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 392 393 console_flush(); 394 bl2_plat_flush_bl31_params(); 395 396 /* will not return */ 397 bl2_enter_bl31(&bl_mem_params->ep_info); 398 399 cold_boot: 400 *boot_kind = RCAR_COLD_BOOT; 401 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 402 403 return 0; 404 } 405 406 static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest) 407 { 408 uint32_t cert, len; 409 int ret; 410 411 ret = rcar_get_certificate(certid, &cert); 412 if (ret) { 413 ERROR("%s : cert file load error", __func__); 414 return 1; 415 } 416 417 rcar_read_certificate((uint64_t) cert, &len, dest); 418 419 return 0; 420 } 421 422 int bl2_plat_handle_post_image_load(unsigned int image_id) 423 { 424 static bl2_to_bl31_params_mem_t *params; 425 bl_mem_params_node_t *bl_mem_params; 426 uintptr_t dest; 427 int ret; 428 429 if (!params) { 430 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 431 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 432 } 433 434 bl_mem_params = get_bl_mem_params_node(image_id); 435 436 switch (image_id) { 437 case BL31_IMAGE_ID: 438 ret = rcar_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID, 439 &dest); 440 if (!ret) 441 bl_mem_params->image_info.image_base = dest; 442 break; 443 case BL32_IMAGE_ID: 444 ret = rcar_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID, 445 &dest); 446 if (!ret) 447 bl_mem_params->image_info.image_base = dest; 448 449 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 450 sizeof(entry_point_info_t)); 451 break; 452 case BL33_IMAGE_ID: 453 #if RCAR_GEN3_BL33_GZIP == 1 454 if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) { 455 /* decompress gzip-compressed image */ 456 ret = image_decompress(&bl_mem_params->image_info); 457 if (ret != 0) { 458 return ret; 459 } 460 } else { 461 /* plain image, copy it in place */ 462 memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE, 463 bl_mem_params->image_info.image_size); 464 } 465 #endif 466 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 467 sizeof(entry_point_info_t)); 468 break; 469 } 470 471 return 0; 472 } 473 474 struct meminfo *bl2_plat_sec_mem_layout(void) 475 { 476 return &bl2_tzram_layout; 477 } 478 479 static void bl2_populate_compatible_string(void *dt) 480 { 481 uint32_t board_type; 482 uint32_t board_rev; 483 uint32_t reg; 484 int ret; 485 486 fdt_setprop_u32(dt, 0, "#address-cells", 2); 487 fdt_setprop_u32(dt, 0, "#size-cells", 2); 488 489 /* Populate compatible string */ 490 rcar_get_board_type(&board_type, &board_rev); 491 switch (board_type) { 492 case BOARD_SALVATOR_X: 493 ret = fdt_setprop_string(dt, 0, "compatible", 494 "renesas,salvator-x"); 495 break; 496 case BOARD_SALVATOR_XS: 497 ret = fdt_setprop_string(dt, 0, "compatible", 498 "renesas,salvator-xs"); 499 break; 500 case BOARD_STARTER_KIT: 501 ret = fdt_setprop_string(dt, 0, "compatible", 502 "renesas,m3ulcb"); 503 break; 504 case BOARD_STARTER_KIT_PRE: 505 ret = fdt_setprop_string(dt, 0, "compatible", 506 "renesas,h3ulcb"); 507 break; 508 case BOARD_EAGLE: 509 ret = fdt_setprop_string(dt, 0, "compatible", 510 "renesas,eagle"); 511 break; 512 case BOARD_EBISU: 513 case BOARD_EBISU_4D: 514 ret = fdt_setprop_string(dt, 0, "compatible", 515 "renesas,ebisu"); 516 break; 517 case BOARD_DRAAK: 518 ret = fdt_setprop_string(dt, 0, "compatible", 519 "renesas,draak"); 520 break; 521 default: 522 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 523 panic(); 524 } 525 526 if (ret < 0) { 527 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 528 panic(); 529 } 530 531 reg = mmio_read_32(RCAR_PRR); 532 switch (reg & PRR_PRODUCT_MASK) { 533 case PRR_PRODUCT_H3: 534 ret = fdt_appendprop_string(dt, 0, "compatible", 535 "renesas,r8a7795"); 536 break; 537 case PRR_PRODUCT_M3: 538 ret = fdt_appendprop_string(dt, 0, "compatible", 539 "renesas,r8a7796"); 540 break; 541 case PRR_PRODUCT_M3N: 542 ret = fdt_appendprop_string(dt, 0, "compatible", 543 "renesas,r8a77965"); 544 break; 545 case PRR_PRODUCT_V3M: 546 ret = fdt_appendprop_string(dt, 0, "compatible", 547 "renesas,r8a77970"); 548 break; 549 case PRR_PRODUCT_E3: 550 ret = fdt_appendprop_string(dt, 0, "compatible", 551 "renesas,r8a77990"); 552 break; 553 case PRR_PRODUCT_D3: 554 ret = fdt_appendprop_string(dt, 0, "compatible", 555 "renesas,r8a77995"); 556 break; 557 default: 558 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 559 panic(); 560 } 561 562 if (ret < 0) { 563 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 564 panic(); 565 } 566 } 567 568 static void bl2_add_dram_entry(uint64_t start, uint64_t size) 569 { 570 char nodename[32] = { 0 }; 571 uint64_t fdtsize; 572 int ret, node; 573 574 fdtsize = cpu_to_fdt64(size); 575 576 snprintf(nodename, sizeof(nodename), "memory@"); 577 unsigned_num_print(start, 16, nodename + strlen(nodename)); 578 node = ret = fdt_add_subnode(fdt, 0, nodename); 579 if (ret < 0) { 580 goto err; 581 } 582 583 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 584 if (ret < 0) { 585 goto err; 586 } 587 588 ret = fdt_setprop_u64(fdt, node, "reg", start); 589 if (ret < 0) { 590 goto err; 591 } 592 593 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 594 sizeof(fdtsize)); 595 if (ret < 0) { 596 goto err; 597 } 598 599 return; 600 err: 601 NOTICE("BL2: Cannot add memory node [%llx - %llx] to FDT (ret=%i)\n", 602 start, start + size - 1, ret); 603 panic(); 604 } 605 606 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 607 { 608 uint64_t start, size; 609 int chan; 610 611 for (chan = 0; chan < 4; chan++) { 612 start = dram_config[2 * chan]; 613 size = dram_config[2 * chan + 1]; 614 if (!size) 615 continue; 616 617 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n", 618 chan, start, start + size - 1, 619 (size >> 30) ? : size >> 20, 620 (size >> 30) ? "G" : "M"); 621 } 622 623 /* 624 * We add the DT nodes in reverse order here. The fdt_add_subnode() 625 * adds the DT node before the first existing DT node, so we have 626 * to add them in reverse order to get nodes sorted by address in 627 * the resulting DT. 628 */ 629 for (chan = 3; chan >= 0; chan--) { 630 start = dram_config[2 * chan]; 631 size = dram_config[2 * chan + 1]; 632 if (!size) 633 continue; 634 635 /* 636 * Channel 0 is mapped in 32bit space and the first 637 * 128 MiB are reserved 638 */ 639 if (chan == 0) { 640 start = 0x48000000; 641 size -= 0x8000000; 642 } 643 644 bl2_add_dram_entry(start, size); 645 } 646 } 647 648 static void bl2_advertise_dram_size(uint32_t product) 649 { 650 uint64_t dram_config[8] = { 651 [0] = 0x400000000ULL, 652 [2] = 0x500000000ULL, 653 [4] = 0x600000000ULL, 654 [6] = 0x700000000ULL, 655 }; 656 657 switch (product) { 658 case PRR_PRODUCT_H3: 659 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 660 /* 4GB(1GBx4) */ 661 dram_config[1] = 0x40000000ULL; 662 dram_config[3] = 0x40000000ULL; 663 dram_config[5] = 0x40000000ULL; 664 dram_config[7] = 0x40000000ULL; 665 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 666 (RCAR_DRAM_CHANNEL == 5) && \ 667 (RCAR_DRAM_SPLIT == 2) 668 /* 4GB(2GBx2 2ch split) */ 669 dram_config[1] = 0x80000000ULL; 670 dram_config[3] = 0x80000000ULL; 671 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 672 /* 8GB(2GBx4: default) */ 673 dram_config[1] = 0x80000000ULL; 674 dram_config[3] = 0x80000000ULL; 675 dram_config[5] = 0x80000000ULL; 676 dram_config[7] = 0x80000000ULL; 677 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 678 break; 679 680 case PRR_PRODUCT_M3: 681 #if (RCAR_GEN3_ULCB == 1) 682 /* 2GB(1GBx2 2ch split) */ 683 dram_config[1] = 0x40000000ULL; 684 dram_config[5] = 0x40000000ULL; 685 #else 686 /* 4GB(2GBx2 2ch split) */ 687 dram_config[1] = 0x80000000ULL; 688 dram_config[5] = 0x80000000ULL; 689 #endif 690 break; 691 692 case PRR_PRODUCT_M3N: 693 /* 2GB(1GBx2) */ 694 dram_config[1] = 0x80000000ULL; 695 break; 696 697 case PRR_PRODUCT_V3M: 698 /* 1GB(512MBx2) */ 699 dram_config[1] = 0x40000000ULL; 700 break; 701 702 case PRR_PRODUCT_E3: 703 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 704 /* 1GB(512MBx2) */ 705 dram_config[1] = 0x40000000ULL; 706 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 707 /* 2GB(512MBx4) */ 708 dram_config[1] = 0x80000000ULL; 709 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 710 /* 4GB(1GBx4) */ 711 dram_config[1] = 0x100000000ULL; 712 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 713 break; 714 715 case PRR_PRODUCT_D3: 716 /* 512MB */ 717 dram_config[1] = 0x20000000ULL; 718 break; 719 } 720 721 bl2_advertise_dram_entries(dram_config); 722 } 723 724 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 725 u_register_t arg3, u_register_t arg4) 726 { 727 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 728 uint32_t product, product_cut, major, minor; 729 int32_t ret; 730 const char *str; 731 const char *unknown = "unknown"; 732 const char *cpu_ca57 = "CA57"; 733 const char *cpu_ca53 = "CA53"; 734 const char *product_m3n = "M3N"; 735 const char *product_h3 = "H3"; 736 const char *product_m3 = "M3"; 737 const char *product_e3 = "E3"; 738 const char *product_d3 = "D3"; 739 const char *product_v3m = "V3M"; 740 const char *lcs_secure = "SE"; 741 const char *lcs_cm = "CM"; 742 const char *lcs_dm = "DM"; 743 const char *lcs_sd = "SD"; 744 const char *lcs_fa = "FA"; 745 const char *sscg_off = "PLL1 nonSSCG Clock select"; 746 const char *sscg_on = "PLL1 SSCG Clock select"; 747 const char *boot_hyper80 = "HyperFlash(80MHz)"; 748 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 749 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 750 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 751 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 752 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) 753 const char *boot_hyper160 = "HyperFlash(150MHz)"; 754 #else 755 const char *boot_hyper160 = "HyperFlash(160MHz)"; 756 #endif 757 #if (RCAR_LOSSY_ENABLE == 1) 758 int fcnlnode; 759 #endif 760 761 bl2_init_generic_timer(); 762 763 reg = mmio_read_32(RCAR_MODEMR); 764 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 765 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 766 767 bl2_cpg_init(); 768 769 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 770 boot_cpu == MODEMR_BOOT_CPU_CA53) { 771 rcar_pfc_init(); 772 rcar_console_boot_init(); 773 } 774 775 plat_rcar_gic_driver_init(); 776 plat_rcar_gic_init(); 777 rcar_swdt_init(); 778 779 /* FIQ interrupts are taken to EL3 */ 780 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 781 782 write_daifclr(DAIF_FIQ_BIT); 783 784 reg = read_midr(); 785 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 786 switch (midr) { 787 case MIDR_CA57: 788 str = cpu_ca57; 789 break; 790 case MIDR_CA53: 791 str = cpu_ca53; 792 break; 793 default: 794 str = unknown; 795 break; 796 } 797 798 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 799 version_of_renesas); 800 801 reg = mmio_read_32(RCAR_PRR); 802 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 803 product = reg & PRR_PRODUCT_MASK; 804 805 switch (product) { 806 case PRR_PRODUCT_H3: 807 str = product_h3; 808 break; 809 case PRR_PRODUCT_M3: 810 str = product_m3; 811 break; 812 case PRR_PRODUCT_M3N: 813 str = product_m3n; 814 break; 815 case PRR_PRODUCT_V3M: 816 str = product_v3m; 817 break; 818 case PRR_PRODUCT_E3: 819 str = product_e3; 820 break; 821 case PRR_PRODUCT_D3: 822 str = product_d3; 823 break; 824 default: 825 str = unknown; 826 break; 827 } 828 829 if ((PRR_PRODUCT_M3 == product) && 830 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) { 831 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 832 /* M3 Ver.1.1 or Ver.1.2 */ 833 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", 834 str); 835 } else { 836 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", 837 str, 838 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 839 } 840 } else { 841 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 842 major = major + RCAR_MAJOR_OFFSET; 843 minor = reg & RCAR_MINOR_MASK; 844 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 845 } 846 847 if (product == PRR_PRODUCT_E3) { 848 reg = mmio_read_32(RCAR_MODEMR); 849 sscg = reg & RCAR_SSCG_MASK; 850 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 851 NOTICE("BL2: %s\n", str); 852 } 853 854 rcar_get_board_type(&type, &rev); 855 856 switch (type) { 857 case BOARD_SALVATOR_X: 858 case BOARD_KRIEK: 859 case BOARD_STARTER_KIT: 860 case BOARD_SALVATOR_XS: 861 case BOARD_EBISU: 862 case BOARD_STARTER_KIT_PRE: 863 case BOARD_EBISU_4D: 864 case BOARD_DRAAK: 865 case BOARD_EAGLE: 866 break; 867 default: 868 type = BOARD_UNKNOWN; 869 break; 870 } 871 872 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 873 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 874 else { 875 NOTICE("BL2: Board is %s Rev.%d.%d\n", 876 GET_BOARD_NAME(type), 877 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 878 } 879 880 #if RCAR_LSI != RCAR_AUTO 881 if (product != TARGET_PRODUCT) { 882 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 883 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 884 panic(); 885 } 886 #endif 887 rcar_avs_init(); 888 rcar_avs_setting(); 889 890 switch (boot_dev) { 891 case MODEMR_BOOT_DEV_HYPERFLASH160: 892 str = boot_hyper160; 893 break; 894 case MODEMR_BOOT_DEV_HYPERFLASH80: 895 str = boot_hyper80; 896 break; 897 case MODEMR_BOOT_DEV_QSPI_FLASH40: 898 str = boot_qspi40; 899 break; 900 case MODEMR_BOOT_DEV_QSPI_FLASH80: 901 str = boot_qspi80; 902 break; 903 case MODEMR_BOOT_DEV_EMMC_25X1: 904 #if RCAR_LSI == RCAR_D3 905 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 906 panic(); 907 #endif 908 str = boot_emmc25x1; 909 break; 910 case MODEMR_BOOT_DEV_EMMC_50X8: 911 #if RCAR_LSI == RCAR_D3 912 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 913 panic(); 914 #endif 915 str = boot_emmc50x8; 916 break; 917 default: 918 str = unknown; 919 break; 920 } 921 NOTICE("BL2: Boot device is %s\n", str); 922 923 rcar_avs_setting(); 924 reg = rcar_rom_get_lcs(&lcs); 925 if (reg) { 926 str = unknown; 927 goto lcm_state; 928 } 929 930 switch (lcs) { 931 case LCS_CM: 932 str = lcs_cm; 933 break; 934 case LCS_DM: 935 str = lcs_dm; 936 break; 937 case LCS_SD: 938 str = lcs_sd; 939 break; 940 case LCS_SE: 941 str = lcs_secure; 942 break; 943 case LCS_FA: 944 str = lcs_fa; 945 break; 946 default: 947 str = unknown; 948 break; 949 } 950 951 lcm_state: 952 NOTICE("BL2: LCM state is %s\n", str); 953 954 rcar_avs_end(); 955 is_ddr_backup_mode(); 956 957 bl2_tzram_layout.total_base = BL31_BASE; 958 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 959 960 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 961 boot_cpu == MODEMR_BOOT_CPU_CA53) { 962 ret = rcar_dram_init(); 963 if (ret) { 964 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 965 panic(); 966 } 967 rcar_qos_init(); 968 } 969 970 /* Set up FDT */ 971 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 972 if (ret) { 973 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 974 panic(); 975 } 976 977 /* Add platform compatible string */ 978 bl2_populate_compatible_string(fdt); 979 980 /* Print DRAM layout */ 981 bl2_advertise_dram_size(product); 982 983 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 984 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 985 if (rcar_emmc_init() != EMMC_SUCCESS) { 986 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 987 panic(); 988 } 989 rcar_emmc_memcard_power(EMMC_POWER_ON); 990 if (rcar_emmc_mount() != EMMC_SUCCESS) { 991 NOTICE("BL2: Failed to eMMC mount operation.\n"); 992 panic(); 993 } 994 } else { 995 rcar_rpc_init(); 996 rcar_dma_init(); 997 } 998 999 reg = mmio_read_32(RST_WDTRSTCR); 1000 reg &= ~WDTRSTCR_RWDT_RSTMSK; 1001 reg |= WDTRSTCR_PASSWORD; 1002 mmio_write_32(RST_WDTRSTCR, reg); 1003 1004 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 1005 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 1006 1007 reg = mmio_read_32(RCAR_PRR); 1008 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 1009 mmio_write_32(CPG_CA57DBGRCR, 1010 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 1011 1012 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 1013 mmio_write_32(CPG_CA53DBGRCR, 1014 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 1015 1016 if (product_cut == PRR_PRODUCT_H3_CUT10) { 1017 reg = mmio_read_32(CPG_PLL2CR); 1018 reg &= ~((uint32_t) 1 << 5); 1019 mmio_write_32(CPG_PLL2CR, reg); 1020 1021 reg = mmio_read_32(CPG_PLL4CR); 1022 reg &= ~((uint32_t) 1 << 5); 1023 mmio_write_32(CPG_PLL4CR, reg); 1024 1025 reg = mmio_read_32(CPG_PLL0CR); 1026 reg &= ~((uint32_t) 1 << 12); 1027 mmio_write_32(CPG_PLL0CR, reg); 1028 } 1029 #if (RCAR_LOSSY_ENABLE == 1) 1030 NOTICE("BL2: Lossy Decomp areas\n"); 1031 1032 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 1033 if (fcnlnode < 0) { 1034 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 1035 fcnlnode); 1036 panic(); 1037 } 1038 1039 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 1040 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 1041 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 1042 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 1043 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 1044 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 1045 #endif 1046 1047 fdt_pack(fdt); 1048 NOTICE("BL2: FDT at %p\n", fdt); 1049 1050 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 1051 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 1052 rcar_io_emmc_setup(); 1053 else 1054 rcar_io_setup(); 1055 } 1056 1057 void bl2_el3_plat_arch_setup(void) 1058 { 1059 #if RCAR_BL2_DCACHE == 1 1060 NOTICE("BL2: D-Cache enable\n"); 1061 rcar_configure_mmu_el3(BL2_BASE, 1062 BL2_END - BL2_BASE, 1063 BL2_RO_BASE, BL2_RO_LIMIT 1064 #if USE_COHERENT_MEM 1065 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 1066 #endif 1067 ); 1068 #endif 1069 } 1070 1071 void bl2_platform_setup(void) 1072 { 1073 1074 } 1075 1076 static void bl2_init_generic_timer(void) 1077 { 1078 /* FIXME: V3M 16.666 MHz ? */ 1079 #if RCAR_LSI == RCAR_D3 1080 uint32_t reg_cntfid = EXTAL_DRAAK; 1081 #elif RCAR_LSI == RCAR_E3 1082 uint32_t reg_cntfid = EXTAL_EBISU; 1083 #else /* RCAR_LSI == RCAR_E3 */ 1084 uint32_t reg; 1085 uint32_t reg_cntfid; 1086 uint32_t modemr; 1087 uint32_t modemr_pll; 1088 uint32_t board_type; 1089 uint32_t board_rev; 1090 uint32_t pll_table[] = { 1091 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 1092 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 1093 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 1094 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 1095 }; 1096 1097 modemr = mmio_read_32(RCAR_MODEMR); 1098 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 1099 1100 /* Set frequency data in CNTFID0 */ 1101 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 1102 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 1103 switch (modemr_pll) { 1104 case MD14_MD13_TYPE_0: 1105 rcar_get_board_type(&board_type, &board_rev); 1106 if (BOARD_SALVATOR_XS == board_type) { 1107 reg_cntfid = EXTAL_SALVATOR_XS; 1108 } 1109 break; 1110 case MD14_MD13_TYPE_3: 1111 if (PRR_PRODUCT_H3_CUT10 == reg) { 1112 reg_cntfid = reg_cntfid >> 1U; 1113 } 1114 break; 1115 default: 1116 /* none */ 1117 break; 1118 } 1119 #endif /* RCAR_LSI == RCAR_E3 */ 1120 /* Update memory mapped and register based freqency */ 1121 write_cntfrq_el0((u_register_t )reg_cntfid); 1122 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1123 /* Enable counter */ 1124 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1125 (uint32_t)CNTCR_EN); 1126 } 1127