| 420c26b3 | 28-Sep-2021 |
Tinghan Shen <tinghan.shen@mediatek.com> |
fix(plat/mediatek/mt8183): fix out-of-bound access
Fix coverity checks which is found on:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1806/comment/eaec126f_af5eb624/
Change-Id: I
fix(plat/mediatek/mt8183): fix out-of-bound access
Fix coverity checks which is found on:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1806/comment/eaec126f_af5eb624/
Change-Id: I9405f7f67aa4115c1a7b8b4623b6b0830e62f814
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
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| 46789a7c | 26-Mar-2021 |
Balint Dobszay <balint.dobszay@arm.com> |
build(bl2): enable SP pkg loading for S-EL1 SPMC
Currently the SP package loading mechanism is only enabled when S-EL2
SPMC is selected. Remove this limitation.
Signed-off-by: Balint Dobszay <balin
build(bl2): enable SP pkg loading for S-EL1 SPMC
Currently the SP package loading mechanism is only enabled when S-EL2
SPMC is selected. Remove this limitation.
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Change-Id: I5bf5a32248e85a26d0345cacff7d539eed824cfc
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| b7bc51a7 | 06-Sep-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
fix: OP-TEE SP manifest per latest SPMC changes
Update UUID to little endian:
The SPMC expects a little endian representation of the UUID as an array
of four integers in the SP manifest.
Add manage
fix: OP-TEE SP manifest per latest SPMC changes
Update UUID to little endian:
The SPMC expects a little endian representation of the UUID as an array
of four integers in the SP manifest.
Add managed exit field and cosmetic comments updates.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icad93ca70bc27bc9d83b8cf888fe5f8839cb1288
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| b3b162f3 | 28-Sep-2021 |
Pan Gao <gtk_pangao@mediatek.com> |
feat(plat/mediatek/common): enable software reset for CIRQ
CIRQ software reset can be used on all platforms, so we remove
CIRQ_NEED_SW_RESET in mt_cirq_sw_reset to enable software reset.
BUG=b:1922
feat(plat/mediatek/common): enable software reset for CIRQ
CIRQ software reset can be used on all platforms, so we remove
CIRQ_NEED_SW_RESET in mt_cirq_sw_reset to enable software reset.
BUG=b:192200380, b:201035723
Signed-off-by: Pan Gao <gtk_pangao@mediatek.com>
Change-Id: Id53ea099ae566bf2a573fca866bd10c60429bd5a
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| 3b994a75 | 10-Aug-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8195): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those
feat(plat/mdeiatek/mt8195): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.
BUG=b:192429713
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I02c6c862b6217bc84c83a09b533bd53ec19b06f7
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| ab5964aa | 26-Sep-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration
* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls102
Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration
* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls1028ardb board support
feat(plat/nxp/ls1028a): add ls1028a soc support
feat(plat/nxp/common): define default SD buffer
feat(driver/nxp/xspi): add MT35XU02G flash info
feat(plat/nxp/common): add SecMon register definition for ch_3_2
feat(driver/nxp/dcfg): define RSTCR_RESET_REQ
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
feat(plat/nxp/common): define default PSCI features if not defined
feat(plat/nxp/common): define common macro for ARM registers
feat(plat/nxp/common): add CCI and EPU address definition
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| 98c58a94 | 24-Sep-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(plat/mediatek/mt8195): fix coverity fail" into integration |
| 34e2112d | 13-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/ls1028ardb): add ls1028ardb board support
The LS1028A reference design board (RDB) is a computing,
evaluation, and development platform that supports industrial
IoT applications, human
feat(plat/nxp/ls1028ardb): add ls1028ardb board support
The LS1028A reference design board (RDB) is a computing,
evaluation, and development platform that supports industrial
IoT applications, human machine interface solutions, and
industrial networking.
It supports the following features:
1. Layerscape LS1028A dual-core processor based on Cortex-A72
at 1.3 GHz.
2. 4 GB DDR4 SDRAM w/ECC
3. Support Ethernet:
1) x1 RJ45 connector for 1Gbps Ethernet support w/TSN, 1588
2) x4 RJ45 connector for 1Gbps Ethernet switch support w/TSN,
1588 (QSGMII)
3. With Basic Peripherals and Interconnect
2x M.2 Type E slots with PCIe Gen 3.0 x1
1x M.2 Type B slot with SATA 3.0 (resistor mux with 1 Type E slot)
1x Type A USB 3.0 super-speed port
1x Type C USB 3.0 super-speed port
1x DisplayPort interface
2x DB9 RS232 serial ports
2x DB9 CAN interfaces
1x 3.5 mm audio out
2x MikroBUS™ sockets
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Change-Id: I48ee254a488ae4af227641da3875a1e9a63a720c
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| 9d250f03 | 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/ls1028a): add ls1028a soc support
The QorIQ LS1028A processor integrates two 64-bit ARM Cortex-A72
cores with a GPU and LCD controller, as well as a TSNenabled
Ethernet port and a TSN-
feat(plat/nxp/ls1028a): add ls1028a soc support
The QorIQ LS1028A processor integrates two 64-bit ARM Cortex-A72
cores with a GPU and LCD controller, as well as a TSNenabled
Ethernet port and a TSN-enabled switch with four external ports.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Change-Id: I9f65c6af5db7e20702828cd208290c1b43a54941
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| 46ee50e0 | 24-May-2021 |
Saurabh Gorecha <sgorecha@codeaurora.org> |
feat(plat/qti/sc7280): support for qti sc7280 plat
new qti platform sc7280 support addition
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f216
feat(plat/qti/sc7280): support for qti sc7280 plat
new qti platform sc7280 support addition
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f21656c1
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| b38e2ed2 | 14-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
fix(plat/st): add UART reset in crash console init
Add the reset set/clear sequence at the beginning of the function
plat_crash_console_init(). If not done, there is a risk that the UART
is in a bad
fix(plat/st): add UART reset in crash console init
Add the reset set/clear sequence at the beginning of the function
plat_crash_console_init(). If not done, there is a risk that the UART
is in a bad state and will not be able to print correct characters.
Change-Id: Id31e28773d6c4f26f16d3569d1e3c5aa0e26e039
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| b3210f4d | 17-Sep-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "TrcDbgExt" into integration
* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS E
Merge changes from topic "TrcDbgExt" into integration
* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS EL
feat(trf): initialize trap settings of trace filter control registers access
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
feat(sys_reg_trace): initialize trap settings of trace system registers access
feat(trbe): enable access to trace buffer control registers from lower NS EL
feat(trbe): initialize trap settings of trace buffer control registers access
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| 85e4d14d | 17-Sep-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
fix(plat/mediatek/mt8195): fix coverity fail
Add break to correct the driver flow.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie20f402d543fbf90172671e007fad30d5dc2ab10 |
| d2726117 | 15-Sep-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes Iedc19d8f,Ic5fc78c9 into integration
* changes:
feat(plat/mediatek/mt8195): add EMI MPU basic drivers
feat(plat/mediatek/mt8195): add vcore-dvfs support |
| be1eba51 | 15-Sep-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "refactor(tc): use internal trusted storage" into integration |
| 38f79045 | 10-Aug-2021 |
Davidson K <davidson.kumaresan@arm.com> |
refactor(tc): use internal trusted storage
Trusted Services had removed secure storage and added two new
trusted services - Protected Storage and Internal Trusted Storage.
Hence we are removing secu
refactor(tc): use internal trusted storage
Trusted Services had removed secure storage and added two new
trusted services - Protected Storage and Internal Trusted Storage.
Hence we are removing secure storage and adding support for the
internal trusted storage.
And enable external SP images in BL2 config for TC, so that
we do not have to modify this file whenever the list of SPs
changes. It is already implemented for fvp in the below commit.
commit 33993a3737737a03ee5a9d386d0a027bdc947c9c
Author: Balint Dobszay <balint.dobszay@arm.com>
Date: Fri Mar 26 15:19:11 2021 +0100
feat(fvp): enable external SP images in BL2 config
Change-Id: I3e0a0973df3644413ca5c3a32f36d44c8efd49c7
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
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| 4225ce8b | 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common): define default SD buffer
Define default SD buffer address and size in DRAM.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-I
feat(plat/nxp/common): define default SD buffer
Define default SD buffer address and size in DRAM.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5872d95b0c1114e05f0e145756e9a6ef39b2fd9a
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| 66f7884b | 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common): add SecMon register definition for ch_3_2
Add SecMon register definition for ch_3_2.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.co
feat(plat/nxp/common): add SecMon register definition for ch_3_2
Add SecMon register definition for ch_3_2.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I80d134ea4e94ad234e1a8fbd02798d5fd86d2544
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| 3a2cc2e2 | 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
Define CPUECTLR_TIMER_2TICKS.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iecb5ed
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
Define CPUECTLR_TIMER_2TICKS.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iecb5ede82939e8502d2f1bc74ec3bfe2a00be65c
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| a2047853 | 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common): define default PSCI features if not defined
SoC code can define supported features, otherwise use default setting.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: J
feat(plat/nxp/common): define default PSCI features if not defined
SoC code can define supported features, otherwise use default setting.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I0f11498c1f7558ff0ec2d9b344f3f7a4f5489ced
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| 35efe7a4 | 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common): define common macro for ARM registers
Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.
Signed-off-by: Bi
feat(plat/nxp/common): define common macro for ARM registers
Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I485661bfe3ed4f214c403ff6af53dc6af1ddf089
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| 6cad59c4 | 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common): add CCI and EPU address definition
Add CCI and EPU base address definiton for Chassis v3.2.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I13250555b6646c1e7ba2e9d
feat(plat/nxp/common): add CCI and EPU address definition
Add CCI and EPU base address definiton for Chassis v3.2.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I13250555b6646c1e7ba2e9d7c9efca8501f17b3a
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| 75edd34a | 19-Aug-2021 |
Penny Jan <penny.jan@mediatek.com> |
feat(plat/mediatek/mt8195): add EMI MPU basic drivers
EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and
feat(plat/mediatek/mt8195): add EMI MPU basic drivers
EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and will add more setting for
EMI MPU in next patch.
Change-Id: Iedc19d8f6fcf1ceb2d8241319b8dc17c885642dd
Signed-off-by: Penny Jan <penny.jan@mediatek.com>
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| 3a355c2d | 14-Sep-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(plat/synquacer): update scmi power domain off handling" into integration |
| a16ecd2c | 06-Apr-2021 |
Ying-Chun Liu (PaulLiu) <paulliu@debian.org> |
feat(plat/imx/imx8m/imx8mp): enable Trusted Boot
This patch enables Trusted Boot on the i.MX8MP with BL2 doing image
verification from a FIP prior to hand-over to BL31.
Signed-off-by: Ying-Chun Liu
feat(plat/imx/imx8m/imx8mp): enable Trusted Boot
This patch enables Trusted Boot on the i.MX8MP with BL2 doing image
verification from a FIP prior to hand-over to BL31.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: Iac1d1d62ea9858f67326a47c1e5ba377f23f9db5
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