Merge changes from topic "ethosn-multi-device" into integration

* changes:
feat(drivers/arm/ethosn)!: multi-device support
feat(fdt): add for_each_compatible_node macro

feat(rme): disable Watchdog for Arm platforms if FEAT_RME enabled

In the typical TF-A boot flow, the Trusted Watchdog is started
at the beginning of BL1 and then stopped in BL1 after returning
from

feat(rme): disable Watchdog for Arm platforms if FEAT_RME enabled

In the typical TF-A boot flow, the Trusted Watchdog is started
at the beginning of BL1 and then stopped in BL1 after returning
from BL2. However, in the RME boot flow there is no return path
from BL2 to BL1. Therefore, disable the Watchdog if ENABLE_RME is set.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: Id88fbfab8e8440642414bed48c50e3fcb23f3621

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fix(plat/fvp): bump BL2 stack size

VERBOSE print logs need a larger stack size and the currently configured
BL2 stack size was insufficient for FVP. This patch increases the same.

Signed-off-by: So

fix(plat/fvp): bump BL2 stack size

VERBOSE print logs need a larger stack size and the currently configured
BL2 stack size was insufficient for FVP. This patch increases the same.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I316ba2ea467571161b5f4807e6e5fa0bf89d44c6

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fix(plat/fvp): allow changing the kernel DTB load address

We currently use ARM_PRELOADED_DTB_BASE build
variable to pass the kernel DTB base address to
the kernel when using the ARM_LINUX_KERNEL_AS_

fix(plat/fvp): allow changing the kernel DTB load address

We currently use ARM_PRELOADED_DTB_BASE build
variable to pass the kernel DTB base address to
the kernel when using the ARM_LINUX_KERNEL_AS_BL33
option. However this variable doesn't actually
change the DTB load address.

The DTB load address is actually specified in the
FW_CONFIG DTS (fvp_fw_config.dts) as 'hw_config'.
This patch passes the hw_config value instead of
ARM_PRELOADED_DTB_BASE allowing us to change
the kernel DTB load address through
fvp_fw_config.dts.

With this change we don't need the ARM_PRELOADED_DTB_BASE
build variable if RESET_TO_BL31 is not set.
Note that the hw_config value needs to be within the
ARM_DTB_DRAM_NS region specified by FVP_DTB_DRAM_MAP_START
and FVP_DTB_DRAM_MAP_SIZE.

This patch also expands the ARM_DTB_DRAM_NS region to 32MB.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: Idd74cdf5d2c649bb320644392ba5d69e175a53a9

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refactor(plat/arm): rename ARM_DTB_DRAM_NS region macros

The macros PLAT_HW_CONFIG_DTB_BASE and PLAT_HW_CONFIG_DTB_SIZE
describe the range of memory where the HW_CONFIG_DTB can be loaded
rather than

refactor(plat/arm): rename ARM_DTB_DRAM_NS region macros

The macros PLAT_HW_CONFIG_DTB_BASE and PLAT_HW_CONFIG_DTB_SIZE
describe the range of memory where the HW_CONFIG_DTB can be loaded
rather than the actual load address and size of the DTB. This patch
changes the names to something more descriptive.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I98b81f3ce0c80fd76614f959667c25b07941e190

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feat(plat/arm): add GPT initialization code for Arm platforms

When RME is enabled, during configuration of the TrustZone controller,
Root regions are initially configured as Secure regions, and Real

feat(plat/arm): add GPT initialization code for Arm platforms

When RME is enabled, during configuration of the TrustZone controller,
Root regions are initially configured as Secure regions, and Realm
regions as Non-secure regions. Then later these regions are configured
as Root and Realm regions respectively in the GPT. According to the RME
architecture reference manual, Root firmware must ensure that Granule
Protection Check is enabled before enabling any stage of translation.
Therefore initializations are done as follows when RME is enabled :

Initialize/enable the TrustZone controller (plat_arm_security_setup) -->
Initialize/enable GPC (arm_bl2_plat_gpt_setup) -->
enable MMU (enable_mmu_el3)

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I91094e8259079437bee02de1f65edb9ad51e43cf

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feat(plat/fvp): add memory map for FVP platform for FEAT_RME

When FEAT_RME is enabled, memory is divided into four Physical
Address Spaces (PAS): Root, Realm, Secure and Non-secure.
This patch intro

feat(plat/fvp): add memory map for FVP platform for FEAT_RME

When FEAT_RME is enabled, memory is divided into four Physical
Address Spaces (PAS): Root, Realm, Secure and Non-secure.
This patch introduces new carveouts for the Trusted SRAM and DRAM
for the FVP platform accordingly.

The following new regions are introduced with this change:

ARM_MAP_L0_GPT_REGION: Trusted SRAM region used to store Level 0
Granule Protection Table (GPT). This region resides in the Root PAS.

ARM_MAP_GPT_L1_DRAM: DRAM region used to store Level 1 GPT. It
resides in the Root PAS.

ARM_MAP_RMM_DRAM: DRAM region used to store RMM image. It
resides in the Realm PAS.

The L0 GPT is stored on Trusted SRAM next to firmware configuration
memory. The DRAM carveout when RME is enable is modified as follow:

--------------------
| |
| AP TZC (~28MB) |
--------------------
| |
| REALM (32MB) |
--------------------
| |
| EL3 TZC (3MB) |
--------------------
| L1 GPT + SCP TZC |
| (~1MB) |
0xFFFF_FFFF --------------------

During initialization of the TrustZone controller, Root regions
are configured as Secure regions. Then they are later reconfigured
to Root upon GPT initialization.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: If2e257141d51f51f715b70d4a06f18af53607254

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refactor(plat/arm): modify memory region attributes to account for FEAT_RME

If FEAT_RME is enabled, EL3 runs in the Root world as opposed to
Secure world. This patch changes EL3 memory region attrib

refactor(plat/arm): modify memory region attributes to account for FEAT_RME

If FEAT_RME is enabled, EL3 runs in the Root world as opposed to
Secure world. This patch changes EL3 memory region attributes for
Arm platforms accordingly.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: Ie176f8b440ff34330e4e44bd3bf8d9703b3892ff

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feat(plat/fvp): add RMM image support for FVP platform

This patch adds the necessary changes needed to build
and load RMM image for the FVP platform. RMM image is
loaded by BL2 after BL32 (if BL32 e

feat(plat/fvp): add RMM image support for FVP platform

This patch adds the necessary changes needed to build
and load RMM image for the FVP platform. RMM image is
loaded by BL2 after BL32 (if BL32 exists) and before BL33.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I1ac9eade84c2e35c7479a322ca1d090b4e626819

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refactor(makefile): remove BL prefixes in build macros

The current Makefile assumes all TF-A binaries
have BL prefixes (BL1, BL2, etc). Now that we
have other binary names with FEAT_RME feature, rem

refactor(makefile): remove BL prefixes in build macros

The current Makefile assumes all TF-A binaries
have BL prefixes (BL1, BL2, etc). Now that we
have other binary names with FEAT_RME feature, remove
this assumption. With this change, we need to pass
the full name of a binary when using build macros.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I44e094b2366aa526f807d92dffa709390d14d145

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feat(rme): add Test Realm Payload (TRP)

TRP is a small test payload that implements Realm Monitor
Management (RMM) functionalities. RMM runs in the Realm world
(R-EL2) and manages the execution of R

feat(rme): add Test Realm Payload (TRP)

TRP is a small test payload that implements Realm Monitor
Management (RMM) functionalities. RMM runs in the Realm world
(R-EL2) and manages the execution of Realm VMs and their
interaction with the hypervisor in Normal world.

TRP is used to test the interface between RMM and Normal world
software, known as Realm Management Interface (RMI). Current
functions includes returning RMM version and transitioning
granules from Non-secure to Realm world and vice versa.

More information about RMM can be found at:
https://developer.arm.com/documentation/den0125/latest

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: Ic7b9a1e1f3142ef6458d40150d0b4ba6bd723ea2

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Merge changes Ie7c0eaf2,I11d882f3,I3f173ac4,If1fa12bf,I3e3a202f, ... into integration

* changes:
feat(plat/rcar3): keep RWDT enabled
feat(drivers/rcar3): add extra offset if booting B-side
fea

Merge changes Ie7c0eaf2,I11d882f3,I3f173ac4,If1fa12bf,I3e3a202f, ... into integration

* changes:
feat(plat/rcar3): keep RWDT enabled
feat(drivers/rcar3): add extra offset if booting B-side
feat(plat/rcar3): modify LifeC register setting for R-Car D3
feat(plat/rcar3): modify SWDT counter setting for R-Car D3
feat(plat/rcar3): update DDR setting for R-Car D3
feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3
feat(plat/rcar3): add process of SSCG setting for R-Car D3
feat(plat/rcar3): add process to back up X6 and X7 register's value
feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR
feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up
feat(plat/rcar3): change the memory map for OP-TEE
feat(plat/rcar3): use PRR cut to determine DRAM size on M3
feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537
fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3
fix(plat/rcar3): fix eMMC boot support for R-Car D3
fix(plat/rcar3): fix version judgment for R-Car D3
fix(plat/rcar3): fix source file to make about GICv2
fix(drivers/rcar3): console: fix a return value of console_rcar_init

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fix(fvp): fix fvp_cpu_standby() function

The latest FVP model fix which correctly checks if IRQs
are enabled in current exception level, is causing TFTF
tests to hang.
This patch adds setting SCR_EL

fix(fvp): fix fvp_cpu_standby() function

The latest FVP model fix which correctly checks if IRQs
are enabled in current exception level, is causing TFTF
tests to hang.
This patch adds setting SCR_EL3.I and SCR_EL3.F bits in
'fvp_cpu_standby()' function to allow CPU to exit from WFI.

Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: Iceec1e9dbd805803d370ecdb10e04ad135d6b3aa

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fix(arm_fpga): streamline generated axf file

For convenience we let the build system generate an ELF file (named
bl31.axf), containing all the trampolines, BL31 code and the DTB in one
file. This ca

fix(arm_fpga): streamline generated axf file

For convenience we let the build system generate an ELF file (named
bl31.axf), containing all the trampolines, BL31 code and the DTB in one
file. This can be fed directly into the FPGA payload tool, and it will
load the bits at the right addresses.
Since this ELF file is more used as a "container with load addresses",
there is no need for normal ELF features like alignment or a symbol
table.

Remove unnecessary sections from that output file, by doing a static
"link", dropping the NOBITS stacks section, and by adding "-n" to the
linker command line (to avoid page alignment). This trims the generated
.axf file, and makes it smaller.

Change-Id: I5768543101d667fb4a3b70e60b08cfe970d2a2b6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(arm_fpga): add kernel trampoline

The arm64 Linux kernel needed to be loaded at a certain offset within any
2MB aligned region; this value was configured at compile time and stored
in the Linux

feat(arm_fpga): add kernel trampoline

The arm64 Linux kernel needed to be loaded at a certain offset within any
2MB aligned region; this value was configured at compile time and stored
in the Linux kernel image header. The default value was always 512KiB,
so this is the value we use in the TF-A build system for the kernel
load address.
However the whole scheme around the TEXT_OFFSET changed in Linux v5.8:
Linux kernels became fully relocatable, so this value is largely ignored
now, and its default value changed to 0. The only remainder is a warning
message at boot time in case there is a mismatch:
[Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!

To avoid this warning, and to make TF-A Linux kernel boot protocol
compliant, we should load newer kernels to offset 0 of a 2 MB
region. This can be done by the user at FPGA boot time, but BL31 needs
to know about this address. As we can't change the build default to 0
without breaking older kernels, we should try to make a build dealing
with both versions:

This patch introduces a small trampoline code, which gets loaded at
512KB of DRAM, and branches up to 2MB. If users load their newer
kernels at 2MB, this trampoline will cover them. In case an older kernel
is loaded at 512KB, it will overwrite this trampoline code, so it would
still work.

Change-Id: If49ca86f5dca380036caf2555349748722901277
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "imx8mp-tbbr" into integration

* changes:
feat(plat/imx/imx8m/imx8mp): enable Trusted Boot
feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP
refactor(plat/imx/imx8m): m

Merge changes from topic "imx8mp-tbbr" into integration

* changes:
feat(plat/imx/imx8m/imx8mp): enable Trusted Boot
feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP
refactor(plat/imx/imx8m): make image load logic for TBBR FIP booting common
feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout
refactor(plat/imx/imx): make imx io-storage logic for TBBR/FIP common
feat(plat/imx/imx8m/imx8mp): add imx8mp_private.h to the build

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feat(drivers/arm/ethosn)!: multi-device support

Add support for Arm Ethos-N NPU multi-device.

The device tree parsing currently only supports one NPU device with
multiple cores. To be able to suppo

feat(drivers/arm/ethosn)!: multi-device support

Add support for Arm Ethos-N NPU multi-device.

The device tree parsing currently only supports one NPU device with
multiple cores. To be able to support multi-device NPU configurations
this patch adds support for having multiple NPU devices in the device
tree.

To be able to support multiple NPU devices in the SMC API, it has been
changed in an incompatible way so the API version has been bumped.

Signed-off-by: Laurent Carlier <laurent.carlier@arm.com>
Change-Id: Ide279ce949bd06e8939268b9601c267e45f3edc3

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Merge "feat(cpu): add support for Hayes CPU" into integration

feat(cpu): add support for Hayes CPU

This patch adds the basic CPU library code to support the Hayes CPU
in TF-A. This CPU is based on the Klein core so that library code
has been adapted for use he

feat(cpu): add support for Hayes CPU

This patch adds the basic CPU library code to support the Hayes CPU
in TF-A. This CPU is based on the Klein core so that library code
has been adapted for use here.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If0e0070cfa77fee8f6eebfee13d3c4f209ad84fc

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fvp_r: load, auth, and transfer from BL1 to BL33

Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.

Signed-off-by: Lauren Wehrme

fvp_r: load, auth, and transfer from BL1 to BL33

Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I293cad09739dacac0d20dd57c1d98178dbe84d40

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chore: fvp_r: Initial No-EL3 and MPU Implementation

For v8-R64, especially R82, creating code to run BL1 at EL2, using MPU.

Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I439ac39

chore: fvp_r: Initial No-EL3 and MPU Implementation

For v8-R64, especially R82, creating code to run BL1 at EL2, using MPU.

Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I439ac3915b982ad1e61d24365bdd1584b3070425

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fvp_r: initial platform port for fvp_r

Creating a platform port for FVP_R based on the FVP platform.
Differences including only-BL1, aarch64, Secure only, and EL2 being the
ELmax (No EL3).

Signed-o

fvp_r: initial platform port for fvp_r

Creating a platform port for FVP_R based on the FVP platform.
Differences including only-BL1, aarch64, Secure only, and EL2 being the
ELmax (No EL3).

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I1283e033fbd4e03c397d0a2c10c4139548b4eee4

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Merge changes from topic "st_fixes" into integration

* changes:
fix(stm32_console): do not skip init for crash console
fix(plat/st): add UART reset in crash console init
refactor(stm32mp1_clk)

Merge changes from topic "st_fixes" into integration

* changes:
fix(stm32_console): do not skip init for crash console
fix(plat/st): add UART reset in crash console init
refactor(stm32mp1_clk): update RCC registers file
fix(stm32mp1_clk): keep RTCAPB clock always on
fix(stm32mp1_clk): fix RTC clock rating
fix(stm32mp1_clk): correctly manage RTC clock source
fix(spi_nand): check correct manufacturer id
fix(spi_nand): check that parameters have been set

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feat(plat/arm/sgi): add CPU specific handler for Neoverse N2

The 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an
explicit write to clear it for hotplug and idle to function correctly.
S

feat(plat/arm/sgi): add CPU specific handler for Neoverse N2

The 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an
explicit write to clear it for hotplug and idle to function correctly.
So add Neoverse N2 CPU specific handler in platform reset handler to
clear the CORE_PWRDN_EN bit.

Signed-off-by: shriram.k <shriram.k@arm.com>
Change-Id: If3859447410c4b8e704588993941178fa9411f52

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feat(plat/arm/sgi): add CPU specific handler for Neoverse V1

The 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an
explicit write to clear it for hotplug and idle to function correctly.
S

feat(plat/arm/sgi): add CPU specific handler for Neoverse V1

The 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an
explicit write to clear it for hotplug and idle to function correctly.
So add Neoverse V1 CPU specific handler in platform reset handler to
clear the CORE_PWRDN_EN bit.

Signed-off-by: shriram.k <shriram.k@arm.com>
Change-Id: I56084c42a56c401503a751cb518238c83cfca8ac

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