refactor(measured boot): rename tpm_record_measurement()

tpm_record_measurement() function name suggests that:

- It only records a measurement but does not compute it.
This is not the case, the

refactor(measured boot): rename tpm_record_measurement()

tpm_record_measurement() function name suggests that:

- It only records a measurement but does not compute it.
This is not the case, the function does both.

- It stores this measurement into a TPM (discrete chip or fTPM).
This is not the case either, the measurement is just stored into
the event log, which is a data structure hold in memory, there is
no TPM involvement here.

To better convey the intent of the function, rename it into
event_log_measure_and_record().

Change-Id: I0102eeda477d6c6761151ac96759b31b6997e9fb
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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feat(plat/arm): Add DRAM2 to TZC non-secure region

This allows to increase the total DRAM to 8GB.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I6daaed9a0b7a11d665b2f56e6432a1ef87bfaa38

Merge "plat/marvell/a8k: add Globalscale Mochabin support" into integration

Merge "fix(plat/qemu): reboot/shutdown with low to high gpio" into integration

fix(plat/qemu): reboot/shutdown with low to high gpio

Use low to high gpio sequence to reboot/shutdown qemu machine.

Use low to high gpio pins level change which will cause an interrupt
in qemu vir

fix(plat/qemu): reboot/shutdown with low to high gpio

Use low to high gpio sequence to reboot/shutdown qemu machine.

Use low to high gpio pins level change which will cause an interrupt
in qemu virt platform. This change will supported with next qemu 6.1
release once patchset:
hw/arm: Make virt board secure powerdown/reset work
will be merged.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
CC: Peter Maydell <peter.maydell@linaro.org>
Change-Id: I70979517358c3b587722b2dcb33f63d29bf79d9b

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plat/marvell/a8k: add Globalscale Mochabin support

Add support for Globalscale MOCHAbin board.

Its based on Armada 7040 SoC and ships in multiple DRAM options:
* 2GB DDR4 (1CS)
* 4GB DDR4 (1CS)
* 8

plat/marvell/a8k: add Globalscale Mochabin support

Add support for Globalscale MOCHAbin board.

Its based on Armada 7040 SoC and ships in multiple DRAM options:
* 2GB DDR4 (1CS)
* 4GB DDR4 (1CS)
* 8GB DDR4 (2CS)

Since it ships in multiple DRAM configurations, an
Armada 3k style DDR_TOPOLOGY variable is added.
Currently, this only has effect on the MOCHAbin, but
I expect more boards with multiple DRAM sizes to be
supported.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Change-Id: I8a1ec9268fed34f6a81c5cbf1e891f638d461305

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Merge "fix(arm_fgpa): allow build after MAKE_* changes" into integration

feat(nxp/common/ocram): add driver for OCRAM initialization

In order to enable OCRAM ECC, it need to be initialized
with 64-bit writes and then a write performed to address
0x0010_0534 with the valu

feat(nxp/common/ocram): add driver for OCRAM initialization

In order to enable OCRAM ECC, it need to be initialized
with 64-bit writes and then a write performed to address
0x0010_0534 with the value 0x0000_0008.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Id7d4f5df65ca52f24e9251c08a75ad2006451b95

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feat(plat/nxp/common): add EESR register definition

Add OCRAM bit mask to be used in OCRAM driver.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: If82542cc6c1c243d8f998b193954dd72312ee1a4

fix(plat/nxp/ls1028a): fix compile error when enable fuse provision

Fix the error that no "gpio_init_data" is defined when
build with "FUSE_PROG=1".

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
C

fix(plat/nxp/ls1028a): fix compile error when enable fuse provision

Fix the error that no "gpio_init_data" is defined when
build with "FUSE_PROG=1".

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I0ba8005725fe33c6d8e68b4d52539f5d5d749f1a

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fix(plat/nxp/ls1028a): define endianness of scfg and gpio

Define endianness of scfg and gpio.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ifa18b4fcfc45154c23d54692b374bab293c51a04

Merge changes I9405f7f6,Id53ea099 into integration

* changes:
fix(plat/mediatek/mt8183): fix out-of-bound access
feat(plat/mediatek/common): enable software reset for CIRQ

Merge "feat(fvp_r): configure system registers to boot rich OS" into integration

fix(arm_fgpa): allow build after MAKE_* changes

Commit 434d0491c550 ("refactor(makefile): remove BL prefixes in build
macros") changed the MAKE_S macro to expect "bl31" instead of just "31".

Adjust

fix(arm_fgpa): allow build after MAKE_* changes

Commit 434d0491c550 ("refactor(makefile): remove BL prefixes in build
macros") changed the MAKE_S macro to expect "bl31" instead of just "31".

Adjust our calls to MAKE_S and MAKE_LD to fix the build for arm_fpga.

Change-Id: I2743e421c10eaecb39bfa4515ea049a1b8d18fcb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(stm32mp1): add bl prefix for internal linker script

Due to patch [1], the bl prefix was removed from the build macros.
It should then add explicitly when compiling stm32mp1.ld.S.

[1] 434d0491c5

fix(stm32mp1): add bl prefix for internal linker script

Due to patch [1], the bl prefix was removed from the build macros.
It should then add explicitly when compiling stm32mp1.ld.S.

[1] 434d0491c5 ("refactor(makefile): remove BL prefixes in build macros")

Change-Id: I298dba2a7c958dd4ea6429c83ed4b1ee97e1735f
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(plat/st): correct signedness comparison issue

Add casts where required to avoid compialtion error when enabling
-Wsign-compare in shared resources file.
The assert is also corrected to match the

fix(plat/st): correct signedness comparison issue

Add casts where required to avoid compialtion error when enabling
-Wsign-compare in shared resources file.
The assert is also corrected to match the correct range (change ||
to &&).

Change-Id: Ie4c9c0c935d39ff9a2165b909172aacb3e94ab4d
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "refactor(fvp_r): tidy up platform port [1]" into integration

Merge changes from topic "za/feat_rme" into integration

* changes:
refactor(gpt): productize and refactor GPT library
feat(rme): disable Watchdog for Arm platforms if FEAT_RME enabled
docs(rme

Merge changes from topic "za/feat_rme" into integration

* changes:
refactor(gpt): productize and refactor GPT library
feat(rme): disable Watchdog for Arm platforms if FEAT_RME enabled
docs(rme): add build and run instructions for FEAT_RME
fix(plat/fvp): bump BL2 stack size
fix(plat/fvp): allow changing the kernel DTB load address
refactor(plat/arm): rename ARM_DTB_DRAM_NS region macros
refactor(plat/fvp): update FVP platform DTS for FEAT_RME
feat(plat/arm): add GPT initialization code for Arm platforms
feat(plat/fvp): add memory map for FVP platform for FEAT_RME
refactor(plat/arm): modify memory region attributes to account for FEAT_RME
feat(plat/fvp): add RMM image support for FVP platform
feat(rme): add GPT Library
feat(rme): add ENABLE_RME build option and support for RMM image
refactor(makefile): remove BL prefixes in build macros
feat(rme): add context management changes for FEAT_RME
feat(rme): add Test Realm Payload (TRP)
feat(rme): add RMM dispatcher (RMMD)
feat(rme): run BL2 in root world when FEAT_RME is enabled
feat(rme): add xlat table library changes for FEAT_RME
feat(rme): add Realm security state definition
feat(rme): add register definitions and helper functions for FEAT_RME

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feat(fvp_r): configure system registers to boot rich OS

Following system registers are modified before exiting EL2 to allow
u-boot/Linux to boot
1. CNTHCTL_EL2.EL1PCTEN -> 1
Allows U-boot to

feat(fvp_r): configure system registers to boot rich OS

Following system registers are modified before exiting EL2 to allow
u-boot/Linux to boot
1. CNTHCTL_EL2.EL1PCTEN -> 1
Allows U-boot to use physical counters at EL1
2. VTCR_EL2.MSA -> 1
Enables VMSA at EL1, which is required by U-Boot and Linux.
3. HCR_EL2.APK = 1 & HCR_EL2.API = 1
Disables PAuth instruction and register traps in EL1

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I58f45b6669a9ad1debb80265b243015c054a9bb1

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refactor(fvp_r): tidy up platform port [1]

Following changes done:
1. Remove "fvp_r" specific check from bl1.mk
2. Override BL1_SOURCES in fvp_r platform.mk
3. Regroup source files
4. Remove

refactor(fvp_r): tidy up platform port [1]

Following changes done:
1. Remove "fvp_r" specific check from bl1.mk
2. Override BL1_SOURCES in fvp_r platform.mk
3. Regroup source files
4. Remove platform specific change from arm_common

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I74d0b1f317853ab1333744d8da5c59f937789547

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Merge "feat(plat/mdeiatek/mt8195): add DFD control in SiP service" into integration

fix(plat/st): only check header major when booting

An STM32 image with the awaited header major version shouldn't be forbid
to boot. If the minor differs, then it means only non-mandatory options
ha

fix(plat/st): only check header major when booting

An STM32 image with the awaited header major version shouldn't be forbid
to boot. If the minor differs, then it means only non-mandatory options
have been added in the reserved fields, and the header remains backward
compatible.

Change-Id: Iff16b67f95c728e2f1d128bd1760a4be497c5ca3
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(plat/st): create new helper for DT access

dt_match_instance_by_compatible() gives the DT node offset in DT
that matches both compatible and the peripheral instance address.

Change-Id: Ia85f4f4

feat(plat/st): create new helper for DT access

dt_match_instance_by_compatible() gives the DT node offset in DT
that matches both compatible and the peripheral instance address.

Change-Id: Ia85f4f4aa8fe8efd4df310d765e7586e67aa34c2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(gpt): productize and refactor GPT library

This patch updates and refactors the GPT library and fixes bugs.

- Support all combinations of PGS, PPS, and L0GPTSZ parameters.
- PPS and PGS are

refactor(gpt): productize and refactor GPT library

This patch updates and refactors the GPT library and fixes bugs.

- Support all combinations of PGS, PPS, and L0GPTSZ parameters.
- PPS and PGS are set at runtime, L0GPTSZ is read from GPCCR_EL3.
- Use compiler definitions to simplify code.
- Renaming functions to better suit intended uses.
- MMU enabled before GPT APIs called.
- Add comments to make function usage more clear in GPT library.
- Added _rme suffix to file names to differentiate better from the
GPT file system code.
- Renamed gpt_defs.h to gpt_rme_private.h to better separate private
and public code.
- Renamed gpt_core.c to gpt_rme.c to better conform to TF-A precedent.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4cbb23b0f81e697baa9fb23ba458aa3f7d1ed919

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Merge changes from topic "arm_fpga_resmem" into integration

* changes:
fix(arm_fpga): reserve BL31 memory
fix(arm_fpga): limit BL31 memory usage