fix(intel): fix bit masking issue in intel_secure_reg_update

intel_secure_reg_update function should apply mask to the value before
write into register.

Signed-off-by: Siew Chin Lim <elly.siew.chin

fix(intel): fix bit masking issue in intel_secure_reg_update

intel_secure_reg_update function should apply mask to the value before
write into register.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Change-Id: I84bbd06e24b8666528b53030e8359743d438eb5b

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fix(intel): fix ddr address range checker

This patch fix address range checker to make sure that it does not
errors out on NULL address with size 0. Non-secure software will send
this NULL address i

fix(intel): fix ddr address range checker

This patch fix address range checker to make sure that it does not
errors out on NULL address with size 0. Non-secure software will send
this NULL address if the SMC call doesn't need to pass any address buffer.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I7e492c562a311ba989570c4ed465f845333ec865

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Merge changes from topic "paulliu-imx8m-eventlog" into integration

* changes:
docs(imx8m): update for measured boot for imx8mm
feat(plat/imx/imx8m/imx8mm): add support for measured boot

fix(intel): assert if bl_mem_params is NULL pointer

This patch fixes the code issue detected by Klocwork scan. Pointer
'bl_mem_params' returned from call to function 'get_bl_mem_params_node'
may be

fix(intel): assert if bl_mem_params is NULL pointer

This patch fixes the code issue detected by Klocwork scan. Pointer
'bl_mem_params' returned from call to function 'get_bl_mem_params_node'
may be NULL and the NULL pointer may be caused the system crash. Update
the code to assert if unexpected NULL pointer is returned.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Change-Id: I00f3132a6104618cadce26aa303c0b46b5921d5b

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fix(intel): enable HPS QSPI access by default

Request ownership and direct access to QSPI by default in BL2.
Previously, this is only done on QSPI boot mode.

Signed-off-by: Abdul Halim, Muhammad Ha

fix(intel): enable HPS QSPI access by default

Request ownership and direct access to QSPI by default in BL2.
Previously, this is only done on QSPI boot mode.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie222bbf9d719f2f70f89d4739c285efe6df4c955

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fix(lx2): drop erratum A-009810

The erratum A-009810 should not be applied to LX2, the impaction is
that it can cause system reboot when linux tried to power down, so remove
it.

Signed-off-by: Yang

fix(lx2): drop erratum A-009810

The erratum A-009810 should not be applied to LX2, the impaction is
that it can cause system reboot when linux tried to power down, so remove
it.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5e24229cf8512eff28b315ebcdf18de555c40c74

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Merge changes from topic "ls1046a" into integration

* changes:
docs(layerscape): add ls1046a soc and board support
feat(ls1046aqds): add board ls1046aqds support
feat(ls1046afrwy): add ls1046a

Merge changes from topic "ls1046a" into integration

* changes:
docs(layerscape): add ls1046a soc and board support
feat(ls1046aqds): add board ls1046aqds support
feat(ls1046afrwy): add ls1046afrwy board support
feat(ls1046ardb): add ls1046ardb board support
feat(ls1046a): add new SoC platform ls1046a
fix(nxp-tools): fix tool location path for byte_swape
fix(nxp-qspi): fix include path for QSPI driver
build(changelog): add new scopes for NXP layerscape platforms

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Merge "fix(fvp): extend memory map to include all DRAM memory regions" into integration

Merge changes from topic "st-format-signedness" into integration

* changes:
feat(stm32mp1): enable format-signedness warning
fix(stm32mp1): correct types in messages
fix(st-pmic): correct verb

Merge changes from topic "st-format-signedness" into integration

* changes:
feat(stm32mp1): enable format-signedness warning
fix(stm32mp1): correct types in messages
fix(st-pmic): correct verbose message
fix(st-sdmmc2): correct cmd_idx type in messages
fix(st-fmc): fix type in message
fix(mtd): correct types in messages
fix(usb): correct type in message
fix(tzc400): correct message with filter
fix(psci): correct parent_node type in messages
fix(libc): correct some messages
fix(fconf): correct image_id type in messages
fix(bl2): correct messages with image_id

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fix(fvp): extend memory map to include all DRAM memory regions

Currently only the lowest 2 DRAM region were configured in the
TrustZone Controller, but the platform supports 6 regions spanning the
w

fix(fvp): extend memory map to include all DRAM memory regions

Currently only the lowest 2 DRAM region were configured in the
TrustZone Controller, but the platform supports 6 regions spanning the
whole address space.
Configuring all of them to allow tests to access memory also in those
higher memory regions.

FVP memory map:
https://developer.arm.com/documentation/100964/1116/Base-Platform/Base---memory/Base-Platform-memory-map
Note that last row is wrong, describing a non-existing 56bit address,
all region labels should be shifted upward.
Issue has been reported and next release will be correct.

Change-Id: I695fe8e24aff67d75e74635ba32a133342289eb4
Signed-off-by: Federico Recanati <federico.recanati@arm.com>

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feat(board/rdedmunds): add support for rdedmunds variant

Add initial support for RD-Edmunds platform. This platform is considered
as a variant of RD-N2 platform with only major change being the CPU

feat(board/rdedmunds): add support for rdedmunds variant

Add initial support for RD-Edmunds platform. This platform is considered
as a variant of RD-N2 platform with only major change being the CPU
which is Demeter instead of Neoverse-N2.

Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I939d9eac652fa9e76ad002ee5e6107aa79baa013

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Merge "refactor(stm32mp1): move PIE flag to SP_min" into integration

feat(stm32mp1): enable format-signedness warning

Add the flag -Wformat-signedness to TF_CFLAGS for STM32MP1.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6af18778902b0a4dae1c08735d

feat(stm32mp1): enable format-signedness warning

Add the flag -Wformat-signedness to TF_CFLAGS for STM32MP1.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6af18778902b0a4dae1c08735d2d070ef3d137ce

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fix(stm32mp1): correct types in messages

Avoid warnings when -Wformat-signedness is enabled.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I0ca41cb96826b4f7f9bcf77909fad110325c1e91

feat(corstone1000): identify bank to load fip

Secure enclave decides the boot bank based on the firmware update
state of the system and updates the boot bank information at a given
location in the f

feat(corstone1000): identify bank to load fip

Secure enclave decides the boot bank based on the firmware update
state of the system and updates the boot bank information at a given
location in the flash. In this commit, bl2 reads the given flash
location to indentify the bank from which it should load fip from.

Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I7f0f4ffc97189c9deb99db44afcd966082ffbf21

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fix(a3k): fix comment about BootROM address range

A53 AP BootROM is just 16 kB long and is mapped to address range
0xFFFF0000-0xFFFF4000. RVBAR_EL3 register has value 0xFFFF0000.
A53 AP BootROM itse

fix(a3k): fix comment about BootROM address range

A53 AP BootROM is just 16 kB long and is mapped to address range
0xFFFF0000-0xFFFF4000. RVBAR_EL3 register has value 0xFFFF0000.
A53 AP BootROM itself is in the BootROM window which is 1 MB long and
mapped to address range 0xFFF00000-0xFFFFFFFF.

CM3 BootROM is not accessible from A53 core.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5d4a4c7b1e7550c4738c67a872d341f945d48bbc

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fix(corstone1000): change base address of FIP in the flash

More space in the flash is reserved up front for metadata
parser and UEFI variables. That requires change in the flash
base address of wher

fix(corstone1000): change base address of FIP in the flash

More space in the flash is reserved up front for metadata
parser and UEFI variables. That requires change in the flash
base address of where images are present.

Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: Ieaabe09374d707de18d36505c69b6c9a8c2ec2e9

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feat(corstone1000): implement platform specific psci reset

This change implements platform specific psci reset
for the corstone1000.

Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Signed-off-by

feat(corstone1000): implement platform specific psci reset

This change implements platform specific psci reset
for the corstone1000.

Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I25f77234506416c3376ff4a028f6ea40ebe68437

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feat(ls1046aqds): add board ls1046aqds support

ls1046aqds board is full function board to evaluate ls1046a platform.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: York Sun <york.sun

feat(ls1046aqds): add board ls1046aqds support

ls1046aqds board is full function board to evaluate ls1046a platform.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Id1befe37a25f7c379e76791538348fd03bba78f7

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feat(ls1046afrwy): add ls1046afrwy board support

The LS1046A Freeway board (FRWY) is a high-performance computing,
evaluation, and development platform that supports the LS1046A
architecture process

feat(ls1046afrwy): add ls1046afrwy board support

The LS1046A Freeway board (FRWY) is a high-performance computing,
evaluation, and development platform that supports the LS1046A
architecture processor capable of support more than 32,000 CoreMark
performance. The FRWY-LS1046A board supports the LS1046A processor,
onboard DDR4 memory, multiple Gigabit Ethernet, USB3.0 and M2_Type_E
interfaces for Wi-Fi, FRWY-LS1046A-AC includes the Wi-Fi card.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9a9680689e6f17bf4cc76fd5d1883eed6ace5149

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feat(ls1046ardb): add ls1046ardb board support

The LS1046A reference design board (RDB) is a high-performance
computing, evaluation, and development platform that supports
the Layerscape LS1046A arc

feat(ls1046ardb): add ls1046ardb board support

The LS1046A reference design board (RDB) is a high-performance
computing, evaluation, and development platform that supports
the Layerscape LS1046A architecture processor.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ib7a01b309e0b0acc7f38e22b138e9e181dff244a

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feat(ls1046a): add new SoC platform ls1046a

The LS1046A is a cost-effective, power-efficient, and highly
integrated system-on-chip (SoC) design that extends the reach
of the NXP value-performance li

feat(ls1046a): add new SoC platform ls1046a

The LS1046A is a cost-effective, power-efficient, and highly
integrated system-on-chip (SoC) design that extends the reach
of the NXP value-performance line of QorIQ communications
processors. Featuring power-efficient 64-bit Arm Cortex A72
cores with ECC-protected L1 and L2 cache memories for high
reliability, running up to 1.8 GHz.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Change-Id: I208d9bf1702410463c2b2630d31d0cd4eb7e8837

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feat(corstone1000): made changes to accommodate 3MB for optee

These changes are required to accommodate 3MB for OP-TEE and this
is required for SP's part of optee
Added size macro's for better reada

feat(corstone1000): made changes to accommodate 3MB for optee

These changes are required to accommodate 3MB for OP-TEE and this
is required for SP's part of optee
Added size macro's for better readability of the code
Moved uboot execution memory from CVM to DDR

Change-Id: I16657c6e336fe7c0fffdee1617d10af8a2c76732
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>

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build(corstone1000): rename diphda to corstone1000

diphda platform is now being renamed to corstone1000.
These changes are to replace all the instances and traces
of diphda corstone1000.

Change-Id

build(corstone1000): rename diphda to corstone1000

diphda platform is now being renamed to corstone1000.
These changes are to replace all the instances and traces
of diphda corstone1000.

Change-Id: I330f3a112d232b99b4721b6bf0236253b068dbba
Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

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feat(plat/imx/imx8m/imx8mm): add support for measured boot

Add helper functions to generate event log for imx8mm
when MEASURED_BOOT=1.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Ch

feat(plat/imx/imx8m/imx8mm): add support for measured boot

Add helper functions to generate event log for imx8mm
when MEASURED_BOOT=1.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: Ifc947d749055787fbda0b39170aa2eb8865b7802

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