1 /* 2 * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2021, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/generic_delay_timer.h> 14 #include <drivers/synopsys/dw_mmc.h> 15 #include <drivers/ti/uart/uart_16550.h> 16 #include <lib/xlat_tables/xlat_tables.h> 17 18 #include "agilex_mmc.h" 19 #include "agilex_clock_manager.h" 20 #include "agilex_memory_controller.h" 21 #include "agilex_pinmux.h" 22 #include "ccu/ncore_ccu.h" 23 #include "qspi/cadence_qspi.h" 24 #include "socfpga_emac.h" 25 #include "socfpga_handoff.h" 26 #include "socfpga_mailbox.h" 27 #include "socfpga_private.h" 28 #include "socfpga_reset_manager.h" 29 #include "socfpga_system_manager.h" 30 #include "wdt/watchdog.h" 31 32 static struct mmc_device_info mmc_info; 33 34 const mmap_region_t agilex_plat_mmap[] = { 35 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 36 MT_MEMORY | MT_RW | MT_NS), 37 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 38 MT_DEVICE | MT_RW | MT_NS), 39 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 40 MT_DEVICE | MT_RW | MT_SECURE), 41 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 42 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 43 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 44 MT_DEVICE | MT_RW | MT_SECURE), 45 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 46 MT_DEVICE | MT_RW | MT_NS), 47 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 48 MT_DEVICE | MT_RW | MT_NS), 49 {0}, 50 }; 51 52 boot_source_type boot_source = BOOT_SOURCE; 53 54 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 55 u_register_t x2, u_register_t x4) 56 { 57 static console_t console; 58 handoff reverse_handoff_ptr; 59 60 generic_delay_timer_init(); 61 62 if (socfpga_get_handoff(&reverse_handoff_ptr)) 63 return; 64 config_pinmux(&reverse_handoff_ptr); 65 config_clkmgr_handoff(&reverse_handoff_ptr); 66 67 enable_nonsecure_access(); 68 deassert_peripheral_reset(); 69 config_hps_hs_before_warm_reset(); 70 71 watchdog_init(get_wdt_clk()); 72 73 console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, 74 &console); 75 76 socfpga_delay_timer_init(); 77 init_ncore_ccu(); 78 socfpga_emac_init(); 79 init_hard_memory_controller(); 80 mailbox_init(); 81 agx_mmc_init(); 82 83 if (!intel_mailbox_is_fpga_not_ready()) 84 socfpga_bridges_enable(); 85 } 86 87 88 void bl2_el3_plat_arch_setup(void) 89 { 90 91 const mmap_region_t bl_regions[] = { 92 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, 93 MT_MEMORY | MT_RW | MT_SECURE), 94 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 95 MT_CODE | MT_SECURE), 96 MAP_REGION_FLAT(BL_RO_DATA_BASE, 97 BL_RO_DATA_END - BL_RO_DATA_BASE, 98 MT_RO_DATA | MT_SECURE), 99 #if USE_COHERENT_MEM_BAR 100 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 101 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 102 MT_DEVICE | MT_RW | MT_SECURE), 103 #endif 104 {0}, 105 }; 106 107 setup_page_tables(bl_regions, agilex_plat_mmap); 108 109 enable_mmu_el3(0); 110 111 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); 112 113 mmc_info.mmc_dev_type = MMC_IS_SD; 114 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 115 116 /* Request ownership and direct access to QSPI */ 117 mailbox_hps_qspi_enable(); 118 119 switch (boot_source) { 120 case BOOT_SOURCE_SDMMC: 121 dw_mmc_init(¶ms, &mmc_info); 122 socfpga_io_setup(boot_source); 123 break; 124 125 case BOOT_SOURCE_QSPI: 126 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 127 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 128 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 129 socfpga_io_setup(boot_source); 130 break; 131 132 default: 133 ERROR("Unsupported boot source\n"); 134 panic(); 135 break; 136 } 137 } 138 139 uint32_t get_spsr_for_bl33_entry(void) 140 { 141 unsigned long el_status; 142 unsigned int mode; 143 uint32_t spsr; 144 145 /* Figure out what mode we enter the non-secure world in */ 146 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 147 el_status &= ID_AA64PFR0_ELX_MASK; 148 149 mode = (el_status) ? MODE_EL2 : MODE_EL1; 150 151 /* 152 * TODO: Consider the possibility of specifying the SPSR in 153 * the FIP ToC and allowing the platform to have a say as 154 * well. 155 */ 156 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 157 return spsr; 158 } 159 160 161 int bl2_plat_handle_post_image_load(unsigned int image_id) 162 { 163 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 164 165 switch (image_id) { 166 case BL33_IMAGE_ID: 167 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 168 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 169 break; 170 default: 171 break; 172 } 173 174 return 0; 175 } 176 177 /******************************************************************************* 178 * Perform any BL3-1 platform setup code 179 ******************************************************************************/ 180 void bl2_platform_setup(void) 181 { 182 } 183 184