Merge changes from topic "rustspmc_with_xferlist" into integration

* changes:
feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm
feat(fvp): update evtlog info in the xferlist's DT_SP

Merge changes from topic "rustspmc_with_xferlist" into integration

* changes:
feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm
feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry
feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition
feat(spmd): get spmc manifest from xferlist

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feat(tc): bump SPMC version to FF-A v1.3 TC platform

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I196a0eb1bedb8bcc35b4524f04ea75f8c832a7f9

feat(fvp): bump the SPMC version

Bump the SPMC version in the fvp_spmc_optee_sp_manifest
to FF-A v1.3. The affected setup uses Hafnium as SPMC and
OPTEE as SP.

Signed-off-by: J-Alves <joao.alves@ar

feat(fvp): bump the SPMC version

Bump the SPMC version in the fvp_spmc_optee_sp_manifest
to FF-A v1.3. The affected setup uses Hafnium as SPMC and
OPTEE as SP.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I51d29832d8011dbdc9945f153805ba9b2b8663e7

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Merge "fix(spm): change the SMMUv3TestEngine being used" into integration

Merge changes from topic "bk/no_blx_setup" into integration

* changes:
fix: replace stray BL2_AT_EL3 with RESET_TO_BL2
refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint
re

Merge changes from topic "bk/no_blx_setup" into integration

* changes:
fix: replace stray BL2_AT_EL3 with RESET_TO_BL2
refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint
refactor: unify blx_setup() and blx_main()
fix(bl2): unify the BL2 EL3 and RME entrypoints

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feat(ff-a): bump SPMD FF-A version

The Hafnium SPM version bumped to FF-A v1.3, alongside
the TF-A SPMD.
EL3 SPMC was kept under the v1.2 version with its own
set of FFA_VERSION_SPMC_MAJOR/MINOR mac

feat(ff-a): bump SPMD FF-A version

The Hafnium SPM version bumped to FF-A v1.3, alongside
the TF-A SPMD.
EL3 SPMC was kept under the v1.2 version with its own
set of FFA_VERSION_SPMC_MAJOR/MINOR macros.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I0494738b9978ad72b3316a24d7811096c53f952b

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feat(qemu): skip paged image info

In qemu_bl2_handle_post_image_load() when fixing up the arguments for
BL32, only pass on paged image base and size if it has been loaded. The
paged image is not sup

feat(qemu): skip paged image info

In qemu_bl2_handle_post_image_load() when fixing up the arguments for
BL32, only pass on paged image base and size if it has been loaded. The
paged image is not supported for SPMC_OPTEE so make sure it's not
loaded.

Change-Id: I9c82ef687006e0f882a098de2cc3000038476b17
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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feat(qemu-sbsa): support s-el2 and s-el1 spmc

Reserve memory for TB_FW_CONFIG and TOS_FW_CONFIG if configured with
SPD=spmd and optionally SPMD_SPM_AT_SEL2=1.

Change-Id: I2f27502b6d5f9f0131ab8ba273

feat(qemu-sbsa): support s-el2 and s-el1 spmc

Reserve memory for TB_FW_CONFIG and TOS_FW_CONFIG if configured with
SPD=spmd and optionally SPMD_SPM_AT_SEL2=1.

Change-Id: I2f27502b6d5f9f0131ab8ba273ab738de5643d45
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Merge changes Ibc52a4fc,Ieb56af33 into integration

* changes:
build(allwinner): disable unneeded CVE workarounds and MPAM
fix(cpus): use correct Makefile indentation for CVE-2018-3639 check

feat(ti): am62lx init: boot notif and version msg

Consume the boot notification on this platform before we start further
communication with the system-firmware.

Change-Id: Ia9e5d8d616d7d9cd50ee5de2

feat(ti): am62lx init: boot notif and version msg

Consume the boot notification on this platform before we start further
communication with the system-firmware.

Change-Id: Ia9e5d8d616d7d9cd50ee5de2e4c8abe06104dc05
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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feat(ti): add mmu regions for am62l soc

Update the k3low bl31 platform setup to map required device regions
(USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all
necessary hardware b

feat(ti): add mmu regions for am62l soc

Update the k3low bl31 platform setup to map required device regions
(USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all
necessary hardware blocks are accessible to the A53 cores on the
AM62L SoC.
Use 4K aligned address sizes wherever applicable, and update the
file header comment from "K3 SOC specific bl31_setup" to "k3low SoC
specific bl31_setup" to accurately represent the platform specific
nature of this file.
As part of the effort, rename WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE
to WKUP_CTRL_MMR0_BASE to make name shorter.

Change-Id: I58209bc9c780db3e452b09c2c939bb0c47a63ed1
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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feat(ti): build generic timer

Also, make sure we init the generic timer as part of the soc init
on am62lx as we use it later for delays

Change-Id: I921f4e4120ddaba588eb5b876231435fff3f7f3c
Signed-o

feat(ti): build generic timer

Also, make sure we init the generic timer as part of the soc init
on am62lx as we use it later for delays

Change-Id: I921f4e4120ddaba588eb5b876231435fff3f7f3c
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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Merge changes I32c5be5d,I15a652a0 into integration

* changes:
fix(qemu): add reason parameter to MEC update
refactor(rmmd): modify MEC update call to meet FIRME

fix(spm): change the SMMUv3TestEngine being used

Use a test engine that's not connected via PCIe as those can't make
Secure accesses.

Change-Id: I6f7f235d022090189782381bc88e67de64c11927
Signed-off

fix(spm): change the SMMUv3TestEngine being used

Use a test engine that's not connected via PCIe as those can't make
Secure accesses.

Change-Id: I6f7f235d022090189782381bc88e67de64c11927
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(qemu): add reason parameter to MEC update

The FIRME MFI_MEC_REFRESH call takes a reason parameter. Add it to the
QEMU callback for compatibility.

Change-Id: I32c5be5dbce44102650f9312c44e1d00a31

fix(qemu): add reason parameter to MEC update

The FIRME MFI_MEC_REFRESH call takes a reason parameter. Add it to the
QEMU callback for compatibility.

Change-Id: I32c5be5dbce44102650f9312c44e1d00a3146eb9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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refactor(rmmd): modify MEC update call to meet FIRME

Previous version of MEC refresh call was not compliant with FIRME [1].
This patch modifies the call so it is compliant with the specification.

[

refactor(rmmd): modify MEC update call to meet FIRME

Previous version of MEC refresh call was not compliant with FIRME [1].
This patch modifies the call so it is compliant with the specification.

[1] https://developer.arm.com/documentation/den0149/1-0alp0/

Change-Id: I15a652a021561edca16e79d127e6f08975cf1361
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge "fix(rcar4): drop unused plat_pm_scmi" into integration

build(allwinner): disable unneeded CVE workarounds and MPAM

There are a number of workarounds for CVEs related to sidechannel
attacks on some CPU cores, most of them listed here:
https://developer.a

build(allwinner): disable unneeded CVE workarounds and MPAM

There are a number of workarounds for CVEs related to sidechannel
attacks on some CPU cores, most of them listed here:
https://developer.arm.com/documentation/110280/latest/
Also there are two other CVEs:
https://developer.arm.com/documentation/110324/latest/
https://developer.arm.com/documentation/110326/latest/

As these page reveals, those workaround do not apply to the Cortex-A53
(or A55) cores, so we can safely disable them in the Allwinner build
recipes, since they only use those two cores so far.

Also disable FEAT_MPAM, which is one of the only three later features
that are enabled default, but are not enabled in Cortex-A53 or A55
cores. Use the opportunity to group those options together and improve
the comment.

This decreases the code size by a few hundred bytes.

Change-Id: Ibc52a4fc9b8f5d9b2b28a2ce13d3ab99b63e9640
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "feat(versal2): remove handoff entry from tl" into integration

fix(rcar4): drop unused plat_pm_scmi

Drop unused plat_pm_scmi.c and related platform.mk entries.
If this is ever going to be used, this can be reinstated.

Signed-off-by: Marek Vasut <marek.vasut+re

fix(rcar4): drop unused plat_pm_scmi

Drop unused plat_pm_scmi.c and related platform.mk entries.
If this is ever going to be used, this can be reinstated.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Icdb5188cba97be5dfccb240f773288a54662e977

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fix: replace stray BL2_AT_EL3 with RESET_TO_BL2

For FVP, patch 259b67c08 should have used the latter but introduced the
former. That was a mistake, correct it.

The nuvoton platform seems to have co

fix: replace stray BL2_AT_EL3 with RESET_TO_BL2

For FVP, patch 259b67c08 should have used the latter but introduced the
former. That was a mistake, correct it.

The nuvoton platform seems to have copied arm_def.h and would have been
missed at some point. Update that too.

Change-Id: I28123186bb4b69c5d5154dcdd24e5dee9d9e33b8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm

fvp_stmm_l2_sp_list.dts is used to load StandaloneMm with rust-spmc.

This sp information will be included into fvp_tb_fw_config.dts
by

feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm

fvp_stmm_l2_sp_list.dts is used to load StandaloneMm with rust-spmc.

This sp information will be included into fvp_tb_fw_config.dts
by specifying ARM_BL2_SP_LIST_DTS build option with this file.

Change-Id: I42b1ed9a04ac29b1a3c31f7267b337d4e3036c10
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry

For compatibility with SPMCs that obtain
event log information from DT_SPMC_MANIFEST,
ensure the event log is updated when TF-A

feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry

For compatibility with SPMCs that obtain
event log information from DT_SPMC_MANIFEST,
ensure the event log is updated when TF-A uses firmware handoff.

Change-Id: Iafc11c63c86c2ee67481e3085d2e8390d5f99cea
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition

PLAT_ARM_SPMC_SP_MANIFEST_SIZE is used to allocate transfer entry
when TF-A is built with TRANSFER_LIST to pass:
- StandaloneMm manifest w

feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition

PLAT_ARM_SPMC_SP_MANIFEST_SIZE is used to allocate transfer entry
when TF-A is built with TRANSFER_LIST to pass:
- StandaloneMm manifest with TL_TAG_DT_FFA_MANIFEST tag
in case of SPMC_AT_EL3

- SPMC manifest (i.e) rust-spmc.

Therefore, move the PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition
under the TRNASFER_LIST & SPD_spmd condition and increase
the size of TRANSFER_LIST as much as PLAT_ARM_SPMC_SP_MANIFEST_SIZE

Change-Id: If5e4c184fcf3aa683554f6d49caf78a5f6bfc2d1
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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Merge "fix(xilinx): typecast operands to match data type" into integration