Merge "feat(rss): add TC platform UUIDs for RSS images" into integration

Merge changes from topic "feat_state_rework" into integration

* changes:
feat(fvp): enable FEAT_HCX by default
refactor(context-mgmt): move FEAT_HCX save/restore into C
refactor(cpufeat): conv

Merge changes from topic "feat_state_rework" into integration

* changes:
feat(fvp): enable FEAT_HCX by default
refactor(context-mgmt): move FEAT_HCX save/restore into C
refactor(cpufeat): convert FEAT_HCX to new scheme
feat(fvp): enable FEAT_FGT by default
refactor(context-mgmt): move FEAT_FGT save/restore code into C
refactor(amu): convert FEAT_AMUv1 to new scheme
refactor(cpufeat): decouple FGT feature detection and build flags
refactor(cpufeat): check FEAT_FGT in a new way
refactor(cpufeat): move helpers into .c file, rename FEAT_STATE_
feat(aarch64): make ID system register reads non-volatile

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Merge "fix(plat/css): fix invalid redistributor poweroff" into integration

fix(plat/css): fix invalid redistributor poweroff

Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf
introduced an invalid redistributor power off
where we turn off the redistributor without
checking i

fix(plat/css): fix invalid redistributor poweroff

Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf
introduced an invalid redistributor power off
where we turn off the redistributor without
checking if the system power domain level is
turning off, otherwise we can turn off a
redistributor when other cores or clusters are
sharing it, also if it does indeed needs
powering off during suspend we do it twice.
This change fixes this by checking on the
system power state first then turning off
the redistributor.

Signed-off-by: Waleed Elmelegy <waleed.elmelegy@arm.com>
Change-Id: Id202bc2316ab7c516298fa33ea089ae2e221a933

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Merge "fix(zynqmp): fix xck24 silicon ID" into integration

Merge changes from topic "mtk_spm" into integration

* changes:
refactor(mediatek): add new LPM API for further extension
refactor(mediatek): change the parameters of LPM API
refactor(mediatek)

Merge changes from topic "mtk_spm" into integration

* changes:
refactor(mediatek): add new LPM API for further extension
refactor(mediatek): change the parameters of LPM API
refactor(mediatek): change LPM header file path for further extension
feat(mt8188): keep infra and peri on when system suspend
feat(mt8188): enable SPM and LPM
feat(mt8188): add SPM feature support
feat(mt8188): add MT8188 SPM support
feat(mediatek): add SPM's SSPM notifier
feat(mt8188): add the register definitions accessed by SPM
feat(mediatek): add new features of LPM

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fix(zynqmp): fix xck24 silicon ID

Origin ID code has changed from origin description. After receiving part
new ID code come up that's why fix it. The origin ID code has been added
by commit 86869f99

fix(zynqmp): fix xck24 silicon ID

Origin ID code has changed from origin description. After receiving part
new ID code come up that's why fix it. The origin ID code has been added
by commit 86869f99d0c1 ("feat(zynqmp): add support for xck24 silicon").

Change-Id: I727bfe43fd7ef9e604f63bde5fa37fa3666db8c4
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(rme): set DRAM information in Boot Manifest platform data

This patch adds support for setting configuration of DRAM banks
for FVP model in RMM-EL3 Boot Manifest structure.
Structure 'rmm_manife

feat(rme): set DRAM information in Boot Manifest platform data

This patch adds support for setting configuration of DRAM banks
for FVP model in RMM-EL3 Boot Manifest structure.
Structure 'rmm_manifest' is extended with 'plat_dram' structure
which contains information about platform's DRAM layout:
- number of DRAM banks;
- pointer to 'dram_bank[]' array;
- check sum: two's complement 64-bit value of the sum of
data in 'plat_dram' and 'dram_bank[] array.
Each 'dram_bank' structure holds information about DRAM
bank base address and its size. This values must be aligned
to 4KB page size.
The patch increases Boot Manifest minor version to 2 and
removes 'typedef rmm_manifest_t' as per
"3.4.15.1. Avoid anonymous typedefs of structs/enums in headers" of
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I5176caa5780e27d1e0daeb5dea3e40cf6ad5fd12

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Merge changes from topic "ti-k3-checks-and-refactor" into integration

* changes:
fix(ti): fix typo in boot authentication message name
refactor(ti): remove empty validate_ns_entrypoint function

Merge changes from topic "ti-k3-checks-and-refactor" into integration

* changes:
fix(ti): fix typo in boot authentication message name
refactor(ti): remove empty validate_ns_entrypoint function
refactor(ti): use console_set_scope() rather than empty function hack
refactor(ti): factor out common board code into common files
feat(ti): add PSCI system_off support
feat(ti): do not handle EAs in EL3
feat(ti): set snoop-delayed exclusive handling on A72 cores
feat(ti): disable L2 dataless UniqueClean evictions
feat(ti): set L2 cache ECC and and parity on A72 cores
feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles

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Merge changes from topic "deprecate_io_drivers" into integration

* changes:
refactor(st): remove unused io_mmc driver
docs: deprecate io_dummy driver

Merge changes from topic "refactor_st_common" into integration

* changes:
refactor(st): move board info in common code
refactor(st): move GIC code to common directory
refactor(st): move boot b

Merge changes from topic "refactor_st_common" into integration

* changes:
refactor(st): move board info in common code
refactor(st): move GIC code to common directory
refactor(st): move boot backup register management

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feat(versal-net): add support for uart1 console

Versal NET platform supports two UART(UART0, UART1)
Add support for UART1 to be used as console for Versal NET platform.

Change-Id: I3bc2034f54052e37

feat(versal-net): add support for uart1 console

Versal NET platform supports two UART(UART0, UART1)
Add support for UART1 to be used as console for Versal NET platform.

Change-Id: I3bc2034f54052e37cc480f98d48335fa5b2138bf
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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fix(ti): fix typo in boot authentication message name

Fix AUTH_BOOT message identifier (s/IMIAGE/IMAGE).

Reported-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Andrew Davis <afd@ti.co

fix(ti): fix typo in boot authentication message name

Fix AUTH_BOOT message identifier (s/IMIAGE/IMAGE).

Reported-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I19eb1798c6b9dd8c3f59e05c59318c9c3be971a0

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refactor(ti): remove empty validate_ns_entrypoint function

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I93165e9f26f5a5b600e7b6a9d48df75d62e89f17

refactor(ti): use console_set_scope() rather than empty function hack

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I62c1215bc02e95a7ea9fa1e2dfa9ef05e204fce1

refactor(ti): factor out common board code into common files

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ibf7328418c5285a64608b80e7c430a8dee64fb1d

feat(ti): add PSCI system_off support

Send a TI-SCI control message to system firmware to power down the board.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I6b8fa64baa94da078db82fc8e115630c

feat(ti): add PSCI system_off support

Send a TI-SCI control message to system firmware to power down the board.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I6b8fa64baa94da078db82fc8e115630c9f200b3d

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feat(ti): do not handle EAs in EL3

This could be useful if we had extra information to print or
when RAS extensions are available, neither apply here so lets
not trap these in EL3 for now.

Signed-o

feat(ti): do not handle EAs in EL3

This could be useful if we had extra information to print or
when RAS extensions are available, neither apply here so lets
not trap these in EL3 for now.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ia0334eb845686964e794afe45c7777ea64fd6b0b

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feat(ti): set snoop-delayed exclusive handling on A72 cores

Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by

feat(ti): set snoop-delayed exclusive handling on A72 cores

Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by the
core's SCU delaying to check for the corresponding atomic monitor state.

TI SoCs take the second approach. Set the snoop-delayed exclusive handling
bit to inform the core it needs to delay responses to perform this check.

As J784s4 is currently the only SoC with multiple A72 clusters, limit
this delay to only that device.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I875f64e4f53d47a9a0ccbf3415edc565be7f84d9

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feat(ti): disable L2 dataless UniqueClean evictions

Do this early before we enable caching as a workaround for ARM A72
Errata #854172.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ic878fdb49

feat(ti): disable L2 dataless UniqueClean evictions

Do this early before we enable caching as a workaround for ARM A72
Errata #854172.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ic878fdb49e598da0ea6ade012712f8f57023678e

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feat(ti): set L2 cache ECC and and parity on A72 cores

The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.

Signed-off-by: Andrew Davis <afd@ti.com>
Change

feat(ti): set L2 cache ECC and and parity on A72 cores

The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Icd00bc4aa9c1c48f0fb2a10ea66e75e0b146ef3c

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feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles

The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 acce

feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles

The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883

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feat(rdn2): add platform id value for rdn2 variant 3

The RD-N2-Cfg3 platform is a variant of the RD-N2 platform with the
significant difference being the number of ITS blocks and the use of a
differ

feat(rdn2): add platform id value for rdn2 variant 3

The RD-N2-Cfg3 platform is a variant of the RD-N2 platform with the
significant difference being the number of ITS blocks and the use of a
different part number.

Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: Id4c5faeae44f21da79cb59540558192d0b02b124

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refactor(rdn2): reduce use of CSS_SGI_PLATFORM_VARIANT build flag

The core count is one of the significant difference between the various
RD-N2 platform variants. The PLAT_ARM_CLUSTER_COUNT macro de

refactor(rdn2): reduce use of CSS_SGI_PLATFORM_VARIANT build flag

The core count is one of the significant difference between the various
RD-N2 platform variants. The PLAT_ARM_CLUSTER_COUNT macro defines the
number of core/cluster for a variant. In preparation to add another
variant of RD-N2 platform, replace the use of CSS_SGI_PLATFORM_VARIANT
build flag, where applicable, with the PLAT_ARM_CLUSTER_COUNT macro.
This helps to reduce the changes required to add support for a new
variant.

Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I89b168308d1b5f7edd402205dd25d6c3a355e100

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Merge changes from topic "fix-power-up-dwn-issue" into integration

* changes:
fix(versal-net): enable wake interrupt during client suspend
fix(versal-net): disable wakeup interrupt during client

Merge changes from topic "fix-power-up-dwn-issue" into integration

* changes:
fix(versal-net): enable wake interrupt during client suspend
fix(versal-net): disable wakeup interrupt during client wakeup
fix(versal-net): clear power down bit during wakeup
fix(versal-net): fix setting power down state
fix(versal-net): clear power down interrupt status before enable
fix(versal-net): resolve misra rule 20.7 warnings
fix(versal-net): resolve misra 10.6 warnings

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