1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/partition/partition.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #include <lib/gpt_rme/gpt_rme.h> 22 #ifdef SPD_opteed 23 #include <lib/optee_utils.h> 24 #endif 25 #include <lib/utils.h> 26 #include <plat/arm/common/arm_pas_def.h> 27 #include <plat/arm/common/plat_arm.h> 28 #include <plat/common/platform.h> 29 30 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 31 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 32 33 /* Base address of fw_config received from BL1 */ 34 static uintptr_t config_base; 35 36 /* 37 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 38 * for `meminfo_t` data structure and fw_configs passed from BL1. 39 */ 40 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 41 42 /* Weak definitions may be overridden in specific ARM standard platform */ 43 #pragma weak bl2_early_platform_setup2 44 #pragma weak bl2_platform_setup 45 #pragma weak bl2_plat_arch_setup 46 #pragma weak bl2_plat_sec_mem_layout 47 48 #if ENABLE_RME 49 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 50 bl2_tzram_layout.total_base, \ 51 bl2_tzram_layout.total_size, \ 52 MT_MEMORY | MT_RW | MT_ROOT) 53 #else 54 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 55 bl2_tzram_layout.total_base, \ 56 bl2_tzram_layout.total_size, \ 57 MT_MEMORY | MT_RW | MT_SECURE) 58 #endif /* ENABLE_RME */ 59 60 #pragma weak arm_bl2_plat_handle_post_image_load 61 62 /******************************************************************************* 63 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 64 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 65 * Copy it to a safe location before its reclaimed by later BL2 functionality. 66 ******************************************************************************/ 67 void arm_bl2_early_platform_setup(uintptr_t fw_config, 68 struct meminfo *mem_layout) 69 { 70 /* Initialize the console to provide early debug support */ 71 arm_console_boot_init(); 72 73 /* Setup the BL2 memory layout */ 74 bl2_tzram_layout = *mem_layout; 75 76 config_base = fw_config; 77 78 /* Initialise the IO layer and register platform IO devices */ 79 plat_arm_io_setup(); 80 81 /* Load partition table */ 82 #if ARM_GPT_SUPPORT 83 partition_init(GPT_IMAGE_ID); 84 #endif /* ARM_GPT_SUPPORT */ 85 86 } 87 88 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 89 { 90 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 91 92 generic_delay_timer_init(); 93 } 94 95 /* 96 * Perform BL2 preload setup. Currently we initialise the dynamic 97 * configuration here. 98 */ 99 void bl2_plat_preload_setup(void) 100 { 101 arm_bl2_dyn_cfg_init(); 102 103 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT 104 /* Always use the FIP from bank 0 */ 105 arm_set_fip_addr(0U); 106 #endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */ 107 } 108 109 /* 110 * Perform ARM standard platform setup. 111 */ 112 void arm_bl2_platform_setup(void) 113 { 114 #if !ENABLE_RME 115 /* Initialize the secure environment */ 116 plat_arm_security_setup(); 117 #endif 118 119 #if defined(PLAT_ARM_MEM_PROT_ADDR) 120 arm_nor_psci_do_static_mem_protect(); 121 #endif 122 } 123 124 void bl2_platform_setup(void) 125 { 126 arm_bl2_platform_setup(); 127 } 128 129 #if ENABLE_RME 130 131 static void arm_bl2_plat_gpt_setup(void) 132 { 133 /* 134 * The GPT library might modify the gpt regions structure to optimize 135 * the layout, so the array cannot be constant. 136 */ 137 pas_region_t pas_regions[] = { 138 ARM_PAS_KERNEL, 139 ARM_PAS_SECURE, 140 ARM_PAS_REALM, 141 ARM_PAS_EL3_DRAM, 142 ARM_PAS_GPTS, 143 ARM_PAS_KERNEL_1 144 }; 145 146 /* Initialize entire protected space to GPT_GPI_ANY. */ 147 if (gpt_init_l0_tables(GPCCR_PPS_64GB, ARM_L0_GPT_ADDR_BASE, 148 ARM_L0_GPT_SIZE) < 0) { 149 ERROR("gpt_init_l0_tables() failed!\n"); 150 panic(); 151 } 152 153 /* Carve out defined PAS ranges. */ 154 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K, 155 ARM_L1_GPT_ADDR_BASE, 156 ARM_L1_GPT_SIZE, 157 pas_regions, 158 (unsigned int)(sizeof(pas_regions) / 159 sizeof(pas_region_t))) < 0) { 160 ERROR("gpt_init_pas_l1_tables() failed!\n"); 161 panic(); 162 } 163 164 INFO("Enabling Granule Protection Checks\n"); 165 if (gpt_enable() < 0) { 166 ERROR("gpt_enable() failed!\n"); 167 panic(); 168 } 169 } 170 171 #endif /* ENABLE_RME */ 172 173 /******************************************************************************* 174 * Perform the very early platform specific architectural setup here. 175 * When RME is enabled the secure environment is initialised before 176 * initialising and enabling Granule Protection. 177 * This function initialises the MMU in a quick and dirty way. 178 ******************************************************************************/ 179 void arm_bl2_plat_arch_setup(void) 180 { 181 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 182 /* 183 * Ensure ARM platforms don't use coherent memory in BL2 unless 184 * cryptocell integration is enabled. 185 */ 186 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 187 #endif 188 189 const mmap_region_t bl_regions[] = { 190 MAP_BL2_TOTAL, 191 ARM_MAP_BL_RO, 192 #if USE_ROMLIB 193 ARM_MAP_ROMLIB_CODE, 194 ARM_MAP_ROMLIB_DATA, 195 #endif 196 #if ARM_CRYPTOCELL_INTEG 197 ARM_MAP_BL_COHERENT_RAM, 198 #endif 199 ARM_MAP_BL_CONFIG_REGION, 200 #if ENABLE_RME 201 ARM_MAP_L0_GPT_REGION, 202 #endif 203 {0} 204 }; 205 206 #if ENABLE_RME 207 /* Initialise the secure environment */ 208 plat_arm_security_setup(); 209 #endif 210 setup_page_tables(bl_regions, plat_arm_get_mmap()); 211 212 #ifdef __aarch64__ 213 #if ENABLE_RME 214 /* BL2 runs in EL3 when RME enabled. */ 215 assert(get_armv9_2_feat_rme_support() != 0U); 216 enable_mmu_el3(0); 217 218 /* Initialise and enable granule protection after MMU. */ 219 arm_bl2_plat_gpt_setup(); 220 #else 221 enable_mmu_el1(0); 222 #endif 223 #else 224 enable_mmu_svc_mon(0); 225 #endif 226 227 arm_setup_romlib(); 228 } 229 230 void bl2_plat_arch_setup(void) 231 { 232 const struct dyn_cfg_dtb_info_t *tb_fw_config_info; 233 234 arm_bl2_plat_arch_setup(); 235 236 /* Fill the properties struct with the info from the config dtb */ 237 fconf_populate("FW_CONFIG", config_base); 238 239 /* TB_FW_CONFIG was also loaded by BL1 */ 240 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 241 assert(tb_fw_config_info != NULL); 242 243 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 244 } 245 246 int arm_bl2_handle_post_image_load(unsigned int image_id) 247 { 248 int err = 0; 249 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 250 #ifdef SPD_opteed 251 bl_mem_params_node_t *pager_mem_params = NULL; 252 bl_mem_params_node_t *paged_mem_params = NULL; 253 #endif 254 assert(bl_mem_params != NULL); 255 256 switch (image_id) { 257 #ifdef __aarch64__ 258 case BL32_IMAGE_ID: 259 #ifdef SPD_opteed 260 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 261 assert(pager_mem_params); 262 263 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 264 assert(paged_mem_params); 265 266 err = parse_optee_header(&bl_mem_params->ep_info, 267 &pager_mem_params->image_info, 268 &paged_mem_params->image_info); 269 if (err != 0) { 270 WARN("OPTEE header parse error.\n"); 271 } 272 #endif 273 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 274 break; 275 #endif 276 277 case BL33_IMAGE_ID: 278 /* BL33 expects to receive the primary CPU MPID (through r0) */ 279 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 280 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 281 break; 282 283 #ifdef SCP_BL2_BASE 284 case SCP_BL2_IMAGE_ID: 285 /* The subsequent handling of SCP_BL2 is platform specific */ 286 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 287 if (err) { 288 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 289 } 290 break; 291 #endif 292 default: 293 /* Do nothing in default case */ 294 break; 295 } 296 297 return err; 298 } 299 300 /******************************************************************************* 301 * This function can be used by the platforms to update/use image 302 * information for given `image_id`. 303 ******************************************************************************/ 304 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 305 { 306 #if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD 307 /* For Secure Partitions we don't need post processing */ 308 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 309 (image_id < MAX_NUMBER_IDS)) { 310 return 0; 311 } 312 #endif 313 return arm_bl2_handle_post_image_load(image_id); 314 } 315 316 int bl2_plat_handle_post_image_load(unsigned int image_id) 317 { 318 return arm_bl2_plat_handle_post_image_load(image_id); 319 } 320