fix(tc): only suspend booting after running plat tests

1. When doing a normal boot, tc_bl31_common_platform_setup() should
simply configure the platform and return.

2. When we are running the platf

fix(tc): only suspend booting after running plat tests

1. When doing a normal boot, tc_bl31_common_platform_setup() should
simply configure the platform and return.

2. When we are running the platform tests instead,
tc_bl31_common_platform_setup() should run the tests then suspend
booting (and thus never return).

We were incorreclty suspending the boot in case 1 as well. Put that
code under a preprocessor condition (PLATFORM_TEST_NV_COUNTERS or
PLATFORM_TEST_TFM_TESTSUITE) to fix this.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I7d20800e3bcd85261e2cdad325586d184e12a3e3

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Merge changes from topic "mp/group0_support" into integration

* changes:
docs(spm): support for handling Group0 interrupts
feat(spmd): introduce platform handler for Group0 interrupt
feat(spmd

Merge changes from topic "mp/group0_support" into integration

* changes:
docs(spm): support for handling Group0 interrupts
feat(spmd): introduce platform handler for Group0 interrupt
feat(spmd): add support for FFA_EL3_INTR_HANDLE_32 ABI
feat(spmd): register handler for group0 interrupt from NWd

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fix(n1sdp): add platform-specific power domain functions

Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf added a redistributor
power off to resolve an error on N1SDP/Morello. Prior to this fix,
turn

fix(n1sdp): add platform-specific power domain functions

Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf added a redistributor
power off to resolve an error on N1SDP/Morello. Prior to this fix,
turning off both cores in a cluster would cause a hang when powering
back on either core. This change introduced issues on other platforms
with a different GIC implementation, and was reverted in commit
60719e4e0965aead49d927f12bf2a37bd2629012.

This commit uses the previous fix in platform-specific implementations
of power domain off/suspend functions.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I52c463646c494fe931ff4ce47afb940a56978fcd

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fix(morello): add platform-specific power domain functions

Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf added a redistributor
power off to resolve an error on N1SDP/Morello. Prior to this fix,
tu

fix(morello): add platform-specific power domain functions

Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf added a redistributor
power off to resolve an error on N1SDP/Morello. Prior to this fix,
turning off both cores in a cluster would cause a hang when powering
back on either core. This change introduced issues on other platforms
with a different GIC implementation, and was reverted in commit
60719e4e0965aead49d927f12bf2a37bd2629012.

This commit uses the previous fix in platform-specific implementations
of power domain off/suspend functions.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: Ib7689a5e08ada3862406fa92019a6f0bcfb48d79

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Merge changes I9d06e0ee,I6980e84f into integration

* changes:
feat(tegra): implement 'pwr_domain_off_early' handler
feat(psci): introduce 'pwr_domain_off_early' hook

fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOG

With introduction of check on boolean flags, it should be ensured that
each boolean flag has default value provided by platform.

Signed-off

fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOG

With introduction of check on boolean flags, it should be ensured that
each boolean flag has default value provided by platform.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ia92c3dded842e14099b4a7667569605d7066a8f9

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fix(stm32mp1): always define PKA algos flags

The flags to set PKA algo are set to 0 when TRUSTED_BOARD_BOOT is not
set.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ib70a2bc514

fix(stm32mp1): always define PKA algos flags

The flags to set PKA algo are set to 0 when TRUSTED_BOARD_BOOT is not
set.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ib70a2bc51451a2047d7a50a8307e9063d4a2a0ee

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fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF

This flag just needs to be defined, and does not need to have a boolean
value. Remove it from the assert_booleans check.

Signed-off-by: Yann

fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF

This flag just needs to be defined, and does not need to have a boolean
value. Remove it from the assert_booleans check.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4e4c9ae1e5003ca2cf7c0c0e31d1561d032937c8

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feat(fvp): define ns memory in the SPMC manifest

The SPMC (Hafnium) looks for secure and non-secure ranges
in its manifest.
Those relate with ranges that can be used by SPs in their
FF-A manifests.

feat(fvp): define ns memory in the SPMC manifest

The SPMC (Hafnium) looks for secure and non-secure ranges
in its manifest.
Those relate with ranges that can be used by SPs in their
FF-A manifests.
The NS memory that is not used by SPs will be assigned
to the NWd, for it to share memory with SPs as needed.
Thus, this limits the memory the NWd can share with SPs,
to prevent NWD VMs from sharing memory that belongs
to other critical components.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Iad03eb138a57068fbb18c53141bdf6bf9c171b28

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Merge "feat(xilinx): sync copyright format" into integration

Merge "build: deprecate Arm rde1edge" into integration

Merge "fix(sme): disable SME for SPD=spmd" into integration

Merge changes Ia1142b31,I424f1cde into integration

* changes:
fix(tc): enable the execution of both platform tests
fix(tc): update the name of mbedtls config header

Merge "refactor(fiptool): move plat_fiptool.mk to tools" into integration

feat(spmd): introduce platform handler for Group0 interrupt

This patch introduces a handler for FVP platform to triage Group0
secure interrupts. Currently, it is empty but serves as a
placeholder fo

feat(spmd): introduce platform handler for Group0 interrupt

This patch introduces a handler for FVP platform to triage Group0
secure interrupts. Currently, it is empty but serves as a
placeholder for future Group0 interrupt sources.

Moreover, this patch also provides a dummy implementation of the
above mentioned platform hook for QEMU, corstone100, n1sdp and
hikey960 ports.

Change-Id: I01d3451408f47ac313b0af74046cce89f89b85bb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(tegra): remove dependency on CPU registers to get boot parameters

Commit 3e14df6f6 removed the code to clear the CPU registers X0 - X3,
which affected the Tegra platforms. Tegra platforms rely o

fix(tegra): remove dependency on CPU registers to get boot parameters

Commit 3e14df6f6 removed the code to clear the CPU registers X0 - X3,
which affected the Tegra platforms. Tegra platforms rely on the boot
parameters passed through custom mechanisms and do not use these
general purpose registers, but maintained sanity checks to support
legacy bootloaders. These sanity checks went out of sync due to the
code cleanup from bl31_entrypoint().

This patch removes the checks and calls the SOC specific handlers to
retrieve the boot parameters.

Change-Id: I0cf4d9c0370c33ff7715b48592b6bc0602f3c93e
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge "feat(fvp): introduce PLATFORM_TEST_EA_FFH config" into integration

fix(sme): disable SME for SPD=spmd

SPMD is not compatible with ENABLE_SME_FOR_NS.
Hence disable SME when SPD=spmd

Change-Id: I8bcf2493819718732563f9db69f7186ac7437637
Signed-off-by: Jayanth Dodderi

fix(sme): disable SME for SPD=spmd

SPMD is not compatible with ENABLE_SME_FOR_NS.
Hence disable SME when SPD=spmd

Change-Id: I8bcf2493819718732563f9db69f7186ac7437637
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(fvp): introduce PLATFORM_TEST_EA_FFH config

FVP currently does not have proper handler to do Firmware First Handling
(FFH) of lower EL External aborts and it ends up in EL3 panic.

To test the

feat(fvp): introduce PLATFORM_TEST_EA_FFH config

FVP currently does not have proper handler to do Firmware First Handling
(FFH) of lower EL External aborts and it ends up in EL3 panic.

To test the scenarios sensibly we need a proper handling when the FVP is
under test so that we do not change the default behavior.

Introduce PLATFORM_TEST_EA_FFH config which will be enabled in CI
scripts and implement a proper handling for Sync EA and SErrors from
lower EL.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib130154206b17f72c49c9f07de2d92f35a97ab0b

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Merge "feat(sme): enable SME2 functionality for NS world" into integration

fix(qemu-sbsa): enable FGT

QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.

So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.

Signed-off-by: Marcin Juszkiewicz <mar

fix(qemu-sbsa): enable FGT

QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.

So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I49fb3e742b69ce7be5666e0144525dde21a68238

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chore(bl1): remove redundant bl1_arch_next_el_setup

bl1_arch_next_el_setup has no references anywhere in TF-A. Remove it as
it is redundant

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

chore(bl1): remove redundant bl1_arch_next_el_setup

bl1_arch_next_el_setup has no references anywhere in TF-A. Remove it as
it is redundant

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ice2997f33c318390883347acdd03dc6755f87ea5

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Merge "build(fvp): reduce the number of cpu libraries included by default" into integration

Merge "style(xilinx): fix AMD copyright format" into integration

feat(sme): enable SME2 functionality for NS world

FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations ef

feat(sme): enable SME2 functionality for NS world

FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations efficiently, but also provides
outer-product instructions to accelerate matrix operations.
It affords instructions for multi-vector operations.
Further, it adds an 512 bit architectural register ZT0.

This patch implements all the changes introduced with FEAT_SME2
to ensure that the instructions are allowed to access ZT0
register from Non-secure lower exception levels.

Additionally, it adds support to ensure FEAT_SME2 is aligned
with the existing FEATURE DETECTION mechanism, and documented.

Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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