Merge "fix(versal): replace FPD_MAINCCI* macros" into integration

Merge "feat(mt8188): add apu power on/off control" into integration

Merge "feat(qemu): increase max cpus per cluster to 16" into integration

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.

Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(versal): replace FPD_MAINCCI* macros

Replace FPD_MAINCCI* macros by PLAT_ARM_CCI* not to have two different
names for the same IP.

Change-Id: Ia1930e150a51603471051acec5c79c649d57f92f
Signed-of

fix(versal): replace FPD_MAINCCI* macros

Replace FPD_MAINCCI* macros by PLAT_ARM_CCI* not to have two different
names for the same IP.

Change-Id: Ia1930e150a51603471051acec5c79c649d57f92f
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(intel): fix Agilex and N5X clock manager to main PLL C0

Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ

fix(intel): fix Agilex and N5X clock manager to main PLL C0

Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19

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feat(intel): implement timer init divider via CPU frequency for N5X

Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.

Signe

feat(intel): implement timer init divider via CPU frequency for N5X

Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibfaa47fb7a25176eebf06f4828bf9729d56f12ed

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Merge "fix(rpi3): initialize SD card host controller" into integration

fix(rpi3): initialize SD card host controller

Add initial configuration parameters for Rasperry Pi 3's sdhost
controller, and then configure and use those parameters.

This change allows warm reboot

fix(rpi3): initialize SD card host controller

Add initial configuration parameters for Rasperry Pi 3's sdhost
controller, and then configure and use those parameters.

This change allows warm reboots of UEFI on Raspberry Pi 3B+ where
existing code often fails with "unknown error". See discussion at:

https://github.com/pftf/RPi3/issues/24

The basic idea is that some initial configuration parameters
(clock rate, bus width) aren't configured into the hardware before
commands start being sent. I suspect that the particular setting
that matters is the "slow card" bit, but the initial clock setting
also seemed wrong to me.

Change-Id: I526def340def143f23f3422f1fc14c12c937ca7f
Signed-off-by: Rob Newberry <robthedude@mac.com>

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feat(pie/por): support permission indirection and overlay

Arm v8.9 introduces a series of features providing a new way to set memory
permissions. Instead of directly encoding the permissions in the

feat(pie/por): support permission indirection and overlay

Arm v8.9 introduces a series of features providing a new way to set memory
permissions. Instead of directly encoding the permissions in the page
tables the PTEs contain indexes into an array of permissions stored in
system registers, allowing greater flexibility and density of encoding.

Enable access to these features for EL2 and below, context switching the
newly added EL2 registers as appropriate. Since all of FEAT_S[12]P[IO]E
are separately discoverable we have separate build time options for
enabling them, but note that there is overlap in the registers that they
implement and the enable bit required for lower EL access.

Change the FVP platform to default to handling them as dynamic options so
the right decision can be made by the code at runtime.

Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: Icf89e444e39e1af768739668b505661df18fb234

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Merge "fix(imx8mq): fix compilation with gcc >= 12.x" into integration

Merge "feat(zynqmp): make stack size configurable" into integration

Merge "feat(intel): fix bridge disable and reset" into integration

feat(zynqmp): make stack size configurable

If PLATFORM_STACK_SIZE not already defined, use the default value of
PLATFORM_STACK_SIZE.
This makes the stack size value configurable for different interf

feat(zynqmp): make stack size configurable

If PLATFORM_STACK_SIZE not already defined, use the default value of
PLATFORM_STACK_SIZE.
This makes the stack size value configurable for different interface
like custom packages.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I87e9fcbfb4c4092378b1ac0ff8fb6d084495d320

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Merge "fix(intel): update boot scratch to indicate to Uboot is PSCI ON" into integration

Merge "feat(zynqmp): add hooks for custom runtime setup" into integration

fix(intel): flash dcache before mmio read

Flash dcache before mmio read to avoid reading old/previous value.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ifd5a63a3c0f20b3e673be62

fix(intel): flash dcache before mmio read

Flash dcache before mmio read to avoid reading old/previous value.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ifd5a63a3c0f20b3e673be62ff5c3b6c4cf69df51

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fix(intel): fix the pointer of block memory to fill in and bytes being set

Fix on the pointer of the block memory to fill in and the number of
bytes to be set. So it can clear the exact address with

fix(intel): fix the pointer of block memory to fill in and bytes being set

Fix on the pointer of the block memory to fill in and the number of
bytes to be set. So it can clear the exact address with exact number
of bytes.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Idb8bda446ecd4c1d85d1ec9802bdcb020904c6c1

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feat(intel): fix bridge disable and reset

Fix bridge sideband manager register clear and set incorrect
implementation. To support non-graceful full bridge disable
and enable.

Signed-off-by: Ang Tie

feat(intel): fix bridge disable and reset

Fix bridge sideband manager register clear and set incorrect
implementation. To support non-graceful full bridge disable
and enable.

Signed-off-by: Ang Tien Sung <tien.sung.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I651f3ec163d954e8efb0542ec33bce96e51992db

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fix(intel): update boot scratch to indicate to Uboot is PSCI ON

There is a use case where kernel requested ATF to power off/on only CPU0.
However, after ATF power off/on CPU0, CPU0 did not back into

fix(intel): update boot scratch to indicate to Uboot is PSCI ON

There is a use case where kernel requested ATF to power off/on only CPU0.
However, after ATF power off/on CPU0, CPU0 did not back into the state
to wait for ATF. Instead, CPU0 continue to reentry SPL boot sequence
because CPU0 is master/primary core. This causing the system reboot from
SPL again, while the slave core still in kernel.

To resolve this, ATF is set the boot scratch register 8 bit 17 whenever
it is a request from kernel to power off/on only CPU0. So, if this boot
scratch bit is set, CPU 0 will be able to put into a state to wait for
ATF.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ia0228c5396beaa479858f5bd02fc05139efd2423

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Merge "fix(fvp): work around DRTM_SUPPORT BL31 progbits exceeded" into integration

feat(zynqmp): add hooks for custom runtime setup

Add runtime setup hooks (via custom_runtime_setup()) for low level
operations related to setting up the system to correct state.

Change-Id: I4af7050

feat(zynqmp): add hooks for custom runtime setup

Add runtime setup hooks (via custom_runtime_setup()) for low level
operations related to setting up the system to correct state.

Change-Id: I4af7050dba2ee2446366d482bef5f5c5dde4bddf
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(mt8188): add apu power on/off control

Add mt8188 apu power on/off control

Change-Id: I8e28bf7a4ad4067553981c67c4c2225fdd802859
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-of

feat(mt8188): add apu power on/off control

Add mt8188 apu power on/off control

Change-Id: I8e28bf7a4ad4067553981c67c4c2225fdd802859
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com>

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feat(qemu): increase max cpus per cluster to 16

Qemu-tcg with GICv3 emulation enabled will by default configure MPIDR
topology to report up to 16 cpus per cluster. This is NOT overriden by
qemu's -s

feat(qemu): increase max cpus per cluster to 16

Qemu-tcg with GICv3 emulation enabled will by default configure MPIDR
topology to report up to 16 cpus per cluster. This is NOT overriden by
qemu's -smp setting, e.g. -smp 8,clusters=2,cores=4,threads=1 will still
generate MPIDR reads as if all 8 CPUs were within one cluster.

Increase the hardcoded limit to reflect that so that we accept PSCI
calls that provide MPIDRs based on what was actually read from the
emulated CPU.

Change-Id: Ia321d555f885c96a9a94ae053b340e3a9e300e6d
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

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fix(imx8mq): fix compilation with gcc >= 12.x

Starting with GCC >= 12.x the -Wall option includes -Werror=array-bounds
checks. Per default GCC treats all memory accesses below 4096 as NULL,
so acces

fix(imx8mq): fix compilation with gcc >= 12.x

Starting with GCC >= 12.x the -Wall option includes -Werror=array-bounds
checks. Per default GCC treats all memory accesses below 4096 as NULL,
so access to ROMAPI causes the following warning:

------------
In file included from plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:20:
In function 'mmio_read_8',
inlined from 'imx8mq_soc_info_init' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:70:16,
inlined from 'bl31_platform_setup' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:206:2:
include/lib/mmio.h:19:16: error: array subscript 0 is outside array bounds of 'volatile uint8_t[0]' {aka 'volatile unsigned char[]'} [-Werror=array-bounds]
19 | return *(volatile uint8_t*)addr;
| ^~~~~~~~~~~~~~~~~~~~~~~~
In function 'mmio_read_8',
inlined from 'imx8mq_soc_info_init' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:74:16,
inlined from 'bl31_platform_setup' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:206:2:
include/lib/mmio.h:19:16: error: array subscript 0 is outside array bounds of 'volatile uint8_t[0]' {aka 'volatile unsigned char[]'} [-Werror=array-bounds]
19 | return *(volatile uint8_t*)addr;
| ^~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
------------

This comes arguably from us somewhat abusing pointers to access MMIO
memory regions, which is not really covered by the C language.

Replace the pointer-dereferencing mmio_read_8() with an implementation
that uses inline assembly, to directly generate an 8-bit load
instruction. This avoids the compiler thinking that this access is using
a pointer it needs to jealously look after.

Change-Id: Iab39f6f615d51d3e8a1c54a1262d1e6ec208811d
Reported-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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