Merge changes from topic "mp/feat_ras" into integration

* changes:
refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED
refactor(ras): replace RAS_EXTENSION with FEAT_RAS

fix(msm8916): add timeout for crash console TX flush

Resetting the UART DM controller while there are still remaining
characters in the FIFO often results in corruption on the UART receiver
side. To

fix(msm8916): add timeout for crash console TX flush

Resetting the UART DM controller while there are still remaining
characters in the FIFO often results in corruption on the UART receiver
side. To avoid this the msm8916 crash console implementation tries to
wait until the TX FIFO is empty.

Unfortunately this might spin forever if the transmitter was disabled
before it has fully finished transmitting. In this case the TXEMT bit
console_uartdm_core_flush is waiting for will never get set.

There seems to be no good way to detect if the transmitter is actually
enabled via the status registers. However, the TX FIFO is fairly small
and should not take too long to get flushed, so fix this by simply
limiting the amount of iterations with a short timeout.

Move the code to console_uartdm_core_init to ensure that this always
happens before resetting the transmitter (also during initialization).

Change-Id: I5bb43cb0b6c029bcd15e253d60d36c0b310e108b
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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style(msm8916): use size macros

Use the pre-defined size macros (SZ_*) for more clarity and to avoid
having to add comments to each size represented by hexadecimal numbers.

Change-Id: I6aebe2caf136

style(msm8916): use size macros

Use the pre-defined size macros (SZ_*) for more clarity and to avoid
having to add comments to each size represented by hexadecimal numbers.

Change-Id: I6aebe2caf1365279670955b9b507dec7d7b04457
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): expose more timer frames

The memory-mapped generic timer on msm8916 has 7 timer frames, but
currently only one is exposed for usage in the non-secure world.

The platform port is curr

feat(msm8916): expose more timer frames

The memory-mapped generic timer on msm8916 has 7 timer frames, but
currently only one is exposed for usage in the non-secure world.

The platform port is currently only designed to be used as minimal PSCI
implementation, without secure world that could make use of the other
timer frames. Let's make all of them available to the normal world.

If needed this could still be changed later by reserving some timer
frames conditionally to a specific SPD being enabled in the build.

Change-Id: Ib59df16aa1fd3dbc875ab6369c133737830c98c6
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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fix(msm8916): drop unneeded initialization of CNTACR

Normal world software is responsible to initialize CNTACR as needed.
There is no existing software for msm8916 that depends on having this
initia

fix(msm8916): drop unneeded initialization of CNTACR

Normal world software is responsible to initialize CNTACR as needed.
There is no existing software for msm8916 that depends on having this
initialization in BL31 so drop it before anything starts to rely on it.

Related issue: https://github.com/ARM-software/tf-issues/issues/170

Change-Id: I9d037ab218c0c1c8a5d5523722013eba531f4728
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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build(msm8916): disable unneeded workarounds

The Cortex-A53 cores used in the msm8916 platform are not affected by
CVE-2017-5715 and CVE-2022-23960, so disable the workarounds for them
to drop the u

build(msm8916): disable unneeded workarounds

The Cortex-A53 cores used in the msm8916 platform are not affected by
CVE-2017-5715 and CVE-2022-23960, so disable the workarounds for them
to drop the unused code from the compiled binary.

Change-Id: I9df5a4657c4fd90702b4db4e82d4ee1a2f60303c
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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fix(msm8916): flush dcache after writing msm8916_entry_point

msm8916_entry_point is read with caches off (and even from two
different physical addresses when read through the "boot remapper"),
so it

fix(msm8916): flush dcache after writing msm8916_entry_point

msm8916_entry_point is read with caches off (and even from two
different physical addresses when read through the "boot remapper"),
so it should be flushed to RAM after writing it.

Change-Id: I5c8193954bb28043b0a46fb2038f629bd8796c74
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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fix(msm8916): print \r before \n on UART console

UART drivers in TF-A are expected to print \r before \n. Some terminal
emulators expect \r\n as line endings by default so not doing this
causes brok

fix(msm8916): print \r before \n on UART console

UART drivers in TF-A are expected to print \r before \n. Some terminal
emulators expect \r\n as line endings by default so not doing this
causes broken line breaks.

Change-Id: I271a35a7c6907441bc71713b0b6a1da19da96878
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround

Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround platforms non-arm interconnect
refactor(errata_abi): factor in non-arm interconnect
feat(errata_abi): errata management firmware interface

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Merge "fix(qemu-sbsa): enable FGT" into integration

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

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fix(rockchip): use semicolon instead of comma

Use semicolon insted of comma at the end of line.

Change-Id: I0ec7a70ec659333c98d586f7bebd5d91bd6c6cc1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>

Merge "feat(mt8188): add MT8188 SPM debug logs" into integration

refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED

At the moment we only support FEAT_RAS to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime det

refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED

At the moment we only support FEAT_RAS to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (FEAT_RAS=2), by splitting
is_armv8_2_feat_ras_present() into an ID register reading function and
a second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we access RAS related registers.

Also move the context saving code from assembly to C, and use the new
is_feat_ras_supported() function to guard its execution.

Change the FVP platform default to the now supported dynamic
option (=2), so the right decision can be made by the code at runtime.

Change-Id: I30498f72fd80b136850856244687400456a03d0e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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refactor(ras): replace RAS_EXTENSION with FEAT_RAS

The current usage of RAS_EXTENSION in TF-A codebase is to cater for two
things in TF-A :
1. Pull in necessary framework and platform hooks for Firm

refactor(ras): replace RAS_EXTENSION with FEAT_RAS

The current usage of RAS_EXTENSION in TF-A codebase is to cater for two
things in TF-A :
1. Pull in necessary framework and platform hooks for Firmware first
handling(FFH) of RAS errors.
2. Manage the FEAT_RAS extension when switching the worlds.

FFH means that all the EAs from NS are trapped in EL3 first and signaled
to NS world later after the first handling is done in firmware. There is
an alternate way of handling RAS errors viz Kernel First handling(KFH).
Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the
feature is needed for proper handling KFH in as well.

This patch breaks down the RAS_EXTENSION flag into a flag to denote the
CPU architecture `ENABLE_FEAT_RAS` which is used in context management
during world switch and another flag `RAS_FFH_SUPPORT` to pull in
required framework and platform hooks for FFH.

Proper support for KFH will be added in future patches.

BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The
equivalent functionality can be achieved by the following
2 options:
- ENABLE_FEAT_RAS
- RAS_FFH_SUPPORT

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec

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Merge changes from topic "assert_boolean_set" into integration

* changes:
build!: check boolean flags are not empty
fix(build): add a default value for INVERTED_MEMMAP
fix(a5ds): add default v

Merge changes from topic "assert_boolean_set" into integration

* changes:
build!: check boolean flags are not empty
fix(build): add a default value for INVERTED_MEMMAP
fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOG
fix(st-crypto): move flag control into source code
fix(stm32mp1): always define PKA algos flags
fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF

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Merge "feat(fvp): introduce PLATFORM_TEST_RAS_FFH config" into integration

feat(mt8188): add MT8188 SPM debug logs

Add debug logs for tracking the status of suspend and resume.

Change-Id: Id2d2ab06fadb3118ab66f816937e0dd6e43dbdc3
Signed-off-by: Jason Chen <Jason-ch.Chen@m

feat(mt8188): add MT8188 SPM debug logs

Add debug logs for tracking the status of suspend and resume.

Change-Id: Id2d2ab06fadb3118ab66f816937e0dd6e43dbdc3
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>

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refactor(tc): define PLATFORM_TESTS for scale

For scalability when we add more tests in the future, add PLATFORM_TESTS
macro when specific test flags, i.e. PLATFORM_TEST_NV_COUNTERS, are
defined.

C

refactor(tc): define PLATFORM_TESTS for scale

For scalability when we add more tests in the future, add PLATFORM_TESTS
macro when specific test flags, i.e. PLATFORM_TEST_NV_COUNTERS, are
defined.

Change-Id: Icb875a171dde673fca9fcf66624ac55383e7b641
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(fvp): enable errata management interface

Errata ABI feature specific build flag, flag to enable
CPUs in the cpu list, flags to test non-arm interconnect based
errata flags when enabled from a p

feat(fvp): enable errata management interface

Errata ABI feature specific build flag, flag to enable
CPUs in the cpu list, flags to test non-arm interconnect based
errata flags when enabled from a platform level.
Added to the FVP platform makefile to test the errata abi feature
implementation.

The flags to enable CPUs in the cpu list will be removed once
synchronized with the errata framework.

Change-Id: I30877a22ac1348906a6ddfb26f9e8839912d3572
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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feat(fvp): introduce PLATFORM_TEST_RAS_FFH config

While doing RAS related tests there were few patches related with
fault injection and handling were applied through CI hooks.
These patches were inv

feat(fvp): introduce PLATFORM_TEST_RAS_FFH config

While doing RAS related tests there were few patches related with
fault injection and handling were applied through CI hooks.
These patches were invisible as they were applied and removed after the
build is done.

This patch introduces build macro PLATFORM_TEST_RAS_FFH and moves the
patches applied through CI under this.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Iddba52f3ebf21f575a473e50c607a944391156b9

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feat(tc): allow secure watchdog timer to trigger periodically

This patch does the following:
1. Configures SBSA secure watchdog timer as Group0 interrupt for
TC platform while keeping it as G

feat(tc): allow secure watchdog timer to trigger periodically

This patch does the following:
1. Configures SBSA secure watchdog timer as Group0 interrupt for
TC platform while keeping it as Group1 secure interrupt for
other CSS based SoCs.
2. Programs the watchdog timer to trigger periodically
3. Provides a Group0 interrupt handler for TC platform port to
deactivate the EL3 interrupt due to expiry of secure watchdog
timer and refresh it explicitly.

Change-Id: I3847d6eb7347c6ea0e527b97b096119ca1e6701b
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "feat(fvp): define ns memory in the SPMC manifest" into integration

Merge changes from topic "allwinner_t507" into integration

* changes:
feat(allwinner): add support for Allwinner T507 SoC
feat(allwinner): add function to detect H616 die variant
feat(allwinne

Merge changes from topic "allwinner_t507" into integration

* changes:
feat(allwinner): add support for Allwinner T507 SoC
feat(allwinner): add function to detect H616 die variant
feat(allwinner): add extra CPU control registers
refactor(allwinner): consolidate sunxi_cfg.h files

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Merge "fix(tc): only suspend booting after running plat tests" into integration