History log of /rk3399_ARM-atf/plat/ (Results 2751 – 2775 of 8868)
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573d600e08-Dec-2022 Andre Przywara <andre.przywara@arm.com>

refactor(allwinner): consolidate sunxi_cfg.h files

The header files describing the CPU cluster configuration IP block for
the H6 and H616 are actually identical, so merge them into one file and
move

refactor(allwinner): consolidate sunxi_cfg.h files

The header files describing the CPU cluster configuration IP block for
the H6 and H616 are actually identical, so merge them into one file and
move that to a common location. There is an upcoming SoC which will
similarly share a header file with the R329 SoC, so move that to the
same location already. In Allwinner's BSP source those two SoC groups
are typically called "NCAT" and "NCAT2", so use those names for the
shared header files. No functional change.

Change-Id: I98318373577344dbe228a81fa331ce660df32b5f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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0dcb03b606-Apr-2023 Boyan Karatotev <boyan.karatotev@arm.com>

build(fvp): reduce the number of cpu libraries included by default

The fvp build includes a very large number of cpus so that it can run on
a wide range of models. One config (HW_ASSISTED_COHERENCY=

build(fvp): reduce the number of cpu libraries included by default

The fvp build includes a very large number of cpus so that it can run on
a wide range of models. One config (HW_ASSISTED_COHERENCY=1
CTX_INCLUDE_AARCH32_REGS=0) includes an unusually large number of cpus.
Well, the list is quite arbitrary and incomplete. As we're currently out
of BL31 space on the fvp, remove all that are not routinely run in the
CI to buy us some time.

Also use the opportunity to reorder the list into something searchable.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8c6cad41327451edf0d3a0e92c43d6c72c254aac

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2774965325-Apr-2023 Michal Simek <michal.simek@amd.com>

feat(xilinx): sync copyright format

Use the same format in all files 's/Copyright (C)/Copyright (c)/g'.

Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7
Signed-off-by: Michal Simek <michal.sime

feat(xilinx): sync copyright format

Use the same format in all files 's/Copyright (C)/Copyright (c)/g'.

Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7
Signed-off-by: Michal Simek <michal.simek@amd.com>

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0df3824b25-Apr-2023 Manish Pandey <manish.pandey2@arm.com>

Merge "refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED" into integration

88727fc326-Jan-2023 Andre Przywara <andre.przywara@arm.com>

refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED

At the moment we only support FEAT_DIT to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime det

refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED

At the moment we only support FEAT_DIT to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_DIT=2), by splitting
is_armv8_4_dit_present() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed).

We use ENABLE_DIT in two occassions in assembly code, where we just set
the DIT bit in the DIT system register.
Protect those two cases by reading the CPU ID register when ENABLE_DIT
is set to 2.

Change the FVP platform default to the now supported dynamic
option (=2), so the right decision can be made by the code at runtime.

Change-Id: I506d352f18e23c60db8cdf08edb449f60adbe098
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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33b4041d25-Apr-2023 Manish V Badarkhe <manish.badarkhe@arm.com>

Merge "refactor(morello): remove duplication of platform information struct" into integration

760fbfc425-Apr-2023 Bipin Ravi <bipin.ravi@arm.com>

Merge "feat(gcs): support guarded control stack" into integration

fb2fd55814-Mar-2023 Manish Pandey <manish.pandey2@arm.com>

fix(fvp): correct ehf priority for SPM_MM

PLAT_SP_PRI is used by SPM_MM and it is assigned same value as RAS
priority. Which is not allowed by exception handling framework and
causes build failure i

fix(fvp): correct ehf priority for SPM_MM

PLAT_SP_PRI is used by SPM_MM and it is assigned same value as RAS
priority. Which is not allowed by exception handling framework and
causes build failure if both SPM_MM and RAS is enabled.

To fix this problem assign SP a different priority than RAS.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Iff64ac547f0966c0d94ac7c3ab0eb1e3151fb314

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7c7e7b6224-Apr-2023 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge changes from topic "mb/trusted-boot-update" into integration

* changes:
refactor(auth)!: unify REGISTER_CRYPTO_LIB
refactor(auth): replace plat_convert_pk
docs(auth): add auth_decrypt in

Merge changes from topic "mb/trusted-boot-update" into integration

* changes:
refactor(auth)!: unify REGISTER_CRYPTO_LIB
refactor(auth): replace plat_convert_pk
docs(auth): add auth_decrypt in CM chapter
feat(auth): compare platform and certificate ROTPK for authentication
docs(auth): add 'calc_hash' function's details in CM

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ac72bdc020-Apr-2023 Michal Simek <michal.simek@amd.com>

style(xilinx): fix AMD copyright format

There is missing comma in copyright line. It is better to have all
Copyrights align to the same style that's why fix it.

Change-Id: Ifc04b474e1a172a7243b073d

style(xilinx): fix AMD copyright format

There is missing comma in copyright line. It is better to have all
Copyrights align to the same style that's why fix it.

Change-Id: Ifc04b474e1a172a7243b073d944007cf17d76e87
Signed-off-by: Michal Simek <michal.simek@amd.com>

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0aab76a424-Apr-2023 Joanna Farley <joanna.farley@arm.com>

Merge changes from topic "versal/xlat-v2" into integration

* changes:
feat(versal): switch to xlat_v2
fix(xilinx): remove asserts around arg0/arg1

dee99f1015-Mar-2023 Yann Gautier <yann.gautier@st.com>

refactor(auth)!: unify REGISTER_CRYPTO_LIB

Have only one definition for REGISTER_CRYPTO_LIB macro, with all the
possible fields. Worst case adds 4 u64 to crypto_lib_desc.
While at it, correct some M

refactor(auth)!: unify REGISTER_CRYPTO_LIB

Have only one definition for REGISTER_CRYPTO_LIB macro, with all the
possible fields. Worst case adds 4 u64 to crypto_lib_desc.
While at it, correct some MISRA violations:
MC3R1.R12.1: (advisory) The precedence of operators within expressions
should be made explicit.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I1342a20e6eef2354753182c2a81ff959e03e5c81

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4ac5b39424-Jan-2023 Yann Gautier <yann.gautier@foss.st.com>

refactor(auth): replace plat_convert_pk

Following discussions in the reviews of the patch that introduced
plat_convert_pk() function [1], it was decided to deprecate it to
avoid weak function declar

refactor(auth): replace plat_convert_pk

Following discussions in the reviews of the patch that introduced
plat_convert_pk() function [1], it was decided to deprecate it to
avoid weak function declaration.
A new optional function pointer convert_pk is added to crypto_lib_desc_t.
A new function crypto_mod_convert_pk() will either call
crypto_lib_desc.convert_pk() if it is defined, or do the same
as what was done by the weak function otherwise.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/17174

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9358867f8bfd5e96b5ee238c066877da368e43c6

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2ef07eb420-Apr-2023 Joanna Farley <joanna.farley@arm.com>

Merge "fix(zynqmp): remove unused PLAT_NUM_POWER_DOMAINS" into integration

d84171b420-Apr-2023 Joanna Farley <joanna.farley@arm.com>

Merge "style(xilinx): replace ARM by Arm in copyrights" into integration


xilinx/common/include/plat_startup.h
xilinx/common/include/pm_client.h
xilinx/common/include/pm_common.h
xilinx/common/include/pm_ipi.h
xilinx/common/ipi.c
xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.h
xilinx/common/plat_startup.c
xilinx/common/pm_service/pm_ipi.c
xilinx/versal/aarch64/versal_common.c
xilinx/versal/aarch64/versal_helpers.S
xilinx/versal/bl31_versal_setup.c
xilinx/versal/include/plat_macros.S
xilinx/versal/include/plat_private.h
xilinx/versal/include/platform_def.h
xilinx/versal/include/versal_def.h
xilinx/versal/plat_psci.c
xilinx/versal/plat_topology.c
xilinx/versal/plat_versal.c
xilinx/versal/platform.mk
xilinx/versal/sip_svc_setup.c
xilinx/versal/versal_gicv3.c
xilinx/versal_net/aarch64/versal_net_common.c
xilinx/versal_net/aarch64/versal_net_helpers.S
xilinx/versal_net/bl31_versal_net_setup.c
xilinx/versal_net/include/plat_macros.S
xilinx/versal_net/include/plat_private.h
xilinx/versal_net/include/platform_def.h
xilinx/versal_net/include/versal_net_def.h
xilinx/versal_net/plat_psci.c
xilinx/versal_net/plat_topology.c
xilinx/versal_net/platform.mk
xilinx/versal_net/sip_svc_setup.c
xilinx/versal_net/versal_net_gicv3.c
xilinx/zynqmp/aarch64/zynqmp_common.c
xilinx/zynqmp/aarch64/zynqmp_helpers.S
xilinx/zynqmp/bl31_zynqmp_setup.c
xilinx/zynqmp/include/plat_ipi.h
xilinx/zynqmp/include/plat_macros.S
xilinx/zynqmp/include/plat_pm_common.h
xilinx/zynqmp/include/plat_private.h
xilinx/zynqmp/include/platform_def.h
xilinx/zynqmp/include/zynqmp_def.h
xilinx/zynqmp/plat_psci.c
xilinx/zynqmp/plat_topology.c
xilinx/zynqmp/plat_zynqmp.c
xilinx/zynqmp/platform.mk
xilinx/zynqmp/pm_service/pm_api_clock.c
xilinx/zynqmp/pm_service/pm_api_clock.h
xilinx/zynqmp/pm_service/pm_api_ioctl.c
xilinx/zynqmp/pm_service/pm_api_ioctl.h
xilinx/zynqmp/pm_service/pm_api_pinctrl.c
xilinx/zynqmp/pm_service/pm_api_pinctrl.h
xilinx/zynqmp/pm_service/pm_client.c
xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h
xilinx/zynqmp/pm_service/zynqmp_pm_defs.h
xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.h
xilinx/zynqmp/sip_svc_setup.c
xilinx/zynqmp/tsp/tsp-zynqmp.mk
xilinx/zynqmp/tsp/tsp_plat_setup.c
xilinx/zynqmp/zynqmp_ehf.c
xilinx/zynqmp/zynqmp_ipi.c
xilinx/zynqmp/zynqmp_sdei.c
58290c4619-Apr-2023 Manish V Badarkhe <Manish.Badarkhe@arm.com>

build: deprecate Arm rde1edge

Arm has decided to deprecate the rde1edge platform. The development
of software and fast model for this platform have been discontinued.
Hence, updated the makefile to

build: deprecate Arm rde1edge

Arm has decided to deprecate the rde1edge platform. The development
of software and fast model for this platform have been discontinued.
Hence, updated the makefile to warn about the deprecation of this
platform, and also reflected it in the documentation.

Change-Id: I0d44de4590dd5dce02c7c4b433df25dc438e6c49
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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2e31daec19-Apr-2023 Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge "feat(imx8): add support for debug uart on lpuart1" into integration

468a601622-Mar-2023 Werner Lewis <werner.lewis@arm.com>

refactor(morello): remove duplication of platform information struct

morello_plat_info is defined identically in multiple files, definition
is moved to a header file to avoid duplication.

Signed-of

refactor(morello): remove duplication of platform information struct

morello_plat_info is defined identically in multiple files, definition
is moved to a header file to avoid duplication.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I607354902c55f5c31f0732de9db60604b82aef97

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1cf3e2f020-Mar-2023 Manish V Badarkhe <Manish.Badarkhe@arm.com>

feat(fvp): add Event Log maximum size property in DT

Updated the code to get and set the 'tpm_event_log_max_size' property
in the event_log.dtsi.

In this change, the maximum Event Log buffer size a

feat(fvp): add Event Log maximum size property in DT

Updated the code to get and set the 'tpm_event_log_max_size' property
in the event_log.dtsi.

In this change, the maximum Event Log buffer size allocated by BL1 is
passed to BL2, rather than both relying on the maximum Event Log buffer
size macro.

Change-Id: I7aa6256390872171e362b6f166f3f7335aa6e425
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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688ab57b14-Mar-2023 Mark Brown <broonie@kernel.org>

feat(gcs): support guarded control stack

Arm v9.4 introduces support for Guarded Control Stack, providing
mitigations against some forms of RPO attacks and an efficient mechanism
for obtaining the c

feat(gcs): support guarded control stack

Arm v9.4 introduces support for Guarded Control Stack, providing
mitigations against some forms of RPO attacks and an efficient mechanism
for obtaining the current call stack without requiring a full stack
unwind. Enable access to this feature for EL2 and below, context
switching the newly added EL2 registers as appropriate.

Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.

Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b

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ffc56bd017-Apr-2023 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge changes I43a9d83c,Ibfaa47fb into integration

* changes:
fix(intel): fix Agilex and N5X clock manager to main PLL C0
feat(intel): implement timer init divider via CPU frequency for N5X

8406447f02-Mar-2021 Markus Niebel <Markus.Niebel@tq-group.com>

feat(imx8): add support for debug uart on lpuart1

Needed for TQMa8Xx on MBa8Xx. With this changes it is
possible to build:

$ make PLAT=imx8qx IMX_DEBUG_UART=1 DEBUG_CONSOLE=1 bl31

Signed-off-by: M

feat(imx8): add support for debug uart on lpuart1

Needed for TQMa8Xx on MBa8Xx. With this changes it is
possible to build:

$ make PLAT=imx8qx IMX_DEBUG_UART=1 DEBUG_CONSOLE=1 bl31

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Change-Id: If380845b254f30fe919ebb33c86130597c4b8ad3

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72c3124f17-Apr-2023 Michal Simek <michal.simek@amd.com>

fix(zynqmp): remove unused PLAT_NUM_POWER_DOMAINS

Remove unused PLAT_NUM_POWER_DOMAINS macro. Macro is referenced by
docs/design/psci-pd-tree.rst but it is not used in any calculation
that's why it

fix(zynqmp): remove unused PLAT_NUM_POWER_DOMAINS

Remove unused PLAT_NUM_POWER_DOMAINS macro. Macro is referenced by
docs/design/psci-pd-tree.rst but it is not used in any calculation
that's why it is better to remove it.

Change-Id: I33f26cda6a4404061af5598ea4c751f64127e50a
Signed-off-by: Michal Simek <michal.simek@amd.com>

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0e9f54e513-Apr-2023 Michal Simek <michal.simek@amd.com>

feat(versal): switch to xlat_v2

Switch to v2 version to add support for dynamic mapping which is not
supported in v1. It can be used for run time DT mapping.

Change-Id: I3f27591caf944dc758cc45ee870

feat(versal): switch to xlat_v2

Switch to v2 version to add support for dynamic mapping which is not
supported in v1. It can be used for run time DT mapping.

Change-Id: I3f27591caf944dc758cc45ee870b9b5b3ff0a18d
Signed-off-by: Michal Simek <michal.simek@amd.com>

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8be2044617-Apr-2023 Michal Simek <michal.simek@amd.com>

fix(xilinx): remove asserts around arg0/arg1

The commit a6f340fe58b9 ("Introduce the new BL handover interface")
extended handoff to 4 registers instead of 2. Arguments arg0-3 are
not used by platfo

fix(xilinx): remove asserts around arg0/arg1

The commit a6f340fe58b9 ("Introduce the new BL handover interface")
extended handoff to 4 registers instead of 2. Arguments arg0-3 are
not used by platform code but in future they can be used for it.
But it doesn't make sense to checking their unused value.

Change-Id: I151e4b1574465409424453c054d937487086b79a
Signed-off-by: Michal Simek <michal.simek@amd.com>

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