1 /* 2 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* Versal IPI management enums and defines */ 9 10 #ifndef PLAT_IPI_H 11 #define PLAT_IPI_H 12 13 #include <ipi.h> 14 #include <stdint.h> 15 16 /********************************************************************* 17 * IPI agent IDs macros 18 ********************************************************************/ 19 #define IPI_ID_PMC 1U 20 #define IPI_ID_APU 2U 21 #define IPI_ID_RPU0 3U 22 #define IPI_ID_RPU1 4U 23 #define IPI_ID_3 5U 24 #define IPI_ID_4 6U 25 #define IPI_ID_5 7U 26 27 /********************************************************************* 28 * IPI message buffers 29 ********************************************************************/ 30 #define IPI_BUFFER_BASEADDR 0xFF3F0000U 31 32 #define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + 0x400U) 33 #define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + 0x200U) 34 35 #define IPI_BUFFER_TARGET_LOCAL_OFFSET 0x80U 36 #define IPI_BUFFER_TARGET_REMOTE_OFFSET 0x40U 37 38 #define IPI_BUFFER_MAX_WORDS 8 39 40 #define IPI_BUFFER_REQ_OFFSET 0x0U 41 #define IPI_BUFFER_RESP_OFFSET 0x20U 42 43 /********************************************************************* 44 * Platform specific IPI API declarations 45 ********************************************************************/ 46 47 /* Configure IPI table for versal */ 48 void versal_ipi_config_table_init(void); 49 50 /* IPI registers and bitfields */ 51 #define PMC_REG_BASE U(0xFF320000) 52 #define PMC_IPI_TRIG_BIT (1U << 1U) 53 #define IPI0_REG_BASE U(0xFF330000) 54 #define IPI0_TRIG_BIT (1U << 2U) 55 #define IPI1_REG_BASE U(0xFF340000) 56 #define IPI1_TRIG_BIT (1U << 3U) 57 #define IPI2_REG_BASE U(0xFF350000) 58 #define IPI2_TRIG_BIT (1U << 4U) 59 #define IPI3_REG_BASE U(0xFF360000) 60 #define IPI3_TRIG_BIT (1U << 5U) 61 #define IPI4_REG_BASE U(0xFF370000) 62 #define IPI4_TRIG_BIT (1U << 5U) 63 #define IPI5_REG_BASE U(0xFF380000) 64 #define IPI5_TRIG_BIT (1U << 6U) 65 66 #endif /* PLAT_IPI_H */ 67