Merge "feat(versal2): add SPMD support for SPMC at S-EL1" into integration

Merge changes from topic "xl/separate-bl2" into integration

* changes:
feat(fwu): documentation for BL2 separation
feat(fwu): separate bl2 image from rest of the FIP
feat(fwu): create flag for

Merge changes from topic "xl/separate-bl2" into integration

* changes:
feat(fwu): documentation for BL2 separation
feat(fwu): separate bl2 image from rest of the FIP
feat(fwu): create flag for BL2 separation

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feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONF

feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONFIG_ADDR` with a common macro `ARM_HW_CONFIG_ADDR` for
accessing the device tree blob base address.

For FVP the DT address is set to use `ARM_PRELOADED_DTB_BASE` if
provided, falling back to a default address otherwise.

This provides a consistent mechanism for Arm platforms to define and
override the DTB base address used during kernel handoff. It reduces the
chance of misconfiguration, and simplifies platform integration.

Change-Id: Ib668dbb1de9d42cf41c0b0ee9a316f054891752a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fwu): separate bl2 image from rest of the FIP

Create a separate partition for BL2 image in the GPT.
Modify the makefile to package BL2 image and its certificates
into a different FIP image.

Ch

feat(fwu): separate bl2 image from rest of the FIP

Create a separate partition for BL2 image in the GPT.
Modify the makefile to package BL2 image and its certificates
into a different FIP image.

Change-Id: I950883ea0c393a2a063ad9e51bb963cbac742705
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "fix(ti): specify allowable rcv_addr in mailbox" into integration

Merge "feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support" into integration

fix(gpt): fix fill_l1_cont_desc() function

GPT library function fill_l1_cont_desc() writes
contiguous descriptors and is called in a loop
by fill_l1_tbl() which fills out GPI entries in
in a single

fix(gpt): fix fill_l1_cont_desc() function

GPT library function fill_l1_cont_desc() writes
contiguous descriptors and is called in a loop
by fill_l1_tbl() which fills out GPI entries in
in a single L1 table. The loop terminates when
the address of the first granule in range 'first'
exceeds address of the last granule (inclusive)
'last'.
This patch fixes the issue when fill_l1_cont_desc()
was iterating through all matching contiguous block
sizes 512, 32 and 2MB in a loop and filling consecutive
smaller descriptors instead of filling a single one with
a maximum size. This resulted for memory region 0x80000000
of size 1.5GB (3*512MB)to be filled with 2 512MB, 8 32MB and
128 2MB contiguous descriptors instead of 3 512MB descriptors
with build option RME_GPT_MAX_BLOCK=512.
This patch also removes unused definition of ARM_PAS_GPI_ANY
macro in fvp_pas_def.h.

Change-Id: I9fcff512af306a57d17dee0bade74d2f3f79b5e9
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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Merge "fix(neoverse-rd): add console initialisation to BL31" into integration

fix(imx8mp): assign wdog1 to domain0 only

Normally, wdog1 is used by A53 side, and it should be stopped when
A53 domain enters STOP mode. After Power-on-Reset this watchdog is owned
by both M7 & A53

fix(imx8mp): assign wdog1 to domain0 only

Normally, wdog1 is used by A53 side, and it should be stopped when
A53 domain enters STOP mode. After Power-on-Reset this watchdog is owned
by both M7 & A53 side. This watchdog can only enter STOP mode only when
both A53 & M7 enter STOP mode. This is not reasonable as this watchdog
is only used by A53 side, so assign wdog1 to domain0(a53 side) only.

Change-Id: I4c04a8c7f3cba4713f410866c18fef88fcbe9f11
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

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chore(versal2): rename versal2 to Versal Gen 2

The term Versal2 should be updated to Versal Gen 2.

Change-Id: Iac94ef32604f88ec030bf95ec35484b72a0f7ffa
Signed-off-by: Prasad Kummari <prasad.kummari

chore(versal2): rename versal2 to Versal Gen 2

The term Versal2 should be updated to Versal Gen 2.

Change-Id: Iac94ef32604f88ec030bf95ec35484b72a0f7ffa
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge "feat(cpus): add support for Canyon CPU" into integration

Merge "fix(arm): increase reserved DRAM1 mem for NS images" into integration

feat(versal2): add SPMD support for SPMC at S-EL1

Added support for SPMD when SPMC is running at S-EL1 on Versal Gen 2
platform. Added DTB with manifest addresses to BL32 for proper
initialization.

feat(versal2): add SPMD support for SPMC at S-EL1

Added support for SPMD when SPMC is running at S-EL1 on Versal Gen 2
platform. Added DTB with manifest addresses to BL32 for proper
initialization. Added `plat_spmd_handle_group0_interrupt` to handle
Group0 interrupts in SPMD. Added a new manifest source file compliant
with FFA 1.0 specification in which load_address and entrypoint
points to BL32 base address.

Change-Id: I518e2e799d3b86fcd67f9fee0af42503ca705488
Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>

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Merge "fix(arm): re-enable console by default in BL31" into integration

fix(xilinx): fix missing security flag in suspend path

Suspend flow was always programming wakeup sources with a fixed
secure flag, regardless of whether the caller was secure or
non-secure. This ma

fix(xilinx): fix missing security flag in suspend path

Suspend flow was always programming wakeup sources with a fixed
secure flag, regardless of whether the caller was secure or
non-secure. This may cause incorrect behavior for non-secure
suspend requests.

Fix this by passing the caller's security state (flag) through
pm_client_suspend() and pm_client_set_wakeup_sources() to ensure
that wakeup sources are set with the correct context.

Fixes: <4697164a3fa8> ("plat: xilinx: versal: Mark IPI calls secure/non-secure")

Change-Id: I5fcf65788a54010b4759b0d08e4f54c6e5037e47
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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feat(zynqmp): mark IPI calls secure/non-secure

Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a n

feat(zynqmp): mark IPI calls secure/non-secure

Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.

The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.

Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(arm): increase reserved DRAM1 mem for NS images

Defconfig kernels are now approaching 50MB, making the previous 64MB
allocation for both the kernel and initrd insufficient. To accommodate
this g

fix(arm): increase reserved DRAM1 mem for NS images

Defconfig kernels are now approaching 50MB, making the previous 64MB
allocation for both the kernel and initrd insufficient. To accommodate
this growth, increase the reserved NS memory to 128MB.

Change-Id: Ifffdda4623ec7930e4c830a6a222933807d09882
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to

feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.

When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.

At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e

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Merge changes from topic "xlnx_misra_fix_gen_common" into integration

* changes:
fix(common): initialize the variables
fix(common): rename exit label
fix(common): add missing curly braces
fi

Merge changes from topic "xlnx_misra_fix_gen_common" into integration

* changes:
fix(common): initialize the variables
fix(common): rename exit label
fix(common): add missing curly braces
fix(common): add missing curly braces

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Merge changes from topic "xlnx_armclang_fix" into integration

* changes:
fix(versal2): move plat_core_pos_by_mpidr to asm
fix(versal-net): move plat_core_pos_by_mpidr to asm

Merge "fix(drtm): remove plat_system_reset()" into integration

feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
S

feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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Merge changes from topic "xlnx_misra_fix_gen_arm" into integration

* changes:
fix(arm-drivers): add missing curly braces
fix(arm): typecast operands to match data type
fix(arm-drivers): declar

Merge changes from topic "xlnx_misra_fix_gen_arm" into integration

* changes:
fix(arm-drivers): add missing curly braces
fix(arm): typecast operands to match data type
fix(arm-drivers): declare unused parameters as void

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Merge "feat(mt8189): add SPM low power mode" into integration

Merge changes I1e816dc9,I6550f2b9 into integration

* changes:
feat(mt8189): add UFS driver support
fix(mediatek): fix mtcmos build failure