fix(fiptool): move juno plat_fiptool.mk

plat_fiptool.mk files now need to be in tools/fiptool/plat_fiptool/, so
this file has been moved to the new location so that it is picked up
correctly by the

fix(fiptool): move juno plat_fiptool.mk

plat_fiptool.mk files now need to be in tools/fiptool/plat_fiptool/, so
this file has been moved to the new location so that it is picked up
correctly by the build system.

Change-Id: Id3596b08bc856362e300f3dfefcaab5d75b4c400
Signed-off-by: Rob Hughes <robert.hughes@arm.com>

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feat(versal-net): add the IPI CRC checksum macro support

Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.

Change-Id: I14dee4729f88c407bafdf1d6b46106459d8e22c4
Sign

feat(versal-net): add the IPI CRC checksum macro support

Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.

Change-Id: I14dee4729f88c407bafdf1d6b46106459d8e22c4
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge "fix(tegra210): mark bits [23:17] as zero for Fast SMCs" into integration

Merge changes from topics "plat_tests_scalability", "sb/tc-plat-tests" into integration

* changes:
test(tc): unify platform tests traces
test(tc): return test failures count for tfm-testsuite

Merge changes from topics "plat_tests_scalability", "sb/tc-plat-tests" into integration

* changes:
test(tc): unify platform tests traces
test(tc): return test failures count for tfm-testsuite
test(tc): move platform tests in their own function
test(tc): centralize platform error handling
refactor(tc): define PLATFORM_TESTS for scale

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fix(brcm): fix misspelled header inclusion guard

The header inclusion guard for some header for the Broadcom Stingray
board was misspelled.

Make the preprocessor symbol for the #ifndef and #define

fix(brcm): fix misspelled header inclusion guard

The header inclusion guard for some header for the Broadcom Stingray
board was misspelled.

Make the preprocessor symbol for the #ifndef and #define lines the
same, so that the double inclusion protection works as expected.

Change-Id: I19d73c854cd0689a248ce914ef35ae87c39ebf39
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat: define memory ranges for tc platform

In [1] we missed to update the SPMC manifest for the
TC platform, managing OPTEE as an SP.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-

feat: define memory ranges for tc platform

In [1] we missed to update the SPMC manifest for the
TC platform, managing OPTEE as an SP.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/20107

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I68c2e0da6e63216c827f77b5b86afe9f5813e62f

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test(tc): unify platform tests traces

Add some traces at the start and end of platform tests. These traces
are the same regardless of the set of platform tests we run (NV
counter tests / TF-M testsu

test(tc): unify platform tests traces

Add some traces at the start and end of platform tests. These traces
are the same regardless of the set of platform tests we run (NV
counter tests / TF-M testsuite / future set of tests).

This makes it easier to integrate these tests in the CI because we can
now have a unified "expect" script for all platform tests, instead of
having one dedicated "expect" script for each possible set of tests.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I5ec30a7a25d8a9a4a90e3338a9789acff7ad4843

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test(tc): return test failures count for tfm-testsuite

When running the "tfm-testsuite" set of platform tests, we now count
the number of failed tests (in addition to printing a test summary)
and re

test(tc): return test failures count for tfm-testsuite

When running the "tfm-testsuite" set of platform tests, we now count
the number of failed tests (in addition to printing a test summary)
and report that back to the caller,
i.e. tc_bl31_common_platform_setup().

This will be useful to consolidate the tests failure reporting code in
a subsequent patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I8e51f03869f3b2f264b6581b3bd2a53be0198057

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test(tc): move platform tests in their own function

This is a bit cleaner, as it avoids cluttering the normal boot execution
path. It also gives us the opportunity to mark the tests function with
th

test(tc): move platform tests in their own function

This is a bit cleaner, as it avoids cluttering the normal boot execution
path. It also gives us the opportunity to mark the tests function with
the __dead2 attribute, which inform both the compiler and the developer
that the test function never returns (since it suspends booting).

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I082a34a840ef791a2ac4c1f59b19b32aeb0a9ec7

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test(tc): centralize platform error handling

Note that this change only affects the platform tests execution
path. It has no impact on the normal boot flow.

Make individual test functions propagate

test(tc): centralize platform error handling

Note that this change only affects the platform tests execution
path. It has no impact on the normal boot flow.

Make individual test functions propagate an error code, instead of
calling the platform error handler at the point of failure. The latter
is now the responsibility of the caller - in this case
tc_bl31_common_platform_setup().

Note that right now, tc_bl31_common_platform_setup() does not look at
the said error code but this initial change opens up an opportunity to
centralize any error handling in tc_bl31_common_platform_setup(),
which we will seize in subsequent patches.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ib282b64039e0b1ec6e6d29476fbaa2bcd33cb0c7

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fix(tegra210): mark bits [23:17] as zero for Fast SMCs

Per SMCCC documentation, bits [23:17] must be zero for Fast
SMCs. Other values are reserved for future use. Ensure that
these bits are zeroes f

fix(tegra210): mark bits [23:17] as zero for Fast SMCs

Per SMCCC documentation, bits [23:17] must be zero for Fast
SMCs. Other values are reserved for future use. Ensure that
these bits are zeroes for TEGRA_SIP_PMC_COMMANDS.

Commit f8a35797 introduced a check to return error if these
bits are not zero, thus breaking Tegra210 platforms. This
patch fixes the anomaly.

Change-Id: I19edc3b33c999a6fee6b86184233fba146316466
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge "fix(n1sdp): add platform-specific power domain functions" into integration

Merge "fix(morello): add platform-specific power domain functions" into integration

Merge "fix(spmd): fix build error with spmd" into integration

fix(spmd): fix build error with spmd

Currently when we build with 'SPD=spmd SPMD_SPM_AT_SEL2=0'
options, this causes a build failure as
'plat_spmd_handle_group0_interrupt' is called irrespective of

fix(spmd): fix build error with spmd

Currently when we build with 'SPD=spmd SPMD_SPM_AT_SEL2=0'
options, this causes a build failure as
'plat_spmd_handle_group0_interrupt' is called irrespective of
'SPMD_SPM_AT_SEL2' usage in 'spmd_group0_interrupt_handler_nwd'

So make 'plat_spmd_handle_group0_interrupt' dummy implementation
available just when spmd is enabled and SPMC_AT_EL3 is disabled.

Change-Id: Iaccd38faab81671c98f9165f318145187dca9bc2
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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build(fpga): reduce cpu_libs to tc and neoverse

Change-Id: I20e88d5e712dafa7364b7932b8b4aaa9051bea55
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

Merge changes I5bb43cb0,I6aebe2ca,Ib59df16a,I9d037ab2,I9df5a465, ... into integration

* changes:
fix(msm8916): add timeout for crash console TX flush
style(msm8916): use size macros
feat(msm89

Merge changes I5bb43cb0,I6aebe2ca,Ib59df16a,I9d037ab2,I9df5a465, ... into integration

* changes:
fix(msm8916): add timeout for crash console TX flush
style(msm8916): use size macros
feat(msm8916): expose more timer frames
fix(msm8916): drop unneeded initialization of CNTACR
build(msm8916): disable unneeded workarounds
fix(msm8916): flush dcache after writing msm8916_entry_point
fix(msm8916): print \r before \n on UART console

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Merge changes I1bfa797e,I0ec7a70e into integration

* changes:
fix(tree): correct some typos
fix(rockchip): use semicolon instead of comma

Merge changes from topic "mp/feat_ras" into integration

* changes:
refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED
refactor(ras): replace RAS_EXTENSION with FEAT_RAS

fix(msm8916): add timeout for crash console TX flush

Resetting the UART DM controller while there are still remaining
characters in the FIFO often results in corruption on the UART receiver
side. To

fix(msm8916): add timeout for crash console TX flush

Resetting the UART DM controller while there are still remaining
characters in the FIFO often results in corruption on the UART receiver
side. To avoid this the msm8916 crash console implementation tries to
wait until the TX FIFO is empty.

Unfortunately this might spin forever if the transmitter was disabled
before it has fully finished transmitting. In this case the TXEMT bit
console_uartdm_core_flush is waiting for will never get set.

There seems to be no good way to detect if the transmitter is actually
enabled via the status registers. However, the TX FIFO is fairly small
and should not take too long to get flushed, so fix this by simply
limiting the amount of iterations with a short timeout.

Move the code to console_uartdm_core_init to ensure that this always
happens before resetting the transmitter (also during initialization).

Change-Id: I5bb43cb0b6c029bcd15e253d60d36c0b310e108b
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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style(msm8916): use size macros

Use the pre-defined size macros (SZ_*) for more clarity and to avoid
having to add comments to each size represented by hexadecimal numbers.

Change-Id: I6aebe2caf136

style(msm8916): use size macros

Use the pre-defined size macros (SZ_*) for more clarity and to avoid
having to add comments to each size represented by hexadecimal numbers.

Change-Id: I6aebe2caf1365279670955b9b507dec7d7b04457
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): expose more timer frames

The memory-mapped generic timer on msm8916 has 7 timer frames, but
currently only one is exposed for usage in the non-secure world.

The platform port is curr

feat(msm8916): expose more timer frames

The memory-mapped generic timer on msm8916 has 7 timer frames, but
currently only one is exposed for usage in the non-secure world.

The platform port is currently only designed to be used as minimal PSCI
implementation, without secure world that could make use of the other
timer frames. Let's make all of them available to the normal world.

If needed this could still be changed later by reserving some timer
frames conditionally to a specific SPD being enabled in the build.

Change-Id: Ib59df16aa1fd3dbc875ab6369c133737830c98c6
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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fix(msm8916): drop unneeded initialization of CNTACR

Normal world software is responsible to initialize CNTACR as needed.
There is no existing software for msm8916 that depends on having this
initia

fix(msm8916): drop unneeded initialization of CNTACR

Normal world software is responsible to initialize CNTACR as needed.
There is no existing software for msm8916 that depends on having this
initialization in BL31 so drop it before anything starts to rely on it.

Related issue: https://github.com/ARM-software/tf-issues/issues/170

Change-Id: I9d037ab218c0c1c8a5d5523722013eba531f4728
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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build(msm8916): disable unneeded workarounds

The Cortex-A53 cores used in the msm8916 platform are not affected by
CVE-2017-5715 and CVE-2022-23960, so disable the workarounds for them
to drop the u

build(msm8916): disable unneeded workarounds

The Cortex-A53 cores used in the msm8916 platform are not affected by
CVE-2017-5715 and CVE-2022-23960, so disable the workarounds for them
to drop the unused code from the compiled binary.

Change-Id: I9df5a4657c4fd90702b4db4e82d4ee1a2f60303c
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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fix(msm8916): flush dcache after writing msm8916_entry_point

msm8916_entry_point is read with caches off (and even from two
different physical addresses when read through the "boot remapper"),
so it

fix(msm8916): flush dcache after writing msm8916_entry_point

msm8916_entry_point is read with caches off (and even from two
different physical addresses when read through the "boot remapper"),
so it should be flushed to RAM after writing it.

Change-Id: I5c8193954bb28043b0a46fb2038f629bd8796c74
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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