Merge "feat(intel): add intel_rsu_update() to sip_svc_v2" into integration

fix(zynqmp): type cast addresses to fix overflow issue

Type cast the build time base and size argument to unsigned integer
and the limit derived from these two as unsigned long to avoid
size overflo

fix(zynqmp): type cast addresses to fix overflow issue

Type cast the build time base and size argument to unsigned integer
and the limit derived from these two as unsigned long to avoid
size overflow issue during build.

For zynqmp platform, calculating the limit without typecasting results
in build error as follows

make -j DEBUG=0 RESET_TO_BL31=1 PLAT=zynqmp \
ZYNQMP_ATF_MEM_BASE=0x70000000 ZYNQMP_ATF_MEM_SIZE=0x10000000 \
XILINX_OF_BOARD_DTB_ADDR=0x100000 bl31

plat/xilinx/zynqmp/include/platform_def.h:51:62:
error: integer overflow in expression of type 'int' results
in '-2147483648' [-Werror=overflow]
51 | # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE)

Change-Id: Id093a50e748884d4fba65626e94f361f6c23cecc
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function

Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function
fix(gic600): fix gic600 maximum SPI ID

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fix(n1sdp): fix spi_ids range for n1sdp multichip boot

According to GIC-600 TRM, it supports upto 960 SPIs.
This patch configures the SPI IDs range to 32-991, and distributes
them equally across bot

fix(n1sdp): fix spi_ids range for n1sdp multichip boot

According to GIC-600 TRM, it supports upto 960 SPIs.
This patch configures the SPI IDs range to 32-991, and distributes
them equally across both the chips.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I814cdadb59c8765c239ae0375e547718b7f208ff

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feat(plat/qemu): add sdei support for QEMU

Add sdei support for QEMU, this is to let jailhouse Hypervisor
use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Note: T

feat(plat/qemu): add sdei support for QEMU

Add sdei support for QEMU, this is to let jailhouse Hypervisor
use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Note: To enable SDEI in QEMU, it needs to set "SDEI_SUPPORT=1
EL3_EXCEPTION_HANDLING=1" when compiling.

Signed-off-by: Dongjiu Geng <gengdongjiu1@gmail.com>
Change-Id: Ia7f9c5a0db36da03e5c6e6fb1270281f19924d77

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feat(juno): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Ch

feat(juno): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I5609da000bbfc8a1503c298550ae3b0ba881fc96

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feat(fvp): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Cha

feat(fvp): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I14310c80033a1142a94c0c4b54d63331479b643d

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Merge "feat(ast2700): add Aspeed AST2700 platform support" into integration

feat(intel): add intel_rsu_update() to sip_svc_v2

Add smc function id for intel_rsu_update() in sip_svc_v2. For temporarily
saving the RSU application image address before a cold reset is
issued.

S

feat(intel): add intel_rsu_update() to sip_svc_v2

Add smc function id for intel_rsu_update() in sip_svc_v2. For temporarily
saving the RSU application image address before a cold reset is
issued.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43bc7bd5aa5fa9238bceba1d826bf0a34ff87adb

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fix(versal): add missing irq mapping for wakeup src

The commit 0ec6c31320c6 provides irq to device index mapping
which is required to check for IRQs and set peripheral as a
wake source if IRQ is ena

fix(versal): add missing irq mapping for wakeup src

The commit 0ec6c31320c6 provides irq to device index mapping
which is required to check for IRQs and set peripheral as a
wake source if IRQ is enabled. But in that commit some IRQ
numbers are missed. Because of that, wakeup using some
peripheral interrupts will not work. Add those missing IRQ
numbers.

Fixes: 0ec6c31320c6 ("feat(versal): replace irq array with switch case")
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Icbc773050c328be253702e63e7cf8450c7dee133

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Merge "fix(zynqmp): fix prepare_dtb() memory description" into integration

Merge changes from topic "psci-osi" into integration

* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update p

Merge changes from topic "psci-osi" into integration

* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update pwr_domain_suspend

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feat(ast2700): add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the doc

feat(ast2700): add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the documents.

Change-Id: I1796f7aae5ed2d1799e91fabb8949607959cd9b3
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

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Merge "chore(xilinx): replace ATF with TFA" into integration

Merge "fix(zynqmp): fix sdei arm_validate_ns_entrypoint()" into integration

fix(zynqmp): fix prepare_dtb() memory description

The commit 8ce2fbffe37d ("fix(zynqmp): fix BLXX memory limits for user
defined values") fixed logic around BL31_LIMIT but didn't update
prepare_dtb(

fix(zynqmp): fix prepare_dtb() memory description

The commit 8ce2fbffe37d ("fix(zynqmp): fix BLXX memory limits for user
defined values") fixed logic around BL31_LIMIT but didn't update
prepare_dtb() which is also using +1 logic.

Change-Id: Ia6de10d992a552ca9cfa39c14261b0f94cda95ec
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes from topic "bk/clearups" into integration

* changes:
chore(rme): add make rule for SPD=spmd
chore(bl1): remove redundant bl1_arch_next_el_setup
chore(docs): remove control regist

Merge changes from topic "bk/clearups" into integration

* changes:
chore(rme): add make rule for SPD=spmd
chore(bl1): remove redundant bl1_arch_next_el_setup
chore(docs): remove control register setup section
chore(pauth): remove redundant pauth_disable_el3() call

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fix(zynqmp): fix sdei arm_validate_ns_entrypoint()

Don't use BL31_LIMIT macro for validation logic directly but clearly
mark BL31_LIMIT as 64bit address to avoid compilation error when
-Werror=logic

fix(zynqmp): fix sdei arm_validate_ns_entrypoint()

Don't use BL31_LIMIT macro for validation logic directly but clearly
mark BL31_LIMIT as 64bit address to avoid compilation error when
-Werror=logical-op is passed.

Likely caused by ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE is in 64bit
logic 0x100000000 and compiler handles it as 32bit value. That's why
error is shown.

Use uint64_t variable for limit and also for base.

Here is command line to replicate this issue:
make realclean; make -j PLAT=zynqmp DEBUG=1 RESET_TO_BL31=1 \
SPD=tspd SDEI_SUPPORT=1 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 \
ZYNQMP_ATF_MEM_SIZE=0x00040000 all -Werror=logical-op

Also error which is coming:
plat/xilinx/zynqmp/zynqmp_sdei.c: In function
'arm_validate_ns_entrypoint':
plat/xilinx/zynqmp/zynqmp_sdei.c:19:40: error: logical 'or' of
collectively exhaustive tests is always true [-Werror=logical-op]
19 | return (entrypoint < BL31_BASE ||
entrypoint > BL31_LIMIT) ? 0 : -1;

Change-Id: Ie1f1b4d2cd94b977aebb72786ecace0b062da418
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge changes from topic "st-fixes" into integration

* changes:
fix(spi-nand): add Quad Enable management
fix(st-clock): disabling CKPER clock is not functional on stm32mp13
fix(st-uart): skip

Merge changes from topic "st-fixes" into integration

* changes:
fix(spi-nand): add Quad Enable management
fix(st-clock): disabling CKPER clock is not functional on stm32mp13
fix(st-uart): skip console flush if UART is disabled
fix(st): flush UART at the end of uart_read()
fix(stm32mp1): use the BSEC nodes compatible for stm32mp13
fix(stm32mp13-fdts): correct the BSEC nodes compatible
fix(stm32mp1-fdts): move /omit-if-no-ref/ to overlay files
fix(stm32mp1): properly check PSCI functions return

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Merge "refactor(fvp): nv ctr addr static helper function" into integration

chore(xilinx): replace ATF with TFA

Since the Arm Trusted Firmware(ATF) has been renamed to Trusted
Firmware-A (TF-A), replace all the instances of ATF from code comments,
macros, variables and func

chore(xilinx): replace ATF with TFA

Since the Arm Trusted Firmware(ATF) has been renamed to Trusted
Firmware-A (TF-A), replace all the instances of ATF from code comments,
macros, variables and functions to TF-A.

Change-Id: Iab448d96158612a3effb4e49943f8d6cb43aaad5
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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fix(mediatek): support saving/restoring GICR registers

The GICR_IPRIORITYR[x] registers are not saved or restored in the
original design. When the kernel tries to use them, such as the
pseudo-NMI, i

fix(mediatek): support saving/restoring GICR registers

The GICR_IPRIORITYR[x] registers are not saved or restored in the
original design. When the kernel tries to use them, such as the
pseudo-NMI, it leads crashes and freezes. This patch adds support for
saving/restoring GICR registers.

Change-Id: I9718a75a1410ca14826710dfdf5f3226299fa6e2
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>

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Merge changes from topic "version/0.1-gic" into integration

* changes:
feat(qemu-sbsa): handle GIC base
feat(qemu-sbsa): handle platform version

Merge changes I21d65a88,I949cfce9,If4249f22,Id0451bd1,I9e930070, ... into integration

* changes:
feat(mediatek): add APU watchdog timeout control
feat(mt8188): add emi mpu protection for APU sec

Merge changes I21d65a88,I949cfce9,If4249f22,Id0451bd1,I9e930070, ... into integration

* changes:
feat(mediatek): add APU watchdog timeout control
feat(mt8188): add emi mpu protection for APU secure memory
feat(mt8188): add devapc setting of apusys rcx
feat(mt8188): add backup/restore function when power on/off
feat(mediatek): add APU bootup control smc call
feat(mt8188): enable apusys mailbox mpu protect
feat(mt8188): enable apusys domain remap
feat(mt8188): add apusys ao devapc setting
feat(mt8188): increase TZRAM_SIZE from 192KB to 256KB

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feat(mediatek): add APU watchdog timeout control

Add APU watchdog timeout control.

Change-Id: I21d65a88d20b6b2752a75f74487b5fe6596ebdf7
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signe

feat(mediatek): add APU watchdog timeout control

Add APU watchdog timeout control.

Change-Id: I21d65a88d20b6b2752a75f74487b5fe6596ebdf7
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>

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