feat(versal-net): add cluster check in handoff parameters

Versal NET platform supports multiple cpu clusters and the cluster
information for every partition contaning firmware component
is being pas

feat(versal-net): add cluster check in handoff parameters

Versal NET platform supports multiple cpu clusters and the cluster
information for every partition contaning firmware component
is being passed by PLM through handoff parameters to TF-A.

Function implementation for getting cluster value for the firmware
component partition in TF-A and check for the firmware component
being targeted to be executed on Cluster 0.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I8622699e12b0a9cda83ae46e2ad0a038ca377fda

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feat(versal-net): get the handoff params using IPI

Use the IPI command GET_HANDOFF_PARAM to get the PLM to TF-A handoff
parameters. The BL32/BL33 information from the handoff parameters will
be used

feat(versal-net): get the handoff params using IPI

Use the IPI command GET_HANDOFF_PARAM to get the PLM to TF-A handoff
parameters. The BL32/BL33 information from the handoff parameters will
be used by TF-A.

If no valid PLM to TF-A handoff parameters are available then,
the TF-A will fall back to the build time information or defaults
set in the TF-A for BL32/BL33.

Once the bootmode identification is supported the default configuration
will be done only for JTAG and for all other bootmodes PLM to TF-A
handoff parameters will be used.

Change-Id: Ia2204fe30fea6f32b4e5d2610820217e6ed23e4d
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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chore(xilinx): replace fsbl with xbl

The handoff functionality is common between platforms and all
platforms do not use fsbl terminology. Renaming handoff related code
to generic naming.

Signed-off

chore(xilinx): replace fsbl with xbl

The handoff functionality is common between platforms and all
platforms do not use fsbl terminology. Renaming handoff related code
to generic naming.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ic250af927f33c4fecbc2e6bab01b83a6dd2aab52
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(imx93): add OPTEE support

Add OPTEE support for imx93 platform.
Add support for the device tree overlay.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Jacky Bai <ping.bai

feat(imx93): add OPTEE support

Add OPTEE support for imx93 platform.
Add support for the device tree overlay.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I99c7819665f8f746b0dd7941fb83dbec9d8651de

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feat(imx93): protect OPTEE memory to secure access only

Configure TRDC_NIC MRC0 to protect OPTEE DDR memory to secure
access only from A55 cores and other peripherals' masters.

Signed-off-by: Ye Li

feat(imx93): protect OPTEE memory to secure access only

Configure TRDC_NIC MRC0 to protect OPTEE DDR memory to secure
access only from A55 cores and other peripherals' masters.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ie5363ecff67e3183fbde998a0bba93df4c099e1f

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feat(imx93): add cpuidle and basic suspend support

Add cpuidle and basic suspend support. For now only
core & cluster will be put into low power mode when
system suspend.

Signed-off-by: Jacky Bai <

feat(imx93): add cpuidle and basic suspend support

Add cpuidle and basic suspend support. For now only
core & cluster will be put into low power mode when
system suspend.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ife0b6dc48738ae7a2322d6a7f6342ffe15d35342

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feat(imx93): add reset & poweroff support

Add system reset & system power off support on i.MX93.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id180461541a1b3f73b2dc00c9cad33f484c145e6

feat(imx93): allow SoC masters access to system TCM

SoC masters should be allowed to access to system TCM. For example,
This makes it possible for M core to run ENET/ENET_QOS examples whose
DMA acce

feat(imx93): allow SoC masters access to system TCM

SoC masters should be allowed to access to system TCM. For example,
This makes it possible for M core to run ENET/ENET_QOS examples whose
DMA accesses system TCM in single boot mode.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I4149e047e49a66699015f92c25a7f5334a972835

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feat(imx93): update the ocram trdc config for did10

Update the ocram trdc config for DID10 to make sure NPU
can access the OCRAM. Need to fine tune the OCRAM config
in the future.

Signed-off-by: Ja

feat(imx93): update the ocram trdc config for did10

Update the ocram trdc config for DID10 to make sure NPU
can access the OCRAM. Need to fine tune the OCRAM config
in the future.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Iaa8518e0bea2c3939292202c116bd08444e07698

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feat(imx93): add the basic support

Add the basic boot support for i.MX93.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I48bac2fd8bf2145133edf101a315908266c3f50a

Merge changes from topic "gr/cpu_rename" into integration

* changes:
chore: rename hayes to a520
chore: rename hunter to a720
chore: rename hunter_elp to cortex-x4

chore: rename hayes to a520

Rename Cortex-hayes to Cortes-A520

Change-Id: Ic574b55b1aaf11b5bf7b583e244245e7b54bdb22
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

chore: rename hunter to a720

Rename cortex_hunter to cortex_a720

Change-Id: Id4e0e2cd47051c2e92b3f16373ea06ef4df1d75f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge "fix(fvp): adjust BL31 maximum size as per total SRAM size" into integration

chore: rename hunter_elp to cortex-x4

Rename hunter_elp to cortex-x4

Change-Id: I78c8c009d7bee14b4793dc1d950ed81273216831
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

fix(fvp): adjust BL31 maximum size as per total SRAM size

Adjusted BL31 maximum size as per total SRAM size.

Change-Id: Ifdfdedb8af3e001cebba8e60c973f3c72be11652
Signed-off-by: Manish V Badarkhe <M

fix(fvp): adjust BL31 maximum size as per total SRAM size

Adjusted BL31 maximum size as per total SRAM size.

Change-Id: Ifdfdedb8af3e001cebba8e60c973f3c72be11652
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "docs: remove deprecated tc0 from list of supported FVPs" into integration

feat(qemu_sbsa): handle GIC ITS address

Read data from DeviceTree provided by QEMU, provide via SMC
to the next firmware level.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Cha

feat(qemu_sbsa): handle GIC ITS address

Read data from DeviceTree provided by QEMU, provide via SMC
to the next firmware level.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I95c5f00ab2cca3b5fda122dcc8d7704a7a82059b

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feat(mt8195): increase TZRAM

We need 4k more memory.

Change-Id: I760e949c2f80a79e111060b24855c0a6a5bfdfaa
Signed-off-by: Yi Chou <yich@google.com>

Merge "refactor(build): merge march32/64 directives" into integration

chore(xilinx): reorder include files as per TF-A guidelines

This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rear

chore(xilinx): reorder include files as per TF-A guidelines

This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rearranged to ensure a consistent and
organized structure in the codebase, facilitating better
readability and maintainability.

https: //trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#headers-and-inclusion
https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/script/static-checks/

For example, to run header check:
/tf-a-ci-scripts/script/static-checks/check-include-order.py --tree ${PWD} > Includefileorder.txt

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ia5802722e69859596b94f31ec40755adbf7d865b

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Merge "chore(xilinx): follow kernel doc format for functional documentation" into integration

Merge "feat(fvp): allow configurable FVP Trusted SRAM size" into integration

Merge changes from topic "RAS_REFACTORING" into integration

* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memor

Merge changes from topic "RAS_REFACTORING" into integration

* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memory region
feat(plat/arm): firmware first error handling support for base RAMs
feat(plat/arm): update common platform RAS implementation
feat(plat/sgi): remove RAS setup call from common code
refactor(plat/sgi): deprecate DMC-620 RAS support
fix(plat/common): register PLAT_SP_PRI only if not already registered
fix(plat/sgi): update PLAT_SP_PRI macro definition
fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority

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docs: remove deprecated tc0 from list of supported FVPs

TC0 is now a deprecated platform so remove it from the list
of supported FVPs as well as throwing an error if it is attempted
to be built.

Si

docs: remove deprecated tc0 from list of supported FVPs

TC0 is now a deprecated platform so remove it from the list
of supported FVPs as well as throwing an error if it is attempted
to be built.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Id013fcecbe20700611463ef9eab8cb3ae09071cc

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