fix(ast2700): add device mapping for coherent memory

The coherent memory should be mapped as Device nGnRnE.
This fix adds the missing MMU attributes for coherent memory
if enabled.

Signed-off-by: C

fix(ast2700): add device mapping for coherent memory

The coherent memory should be mapped as Device nGnRnE.
This fix adds the missing MMU attributes for coherent memory
if enabled.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I90b8de167c48f03392c9740f88f4b1e7b073a82d

show more ...

feat(ti): query firmware for suspend capability

Instead of hardcoding this at build time we can ask the firmware if
suspend is supported and if not disable accordingly. Then remove compile-
time ifd

feat(ti): query firmware for suspend capability

Instead of hardcoding this at build time we can ask the firmware if
suspend is supported and if not disable accordingly. Then remove compile-
time ifdefs.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ib966c04c0bdb79a82e8d890cec5e65d883acd6e3

show more ...

feat(ti): add TI-SCI query firmware capabilities command support

This TISCI API is used to retrieve the firmware capabilities of the
currently running system-firmware.

Signed-off-by: Andrew Davis <

feat(ti): add TI-SCI query firmware capabilities command support

This TISCI API is used to retrieve the firmware capabilities of the
currently running system-firmware.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I55402dcf876e997eb21bb1f31c725e167c507c47

show more ...

feat(ti): remove extra core counts in cluster 2 and 3

No K3 SoC supported by this TARGET_BOARD has any cluster
2 or 3 cores. Remove these to save some memory.

Signed-off-by: Andrew Davis <afd@ti.co

feat(ti): remove extra core counts in cluster 2 and 3

No K3 SoC supported by this TARGET_BOARD has any cluster
2 or 3 cores. Remove these to save some memory.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I27868a2f3aac25fa0fdec56847e273d88f0d9a87

show more ...

Merge changes from topic "gpt_updates" into integration

* changes:
refactor(arm): use gpt_partition_init
feat(partition): add interface to init gpt
refactor(partition): convert warn to verbose

Merge changes from topic "gpt_updates" into integration

* changes:
refactor(arm): use gpt_partition_init
feat(partition): add interface to init gpt
refactor(partition): convert warn to verbose
feat(partition): add support to use backup GPT header
refactor(partition): get GPT header location from MBR
feat(arm): add IO policy to use backup gpt header
feat(tbbr): add image id for backup GPT

show more ...

Merge "feat(cpus): add support for Travis CPU" into integration

Merge "fix(ti): align static device region addresses to reduce MMU table count" into integration

refactor(arm): use gpt_partition_init

Current interface partition_init accepts GPT image id and parses the
GPT image but doesn't return any error on failure.

So use gpt_partition_init which implici

refactor(arm): use gpt_partition_init

Current interface partition_init accepts GPT image id and parses the
GPT image but doesn't return any error on failure.

So use gpt_partition_init which implicitly initialises with GPT image
ID and returns a value.

Change-Id: I63280aa672388f1f8d9dc377ae13002c9f861f03
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

feat(partition): add support to use backup GPT header

Currently we just use primary GPT header which is located in second
entry after MBR header, but if this block is corrupted or CRC
mismatch occur

feat(partition): add support to use backup GPT header

Currently we just use primary GPT header which is located in second
entry after MBR header, but if this block is corrupted or CRC
mismatch occurs we could try to use the backup GPT header located at
LBAn and GPT entries following this from LBA-33.

Add suitable warning messages before returning any errors to identify
the cause of issue.

Change-Id: I0018ae9eafbacb683a18784d2c8bd917c70f50e1
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

feat(arm): add IO policy to use backup gpt header

Add a IO block spec to use GPT backup header if primary fails.
Currently we use only the primary gpt header which is in the second
block(LBA-1) afte

feat(arm): add IO policy to use backup gpt header

Add a IO block spec to use GPT backup header if primary fails.
Currently we use only the primary gpt header which is in the second
block(LBA-1) after the MBR block(LBA-0) so we restrict IO access to
primary gpt header and its entries.

But we plan to use backup GPT which is the last block of the
partition (LBA-n) in case our primary GPT header fails verification
or is corrupted.

Offset and length of the block spec will be updated runtime from
partition driver after parsing MBR data.

Change-Id: Id1d49841d6f4cbcc3248af19faf2fbd8e24a8ba1
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

feat(handoff): port BL31-BL33 interface to fw handoff framework

The firmware handoff framework is a light weight mechanism for sharing
information between bootloader stages. Add support for this fra

feat(handoff): port BL31-BL33 interface to fw handoff framework

The firmware handoff framework is a light weight mechanism for sharing
information between bootloader stages. Add support for this framework at
the handoff boundary between runtime firmware BL31 and NS software on FVP.

Change-Id: Ib02e0e4c20a39e32e06da667caf2ce5a28de1e28
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

refactor(fvp): do not use RSS platform token and attestation key APIs

Since FVP does not support RSS, RSS APIs used to provide the hardcoded
platform token and attestation key. However, that seems t

refactor(fvp): do not use RSS platform token and attestation key APIs

Since FVP does not support RSS, RSS APIs used to provide the hardcoded
platform token and attestation key. However, that seems to be causing
un-necessary mandating of some PSA crypto definitions, that doesn't
seem appropriate.
Hence to retrieve platform token and realm attestation key, these
RSS APIs calls have been replaced with hardcoded information.

Change-Id: I5fd091025e3444a698b9d387763ce20db6b13ae1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

feat(cpus): add support for Travis CPU

Adding basic CPU library code to support Travis CPU

Change-Id: I3c85e9fab409325d213978888a8f6d6949291258
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.

feat(cpus): add support for Travis CPU

Adding basic CPU library code to support Travis CPU

Change-Id: I3c85e9fab409325d213978888a8f6d6949291258
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

show more ...

feat(fvp): increase BL1 RW area for PSA_CRYPTO implementation

When using PSA Crypto API, few algorithms like ECDSA require a
larger BL1 RW area. Hence added an additional BL1 RW page when
PSA_CRYPTO

feat(fvp): increase BL1 RW area for PSA_CRYPTO implementation

When using PSA Crypto API, few algorithms like ECDSA require a
larger BL1 RW area. Hence added an additional BL1 RW page when
PSA_CRYPTO is selected.

Change-Id: Id6994667641a0b1e36b6a356d7c39a125d62ac01
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

fix(ti): align static device region addresses to reduce MMU table count

Align our device memory regions to the next highest MMU table level (LV2).
This allows the xlat_tables library code to use a s

fix(ti): align static device region addresses to reduce MMU table count

Align our device memory regions to the next highest MMU table level (LV2).
This allows the xlat_tables library code to use a single entry in the
higher order table, vs having to create a new table for LV3 entries.

This reduces our tables to just 4: 2 LV2 and 1 LV3 plus 1 spare in case
alignment changes ever cause one to be split. This saves 24KB of our
128KB total TF-A SRAM (~18%!).

While here, as USE_COHERENT_MEM does not change MAX_XLAT_TABLES but
does change our total MAX_MMAP_REGIONS, move that check accordingly.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I4cb8e3b2cc3d05c6c9a84d887dd6ec56bde7a786

show more ...

Merge "fix(mpam): refine MPAM initialization and enablement process" into integration

Merge "fix(build): convert tabs to spaces" into integration

fix(mpam): refine MPAM initialization and enablement process

Restricts MPAM to only NS world and enables trap to EL3 for access of
MPAM registers from lower ELs of Secure and Realm world.

This patc

fix(mpam): refine MPAM initialization and enablement process

Restricts MPAM to only NS world and enables trap to EL3 for access of
MPAM registers from lower ELs of Secure and Realm world.

This patch removes MPAM enablement from global context and adds it to
EL3 State context which enables/disables MPAM during world switches.
Renamed ENABLE_MPAM_FOR_LOWER_ELS to ENABLE_FEAT_MPAM and
removed mpam_init_el3() as RESET behaviour is trapping.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I131f9dba5df236a71959b2d425ee11af7f3c38c4

show more ...

Merge "feat(mt8195): increase TZRAM" into integration

Merge "feat(st): update STM32MP DT files" into integration

Merge changes from topic "st_remove_shm" into integration

* changes:
docs(stm32mp15): mark STM32MP15_OPTEE_RSV_SHM deprecated
feat(stm32mp15): disable OP-TEE shared memory

Merge "fix(st): properly check LOADADDR" into integration

Merge changes Ia66dd232,Ie0ddbe0b,Idd191614 into integration

* changes:
fix(rcar3-drivers): update DDR setting
fix(rcar3): fix CPG register code comment
fix(rcar3): update Draak and Eagle boar

Merge changes Ia66dd232,Ie0ddbe0b,Idd191614 into integration

* changes:
fix(rcar3-drivers): update DDR setting
fix(rcar3): fix CPG register code comment
fix(rcar3): update Draak and Eagle board IDs

show more ...

Merge changes from topic "gcc_linker_aarch32" into integration

* changes:
feat(st): support gcc as linker
fix(build): allow gcc linker on Aarch32 platforms

fix(build): convert tabs to spaces

Convert any used tabs in arch_features.mk to spaces to avoid makefile
build issues. Only recipes should be indented with tabs.

ENABLE_TRBE_FOR_NS should be enable

fix(build): convert tabs to spaces

Convert any used tabs in arch_features.mk to spaces to avoid makefile
build issues. Only recipes should be indented with tabs.

ENABLE_TRBE_FOR_NS should be enabled only for aarch64 but accidentally
its enabled for aarch32 as well in FVP makefile.

Change-Id: Iee913a04d6b60a4738183a17421754c2638e8e6d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...