feat(tc): add DPE context handle node to device tree

Child software components are inheriting their first valid
DPE context handle from their parent components (who loaded
and measured them). The co

feat(tc): add DPE context handle node to device tree

Child software components are inheriting their first valid
DPE context handle from their parent components (who loaded
and measured them). The context handle is shared through
the device tree object the following way:
- BL1 -> BL2 via TB_FW_CONFIG
- BL2 -> BL33 via NT_FW_CONFIG

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I9bf7808fb13a310ad7ca1895674a0c7e6725e08b

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feat(tc): add DPE backend to the measured boot framework

The client platform relies on the DICE attestation
scheme. RSS provides the DICE Protection Environment
(DPE) service. TF-A measured boot fra

feat(tc): add DPE backend to the measured boot framework

The client platform relies on the DICE attestation
scheme. RSS provides the DICE Protection Environment
(DPE) service. TF-A measured boot framework supports
multiple backends. A given platform always enables
the corresponding backend which is required by the
attestation scheme.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Idc3360d0d7216e4859e99b5db3d377407e0aeee5

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refactor(tc): align image identifier string macros

Macros were renamed, align with new names.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Id7a556da34381618577fed4039d9ca957754cd7c

refactor(fvp): align image identifier string macros

Macros were renamed, align with new names.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I85d03164f580d9c41b7955482914d20188e559e5

refactor(imx8m): align image identifier string macros

Macros were renamed, align with new names.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I26be3bc52e176898700568fab5f6c19678978797

refactor(qemu): align image identifier string macros

Macros were renamed, align with new names.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Iefcbf4aac9ce4b21f49a633749703f93d4e34250

Merge changes from topic "sm/framework_optimize" into integration

* changes:
chore: rearrange the fvp_cpu_errata.mk file
fix(cpus): add erratum 2701951 to Cortex-X3's list
refactor(errata-abi)

Merge changes from topic "sm/framework_optimize" into integration

* changes:
chore: rearrange the fvp_cpu_errata.mk file
fix(cpus): add erratum 2701951 to Cortex-X3's list
refactor(errata-abi): workaround platforms non-arm interconnect
refactor(errata-abi): optimize errata ABI using errata framework

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Merge "fix(el3-spmc): add datastore linker script markers" into integration

chore: rearrange the fvp_cpu_errata.mk file

Change-Id: I3959bdf5852c5714f2238f61493a931b3c857a20
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

fix(cpus): add erratum 2701951 to Cortex-X3's list

Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Corte

fix(cpus): add erratum 2701951 to Cortex-X3's list

Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Cortex-A715 in the errata ABI files.
Fixed this by adding it to the Cortex-X3 list.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I6ffaf4360a4a2d0a23c253a2326c178e010c8e45
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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refactor(errata-abi): workaround platforms non-arm interconnect

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level

refactor(errata-abi): workaround platforms non-arm interconnect

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level
based on arm/non-arm interconnect IP flag. The ABI helps assist the
Kernel in the process of mitigation for the following errata:

Cortex-A715: erratum 2701951
Neoverse V2: erratum 2719103
Cortex-A710: erratum 2701952
Cortex-X2: erratum 2701952
Neoverse N2: erratum 2728475
Neoverse V1: erratum 2701953
Cortex-A78: erratum 2712571
Cortex-A78AE: erratum 2712574
Cortex-A78C: erratum 2712575

Change-Id: Ie86b7212d731a79e2a0c07649e69234e733cd78d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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refactor(errata-abi): optimize errata ABI using errata framework

Errata ABI feature introduced per CPU based errata structures
in the errata_abi_main.c, these can be removed by re-using
the structur

refactor(errata-abi): optimize errata ABI using errata framework

Errata ABI feature introduced per CPU based errata structures
in the errata_abi_main.c, these can be removed by re-using
the structures created by the errata framework.

Change-Id: I1a60d3e4f116b6254fb45426f43ff1b21771af89
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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feat(imx8m): add defines for csu_sa access security

This enables the usage of speaking defines instead of magic numbers:

CSU_SA(CSU_SA_SDMA1, 1, LOCKED)

becomes:

CSU_SA(CSU_SA_SDMA1, NON_SEC_

feat(imx8m): add defines for csu_sa access security

This enables the usage of speaking defines instead of magic numbers:

CSU_SA(CSU_SA_SDMA1, 1, LOCKED)

becomes:

CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED)

Change-Id: Idcabcda677bf7840084a2ea66d321b50aa0b2b20
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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feat(imx8m): add imx csu_sa enum type defines for imx8m

This ports the missing enum defines for the central security unit found
in NXPs i.MX8M socs. The defines itself where imported from NXP's
down

feat(imx8m): add imx csu_sa enum type defines for imx8m

This ports the missing enum defines for the central security unit found
in NXPs i.MX8M socs. The defines itself where imported from NXP's
downstream version of the trusted-firmware-a version 2.8[1].

[1]: https://github.com/nxp-imx/imx-atf/commit/0c52279fc4

Change-Id: Iad0c5d3733e9d29ead86334ba4bc5ce915018142
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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fix(imx8m): fix CSU_SA_REG to work with all sa registers

The csu found in the imx8mp has 3 csu_sa registers, before the fix not
all of them could be addressed.

The defines itself was imported from

fix(imx8m): fix CSU_SA_REG to work with all sa registers

The csu found in the imx8mp has 3 csu_sa registers, before the fix not
all of them could be addressed.

The defines itself was imported from NXP's downstream version of the
trusted-firmware-a version 2.8[1].

[1]: https://github.com/nxp-imx/imx-atf/commit/0c52279fc4

Change-Id: Ia3653118bba82df9244c819a5c5f37bdc4e89c49
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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Merge changes from topic "css_refactor_arm" into integration

* changes:
refactor(allwinner): console runtime switch on bl31 exit
refactor(arm): console runtime switch on bl31 exit
refactor(con

Merge changes from topic "css_refactor_arm" into integration

* changes:
refactor(allwinner): console runtime switch on bl31 exit
refactor(arm): console runtime switch on bl31 exit
refactor(console): flush before console_switch_state

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Merge changes from topic "fix-lto-build-all" into integration

* changes:
build(fpga): correctly handle gcc as linker for LTO
fix(build): enforce single partition for LTO build
fix(rockchip): a

Merge changes from topic "fix-lto-build-all" into integration

* changes:
build(fpga): correctly handle gcc as linker for LTO
fix(build): enforce single partition for LTO build
fix(rockchip): add support for building with LTO enabled

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refactor(allwinner): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF

refactor(allwinner): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch only affects the Allwinner platform.

Change-Id: I15b4a459a280822a01c60e3b0c856b530db6efab
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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refactor(arm): console runtime switch on bl31 exit

Any BL31 setup and Runtime initialization within BL31 is still part of
the BOOT process. As such, the console flush and switch must be the
last cal

refactor(arm): console runtime switch on bl31 exit

Any BL31 setup and Runtime initialization within BL31 is still part of
the BOOT process. As such, the console flush and switch must be the
last calls before BL31 exit. Flush the console print buffer before
switching to runtime. This is so that there is no lingering chars in
the print buffer when we move to the runtime console.

This patch adds console flush before switching to runtime in
bl31_plat_runtime_setup() function (before BL31 exits). The plan is to
move flush and switch calls to bl31_main before BL31 exits, until then
console_flush() in bl31_main.c has been left as is.

This patch affects the Arm platform only.

Change-Id: I4d367b9e9640686ac15246ad24318ae4685c12c5
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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refactor(console): flush before console_switch_state

TF-A plans to move console_flush() and
console_switch_state(CONSOLE_FLAG_RUNTIME) to the end of bl31_main()
before BL31 exits.

Add console_flush

refactor(console): flush before console_switch_state

TF-A plans to move console_flush() and
console_switch_state(CONSOLE_FLAG_RUNTIME) to the end of bl31_main()
before BL31 exits.

Add console_flush() in the generic implementation of
bl31_plat_runtime_setup() call so that platforms can implement or
follow the generic pattern to test this implementation before
console_flush() and console_switch_state() move to bl31_main().

This patch affects the generic implementation of
bl31_plat_runtime_setup()

Change-Id: I92b4176022bfb84558dec5a83386e8ecef49516a
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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Merge "fix(spm): reduce verbosity on passing tf-a-tests" into integration

Merge changes from topic "topics/fwu_metadata_v2_migration" into integration

* changes:
style(fwu): change the metadata fields to align with specification
style(partition): use GUID values for G

Merge changes from topic "topics/fwu_metadata_v2_migration" into integration

* changes:
style(fwu): change the metadata fields to align with specification
style(partition): use GUID values for GPT partition fields
feat(st): add logic to boot the platform from an alternate bank
feat(st): add a function to clear the FWU trial state counter
feat(fwu): add a function to obtain an alternate FWU bank to boot
feat(fwu): add some sanity checks for the FWU metadata
feat(fwu): modify the check for getting the FWU bank's state
feat(st): get the state of the active bank directly
feat(fwu): add a config flag for including image info in the FWU metadata
feat(fwu): migrate FWU metadata structure to version 2
feat(fwu): document the config flag for including image info in the FWU metadata
feat(fwu): update the URL links for the FWU specification

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Merge changes from topic "sgi_to_nrd" into integration

* changes:
refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd
refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"
refa

Merge changes from topic "sgi_to_nrd" into integration

* changes:
refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd
refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"
refactor(sgi): move apis and types to "nrd" prefix
refactor(sgi): replace build-option prefix to "NRD"
refactor(sgi): move neoverse_rd out of css
refactor(sgi): move from "sgi" to "neoverse_rd"
feat(sgi): remove unused SGI_PLAT build-option
fix(sgi): align to misra rule for braces
feat(rde1edge): remove support for RD-E1-Edge
fix(rdn2): populate TOS_CONFIG only when SPMC_AT_EL3 is enabled
fix(board): update spi_id max for sgi multichip platforms

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Merge changes from topic "smmuv3_fix" into integration

* changes:
feat(smmu): separate out smmuv3_security_init from smmuv3_init
feat(smmu): fix to perform INV_ALL before enabling GPC

Merge "refactor(qemu): console runtime switch on bl31 exit" into integration