Merge changes from topic "mte_fixes" into integration

* changes:
build(changelog): move mte to mte2
refactor(mte): remove mte, mte_perm

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently cont

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.

BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2

Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "feature/imx8m-csu" into integration

* changes:
style(imx8m): add parenthesis to CSU_HP_REG
feat(imx8mp): restrict peripheral access to secure world
feat(imx8mp): set

Merge changes from topic "feature/imx8m-csu" into integration

* changes:
style(imx8m): add parenthesis to CSU_HP_REG
feat(imx8mp): restrict peripheral access to secure world
feat(imx8mp): set and lock almost all peripherals as non-secure
feat(imx8mm): restrict peripheral access to secure world
feat(imx8mm): set and lock almost all peripherals as non-secure
feat(imx8m): add defines for csu_sa access security
feat(imx8m): add imx csu_sa enum type defines for imx8m
fix(imx8m): fix CSU_SA_REG to work with all sa registers

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fix(nuvoton): prevent changing clock frequency

prevent changing clock frequency already set in BootBlock based on PLL value

Change-Id: I8b4b53448cc8e703fd88ad6166f85a4fe3ba9e46
Signed-off-by: Marga

fix(nuvoton): prevent changing clock frequency

prevent changing clock frequency already set in BootBlock based on PLL value

Change-Id: I8b4b53448cc8e703fd88ad6166f85a4fe3ba9e46
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>

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feat(imx8ulp): give HIFI4 DSP access to more resources

This patch gives i.MX8ULP's HIFI4 DSP R/W access to the
following additional resources (peripherals):
1) LPUART7
2) IOMUXC1
3) PCC4
4) CGC1

feat(imx8ulp): give HIFI4 DSP access to more resources

This patch gives i.MX8ULP's HIFI4 DSP R/W access to the
following additional resources (peripherals):
1) LPUART7
2) IOMUXC1
3) PCC4
4) CGC1

Doing this allows the firmware running on the DSP to
set up serial communication, which also requires doing
pinctrl and clock management-related operations.

Access to the aforementioned resources is given by
configuring the XRDC module.

Change-Id: Ie3ca9f22bb625b2463870158875f503c3c1d6452
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>

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Merge "fix(cpus): workaround for Cortex-A720 erratum 2926083" into integration

Merge changes Id72a0370,I2bafba38,I2bd48441,I164c579c,Iddf8aea0, ... into integration

* changes:
feat(rpi): add Raspberry Pi 5 support
fix(rpi): consider MT when calculating core index from MPID

Merge changes Id72a0370,I2bafba38,I2bd48441,I164c579c,Iddf8aea0, ... into integration

* changes:
feat(rpi): add Raspberry Pi 5 support
fix(rpi): consider MT when calculating core index from MPIDR
refactor(rpi): move register definitions out of rpi_hw.h
refactor(rpi): add platform macro for the crash UART base address
refactor(rpi): split out console registration logic
refactor(rpi): move more platform-specific code into common

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fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE

fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE (Statistical Profiling Extension) is implemented
and enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is "implemented and enabled".

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I30182c3893416af65b55fca9a913cb4512430434
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(nuvoton): gfx frame buffer memory corruption during secondary boot" into integration

Merge changes from topic "st_mckprot_bl32" into integration

* changes:
refactor(stm32mp1): move the MCU security to BL32
feat(st-clock): add function to control MCU subsystem

refactor: fix common misspelling of init*

Change-Id: I3fc95e8e53ef487fd5a559cda739aaea33d765a9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

refactor(stm32mp1): move the MCU security to BL32

Change the MCKPROT control management. Now, the MCU subsystem
is done in the BL32 using the dedicated clock function.
If using OP-TEE, you will need

refactor(stm32mp1): move the MCU security to BL32

Change the MCKPROT control management. Now, the MCU subsystem
is done in the BL32 using the dedicated clock function.
If using OP-TEE, you will need the corresponding commit [1].
This should be integrated in OP-TEE tag 4.2.0.

[1] e07f9212d5 plat-stm32mp1: shared_resource: disable MCKPROT if
not needed

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I59f90ace750aa93f674389f881e2fe14ad334a72

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fix(nuvoton): gfx frame buffer memory corruption during secondary boot

gfx frame buffer memory corruption because of moving TF-A to DDR

Change-Id: I6f1e0c8d048273b8047497adec631160aaf393d6
Signed-o

fix(nuvoton): gfx frame buffer memory corruption during secondary boot

gfx frame buffer memory corruption because of moving TF-A to DDR

Change-Id: I6f1e0c8d048273b8047497adec631160aaf393d6
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>

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Merge "refactor(mbedtls): remove mbedtls 2.x support" into integration

refactor(mbedtls): remove mbedtls 2.x support

Deprecation notice was sent to the community and no objection was
raised, so removing mbedtls 2.x support.

Change-Id: Id3eb98b55692df98aabe6a7c5a5ec910

refactor(mbedtls): remove mbedtls 2.x support

Deprecation notice was sent to the community and no objection was
raised, so removing mbedtls 2.x support.

Change-Id: Id3eb98b55692df98aabe6a7c5a5ec910222c8abd
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(rpi5): add PCI SMCCC support

BCM2712 changes:
- support all 3 PCIe RCs / segments.
- don't check for link up: the RC can now be configured to fabricate
all-ones AXI OKAY responses, so no mo

feat(rpi5): add PCI SMCCC support

BCM2712 changes:
- support all 3 PCIe RCs / segments.
- don't check for link up: the RC can now be configured to fabricate
all-ones AXI OKAY responses, so no more Arm SErrors when the link is
down (or other conditions).

Also, limit bus 0 to devfn 0 as accesses beyond that may result in
lock-ups.

Change-Id: Ic64785cd68b22571c6638fc3f771703113bc76f6
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

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style(imx8m): add parenthesis to CSU_HP_REG

To be inline with CSU_SA_REG and CSU_HPCONTROL_REG.

Change-Id: Ia7332096312df41a8cf994d58fad76a99493dd02
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengu

style(imx8m): add parenthesis to CSU_HP_REG

To be inline with CSU_SA_REG and CSU_HPCONTROL_REG.

Change-Id: Ia7332096312df41a8cf994d58fad76a99493dd02
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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feat(imx8mp): restrict peripheral access to secure world

This restricts and locks all security relevant peripherals to only be
changeable by the secure world. Otherwise the normal world can simply
c

feat(imx8mp): restrict peripheral access to secure world

This restricts and locks all security relevant peripherals to only be
changeable by the secure world. Otherwise the normal world can simply
change the access settings and defeat all security measures put in
place.

Change-Id: I248ef8dd67f1de7e528c3da456311bb138b77540
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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feat(imx8mp): set and lock almost all peripherals as non-secure

This sets and locks all peripheral type-1 masters, except CAAM, access
as non-secure, so that they can't access secure world resources

feat(imx8mp): set and lock almost all peripherals as non-secure

This sets and locks all peripheral type-1 masters, except CAAM, access
as non-secure, so that they can't access secure world resources from the
normal world.

The CAAM itself is TrustZone aware and handles memory access between the
normal world and the secure world on its own. Pinning it as non-secure
access results in bus aborts if the secure memory region is protected by
the TZASC380.

Change-Id: Iedf3d67481dc35d56aa7b291749b999a56d6e85e
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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feat(imx8mm): restrict peripheral access to secure world

This restricts and locks all security relevant peripherals to only be
changeable by the secure world. Otherwise the normal world can simply
c

feat(imx8mm): restrict peripheral access to secure world

This restricts and locks all security relevant peripherals to only be
changeable by the secure world. Otherwise the normal world can simply
change the access settings and defeat all security measures put in
place.

Change-Id: I484a2c8164e58b68256d829470e00d5ec473e266
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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feat(imx8mm): set and lock almost all peripherals as non-secure

This sets and locks all peripheral type-1 masters, except CAAM, access
as non-secure, so that they can't access secure world resources

feat(imx8mm): set and lock almost all peripherals as non-secure

This sets and locks all peripheral type-1 masters, except CAAM, access
as non-secure, so that they can't access secure world resources from the
normal world.

The CAAM itself is TrustZone aware and handles memory access between the
normal world and the secure world on its own. Pinning it as non-secure
access results in bus aborts if the secure memory region is protected by
the TZASC380.

Change-Id: Idba4d8a491ccce0491489c61e73545baab1889c4
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(S

fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(Statistical Profiling Extension) is enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is enabled, ENABLE_SPE_FOR_NS=1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: Iaeb258c8b0a92e93d70b7dad6ba59d1056aeb135
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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feat(rpi): add Raspberry Pi 5 support

The Raspberry Pi 5 is a single-board computer based on BCM2712 that
contains four Arm Cortex-A76 cores.

This change introduces minimal BL31 support with PSCI t

feat(rpi): add Raspberry Pi 5 support

The Raspberry Pi 5 is a single-board computer based on BCM2712 that
contains four Arm Cortex-A76 cores.

This change introduces minimal BL31 support with PSCI that has been
validated to boot Linux and a private EDK2 build.

It's a drop-in replacement for the custom TF-A armstub now included in
the EEPROM images.

Change-Id: Id72a0370f54e71ac97c3daa1bacedacb7dec148f
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

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fix(rpi): consider MT when calculating core index from MPIDR

RPi 5 has newer Armv8.2 cores where the MT bit is set to indicate that
the lowest affinity level represents a thread, but there is only o

fix(rpi): consider MT when calculating core index from MPIDR

RPi 5 has newer Armv8.2 cores where the MT bit is set to indicate that
the lowest affinity level represents a thread, but there is only one
thread per core.

To deal with this, simply right shift MPIDR by one affinity level to get
the cluster and core IDs back into Aff1 and Aff0 as expected.

Change-Id: I2bafba38f82fd9a6ef6f2fdf2c089b754279a6de
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

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refactor(rpi): move register definitions out of rpi_hw.h

Change-Id: I2bd48441359468efb9e94fd2fffb079683f7a7fd
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>