feat(qemu-sbsa): add support for RME on SBSA machine

Add the necessary foundation to support Arm's RME extension on the SBSA
reference architecture.

Change-Id: If5a63ed0015cb33fcae367ff2cded811bbdc

feat(qemu-sbsa): add support for RME on SBSA machine

Add the necessary foundation to support Arm's RME extension on the SBSA
reference architecture.

Change-Id: If5a63ed0015cb33fcae367ff2cded811bbdc1e54
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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feat(qemu-sbsa): configure RMM manifest based on system RAM

The RMM manifest needs to reflect the amount of RAM available on the
system. Since system RAM is based on user input and reflected in the

feat(qemu-sbsa): configure RMM manifest based on system RAM

The RMM manifest needs to reflect the amount of RAM available on the
system. Since system RAM is based on user input and reflected in the
device tree, get the information from there rather than using hard coded
values.

Change-Id: I63f090c1c04d9addfcd7a349450735728fa88ed0
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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feat(qemu-sbsa): configure GPT based on system RAM

The amount of memory supported by the SBSA platform is dynamic
and dependent on user input. Since the configuration of the GPT
needs to reflect th

feat(qemu-sbsa): configure GPT based on system RAM

The amount of memory supported by the SBSA platform is dynamic
and dependent on user input. Since the configuration of the GPT
needs to reflect the system memory, QEMU_PAS_NS0 needs to be set
based on the information found in the device tree.

Change-Id: I5d1411ac00020b7b38a652ba2904c8a70fa64d18
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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feat(qemu-sbsa): adjust DT memory start address when supporting RME

When RME is enabled on SBSA, the RMM is located at the start of the NS
RAM and the device tree after it. This patch adjust the DT

feat(qemu-sbsa): adjust DT memory start address when supporting RME

When RME is enabled on SBSA, the RMM is located at the start of the NS
RAM and the device tree after it. This patch adjust the DT memory start
address so that anyone reading it has an accurate view of the system
configuration.

Change-Id: I32ca63a78d68831faf2c65ad60a45c841b7cbada
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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feat(qemu-sbsa): relocate DT after the RMM when RME is enabled

When RME is enabled, (1) the RMM is installed at the base of system RAM,
(2) the base of the system RAM is shifted upward, after the RM

feat(qemu-sbsa): relocate DT after the RMM when RME is enabled

When RME is enabled, (1) the RMM is installed at the base of system RAM,
(2) the base of the system RAM is shifted upward, after the RMM and (3)
the device tree is relocated to the new system RAM base.

This patch relocates the device tree to the new system RAM base before
the RMM is installed in RAM. From there, other accesses to the device
tree are using the new location.

Change-Id: I0cb4e060ca33a11becd78fe48fab4dc76f0b484b
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE

When RME is enabled the RMM is placed at the bottom of the NS RAM,
meaning that NS_DRAM0_BASE has to be located after that.

This

feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE

When RME is enabled the RMM is placed at the bottom of the NS RAM,
meaning that NS_DRAM0_BASE has to be located after that.

This patch disscociates the base of the NS RAM as defined by QEMU by
introducing a new define, PLAT_QEMU_DRAM0_BASE. An offset can be added
to that new define when the software's view of the base memory need to
differ from QEMU.

No change in functionality.

Change-Id: I887f9993d5a61896352cfff17e0d92e2c2b9030a
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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feat(qemu-sbsa): increase maximum FIP size

Following what was done for:

f465ac221001 ("fix(qemu): increase max FIP size")

increase the size of the FIP image to take up the remaining
space in FLASH

feat(qemu-sbsa): increase maximum FIP size

Following what was done for:

f465ac221001 ("fix(qemu): increase max FIP size")

increase the size of the FIP image to take up the remaining
space in FLASH0. That way the RMM image can also be added
to the FIP.

Change-Id: I89bba36f751468e99241f1c20b51c48fe06d8229
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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refactor(qemu-sbsa): move all DT related functions to sbsa_platform.c

Move all DT related functions to file sbsa_platform_dt.c so that clients
other than SIP SVC can use the funtionality. At the sa

refactor(qemu-sbsa): move all DT related functions to sbsa_platform.c

Move all DT related functions to file sbsa_platform_dt.c so that clients
other than SIP SVC can use the funtionality. At the same time, make all
functions that don't need outside visibility static.

No change in functionality.

Change-Id: I9bce730c8f9e2b827937466f4432ecfa74c35675
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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refactor(qemu-sbsa): create accessor functions for platform info

Creating accessor functions to access information held by struct
qemu_platform_info. That way the code that is relevant to fetching
i

refactor(qemu-sbsa): create accessor functions for platform info

Creating accessor functions to access information held by struct
qemu_platform_info. That way the code that is relevant to fetching
information from the device tree can be taken out of sbsa_sip_svc.c and
placed in a file where other client can use the information it provides.

No change in functionality.

Change-Id: I989952ee6d15e1436549002dd7c7767c745ea297
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful

There is no relation between the name of function sip_svc_init() and
what it does. As such rename it to something mo

refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful

There is no relation between the name of function sip_svc_init() and
what it does. As such rename it to something more appropriate and move
it to a header that make sense.

No change in functionality.

Change-Id: I7bd78b1fe70e2930c395ef0a097bfad3b1e55d3a
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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refactor(qemu-sbsa): move DT related structures to their own header

Move structure declaration related to the DT to their own header. That
way they can be reused by other files. At the same time,

refactor(qemu-sbsa): move DT related structures to their own header

Move structure declaration related to the DT to their own header. That
way they can be reused by other files. At the same time, typedefs are
removed and structure names prepended with "platform_" to avoid clashing
with other structure declarations available in the system.

No change in functionality.

Change-Id: If67a141cc7441b0636af774d7edfe51cf8034a11
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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refactor(qemu-sbsa): rename struct dynamic_platform_info

Rename struct dynamic_platform_info to qemu_platform_info and properly
declare a variable name "dynamic_platform_info". That way structures

refactor(qemu-sbsa): rename struct dynamic_platform_info

Rename struct dynamic_platform_info to qemu_platform_info and properly
declare a variable name "dynamic_platform_info". That way structures
related to the device tree can be moved out of sbsa_sip_svc.c.

No change in functionality.

Change-Id: I1af39047af96ae02f3b8eecda6cb67508f14d37a
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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refactor(qemu): make L0GPT size configurable

Add a new parameter to make the size of the L0GPT configurable based on
the amount of memory available on a platform. That way platform with a
wider phys

refactor(qemu): make L0GPT size configurable

Add a new parameter to make the size of the L0GPT configurable based on
the amount of memory available on a platform. That way platform with a
wider physical address range can be supported.

No change in functionality.

Change-Id: I5b7b4968636d61929ad6ebdc05c389291cf510b1
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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refactor(qemu): move GPT setup to BL31

Some platforms such as QEMU-SBSA access the device tree located at the
bottom of the non-secure RAM from BL31. When GPT checks are enabled at
BL2, that access

refactor(qemu): move GPT setup to BL31

Some platforms such as QEMU-SBSA access the device tree located at the
bottom of the non-secure RAM from BL31. When GPT checks are enabled at
BL2, that access generates a GPT check fault because the device tree
area is configure as non-secure RAM and the access is made from secure
EL3.

We could change the device tree memory area configuration in a way that
it is accessible from BL31, but that would require another configuration
of the GPT before going to BL33.

Since BL2 and BL31 are both running at EL3, a better solution is simply
move the GPT configuration and enabling to BL31, after the device tree
has been probed.

No change in functionality.

Change-Id: Ifa01c50164268b993d563c32e4e42140259c44e2
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
[Added changelog description]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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fix(qemu-sbsa): fix compilation error when accessing DT functions

When building SBSA, using DT functions from fdt_wrappers.c produces a
linker error. Adding:

BL2_SOURCES += ${FDT_WRAPPERS_SOURCES}

fix(qemu-sbsa): fix compilation error when accessing DT functions

When building SBSA, using DT functions from fdt_wrappers.c produces a
linker error. Adding:

BL2_SOURCES += ${FDT_WRAPPERS_SOURCES}

fixes the problem. Since the same inclusion would be present in both
qemu/platform.mk and qemu_sbsa/platform.mk, do the changes in
qemu/common/common.mk.

Change-Id: I775b06c1741f6618813c5e1d2c64cdc1888d8519
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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feat(fvp): build hob library

To produce PHIT HOB list in FVP, add build path for hob library.

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: I8f4905433bd1cc6f4c9247197b9bd69041f50fd7

feat(stm32mp2): add FWU support

Add stm32_get_bkpr_fwu_info_addr() function.
Call stm32_fwu_set_boot_idx() in bl2_plat_handle_post_image_load().

Signed-off-by: Yann Gautier <yann.gautier@foss.st.co

feat(stm32mp2): add FWU support

Add stm32_get_bkpr_fwu_info_addr() function.
Call stm32_fwu_set_boot_idx() in bl2_plat_handle_post_image_load().

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ieb57dffa4ce784d1ed61b401dc17376fe745c111

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fix(romlib): romlib build without MbedTLS

The ROMLIB build currently has a strong dependency on MbedTLS. This
patch has been introduced to remove this dependency, making it more
flexible.

Change-Id

fix(romlib): romlib build without MbedTLS

The ROMLIB build currently has a strong dependency on MbedTLS. This
patch has been introduced to remove this dependency, making it more
flexible.

Change-Id: If8c4cc7cf557687f40b235a4b8f931cfb70943fd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(tc): replace vencoder with simple panel for kernel > 6.6" into integration

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02e3f
("drm/arm/komeda: Remove component framework and add a simple encoder")

To address this we introduce a new compilation flag
`TC_DPU_USE_SIMPLE_PANEL` for control panel vs. encoder enablement.
This flag is set when the kernel version is >= 6.6 and 0 when the kernel
version is < 6.6.

We also rename the `vencoder_in` node to `lcd_in` to avoid unnecessary
conditional code for vencoder vs. simple panel enablement.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibb14a56911cfb406b2181a22cc40db58d8ceaa8d

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feat(cpus): add support for Alto CPU

Add basic CPU library code to support the Alto CPU.

Change-Id: I45958be99c4a350a32a9e511d3705fb568b97236
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>

Merge changes I00d2de7b,I5ec82646 into integration

* changes:
feat(tc): fpga: Enable support for loading FIP image to DRAM
feat(tc): allow Android load and Boot From RAM

feat(tc): fpga: Enable support for loading FIP image to DRAM

This patch enable support for loading FIP image into DRAM rather than
flash drive.

Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554

feat(tc): fpga: Enable support for loading FIP image to DRAM

This patch enable support for loading FIP image into DRAM rather than
flash drive.

Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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feat(tc): allow Android load and Boot From RAM

This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loadi

feat(tc): allow Android load and Boot From RAM

This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loading Android image

Change-Id: I5ec82646cb2993e7b5976e702ebcc8efa51d1128
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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Merge changes I04ecd50f,I830b53e2 into integration

* changes:
fix(rcar3-drivers): disable A/B loader support by default
fix(rcar-layout): fix tool build