1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/arm/gicv2.h> 14 #include <lib/mmio.h> 15 #include <lib/psci/psci.h> 16 #include <plat/arm/common/plat_arm.h> 17 #include <plat/common/platform.h> 18 19 #include <plat_private.h> 20 #include "pm_client.h" 21 #include "zynqmp_pm_api_sys.h" 22 23 static uintptr_t zynqmp_sec_entry; 24 25 static void zynqmp_cpu_standby(plat_local_state_t cpu_state) 26 { 27 VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state); 28 29 dsb(); 30 wfi(); 31 } 32 33 static int32_t zynqmp_pwr_domain_on(u_register_t mpidr) 34 { 35 int32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 36 const struct pm_proc *proc; 37 uint32_t buff[3]; 38 enum pm_ret_status ret; 39 40 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); 41 42 if (cpu_id == -1) { 43 return PSCI_E_INTERN_FAIL; 44 } 45 46 proc = pm_get_proc(cpu_id); 47 if (proc == NULL) { 48 return PSCI_E_INTERN_FAIL; 49 } 50 51 /* Check the APU proc status before wakeup */ 52 ret = pm_get_node_status(proc->node_id, buff); 53 if ((ret != PM_RET_SUCCESS) || (buff[0] == PM_PROC_STATE_SUSPENDING)) { 54 return PSCI_E_INTERN_FAIL; 55 } 56 57 /* Clear power down request */ 58 pm_client_wakeup(proc); 59 60 /* Send request to PMU to wake up selected APU CPU core */ 61 (void)pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING); 62 63 return PSCI_E_SUCCESS; 64 } 65 66 static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state) 67 { 68 uint32_t cpu_id = plat_my_core_pos(); 69 const struct pm_proc *proc = pm_get_proc(cpu_id); 70 71 if (proc == NULL) { 72 return; 73 } 74 75 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 76 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 77 __func__, i, target_state->pwr_domain_state[i]); 78 } 79 80 /* Prevent interrupts from spuriously waking up this cpu */ 81 gicv2_cpuif_disable(); 82 83 /* 84 * Send request to PMU to power down the appropriate APU CPU 85 * core. 86 * According to PSCI specification, CPU_off function does not 87 * have resume address and CPU core can only be woken up 88 * invoking CPU_on function, during which resume address will 89 * be set. 90 */ 91 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0); 92 } 93 94 static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) 95 { 96 uint32_t state; 97 uint32_t cpu_id = plat_my_core_pos(); 98 const struct pm_proc *proc = pm_get_proc(cpu_id); 99 100 if (proc == NULL) { 101 return; 102 } 103 104 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 105 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 106 __func__, i, target_state->pwr_domain_state[i]); 107 } 108 109 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? 110 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; 111 112 /* Send request to PMU to suspend this core */ 113 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry); 114 115 /* APU is to be turned off */ 116 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 117 /* disable coherency */ 118 plat_arm_interconnect_exit_coherency(); 119 } 120 } 121 122 static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) 123 { 124 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 125 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 126 __func__, i, target_state->pwr_domain_state[i]); 127 } 128 plat_arm_gic_pcpu_init(); 129 gicv2_cpuif_enable(); 130 } 131 132 static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 133 { 134 uint32_t cpu_id = plat_my_core_pos(); 135 const struct pm_proc *proc = pm_get_proc(cpu_id); 136 137 if (proc == NULL) { 138 return; 139 } 140 141 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 142 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 143 __func__, i, target_state->pwr_domain_state[i]); 144 } 145 146 /* Clear the APU power control register for this cpu */ 147 pm_client_wakeup(proc); 148 149 /* enable coherency */ 150 plat_arm_interconnect_enter_coherency(); 151 /* APU was turned off */ 152 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 153 plat_arm_gic_init(); 154 } else { 155 gicv2_cpuif_enable(); 156 gicv2_pcpu_distif_init(); 157 } 158 } 159 160 /******************************************************************************* 161 * ZynqMP handlers to shutdown/reboot the system 162 ******************************************************************************/ 163 164 static void __dead2 zynqmp_system_off(void) 165 { 166 /* disable coherency */ 167 plat_arm_interconnect_exit_coherency(); 168 169 /* Send the power down request to the PMU */ 170 (void)pm_system_shutdown((uint32_t)PMF_SHUTDOWN_TYPE_SHUTDOWN, 171 pm_get_shutdown_scope()); 172 173 while (true) { 174 wfi(); 175 } 176 } 177 178 static void __dead2 zynqmp_system_reset(void) 179 { 180 /* disable coherency */ 181 plat_arm_interconnect_exit_coherency(); 182 183 /* Send the system reset request to the PMU */ 184 (void)pm_system_shutdown((uint32_t)PMF_SHUTDOWN_TYPE_RESET, 185 pm_get_shutdown_scope()); 186 187 while (true) { 188 wfi(); 189 } 190 } 191 192 static int32_t zynqmp_validate_power_state(uint32_t power_state, 193 psci_power_state_t *req_state) 194 { 195 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 196 197 uint32_t pstate = psci_get_pstate_type(power_state); 198 199 assert(req_state); 200 201 /* Sanity check the requested state */ 202 if (pstate == PSTATE_TYPE_STANDBY) { 203 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 204 } else { 205 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 206 } 207 /* We expect the 'state id' to be zero */ 208 if (psci_get_pstate_id(power_state) != 0U) { 209 return PSCI_E_INVALID_PARAMS; 210 } 211 212 return PSCI_E_SUCCESS; 213 } 214 215 static void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) 216 { 217 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; 218 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; 219 } 220 221 /******************************************************************************* 222 * Export the platform handlers to enable psci to invoke them 223 ******************************************************************************/ 224 static const struct plat_psci_ops zynqmp_psci_ops = { 225 .cpu_standby = zynqmp_cpu_standby, 226 .pwr_domain_on = zynqmp_pwr_domain_on, 227 .pwr_domain_off = zynqmp_pwr_domain_off, 228 .pwr_domain_suspend = zynqmp_pwr_domain_suspend, 229 .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish, 230 .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish, 231 .system_off = zynqmp_system_off, 232 .system_reset = zynqmp_system_reset, 233 .validate_power_state = zynqmp_validate_power_state, 234 .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, 235 }; 236 237 /******************************************************************************* 238 * Export the platform specific power ops. 239 ******************************************************************************/ 240 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 241 const struct plat_psci_ops **psci_ops) 242 { 243 zynqmp_sec_entry = sec_entrypoint; 244 245 *psci_ops = &zynqmp_psci_ops; 246 247 return 0; 248 } 249