| 20fdf0b0 | 05-Oct-2018 |
Rajan Vaja <rajan.vaja@xilinx.com> |
zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list
CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid
clock list would not be registered to CCF framework and so
cannot be used as par
zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list
CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid
clock list would not be registered to CCF framework and so
cannot be used as parent of other clocks.
WDT clock has default parent as CLK_TOPSW_LSBUS(APB clock).
If CLK_TOPSW_LSBUS is not registered, CCF would not recognize
that clock and hence rate of WDT clock would be calculated to
be 0 by CCF(as parent rate is considered 0).
So it is necessary to allow registration of CLK_TOPSW_LSBUS
clock.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Iceaba0f137784fc5fd666e66ffc4c143381c6ccc
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| b3ce966a | 09-Jan-2019 |
Mounika Grace Akula <mounika.grace.akula@xilinx.com> |
zynqmp: pm: Add LPD WDT clock to the pm_clock structure
This patch adds LPD WDT clock node to the pm_clock clocks structure list
so that LPD WDT can be used from Linux.
Also this patch removes the
zynqmp: pm: Add LPD WDT clock to the pm_clock structure
This patch adds LPD WDT clock node to the pm_clock clocks structure list
so that LPD WDT can be used from Linux.
Also this patch removes the CLK_LPD_LSBUS from invalid clock list to
allow the registration of this clock to CCF framework as it is the
parent of LPD WDT.
Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Iea065aa8150eaba4bb4b42bc6be1fd4b7fe7b403
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| 06ad9803 | 17-Sep-2018 |
Mirela Simonovic <mirela.simonovic@aggios.com> |
zynqmp: pm: Fix clock models and IDs of GEM-related clocks
GEM-related clock models were incorrect and are fixed as follows
(documented below for GEM0, but the same holds for any GEM ID):
- CLK_GEM
zynqmp: pm: Fix clock models and IDs of GEM-related clocks
GEM-related clock models were incorrect and are fixed as follows
(documented below for GEM0, but the same holds for any GEM ID):
- CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and
the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this
clock is newly introduced in this patch.
- CLK_GEM0_REF models the clock mux that selects the reference clock
for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This
mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL.
Note that the routing of external clock to the mux is not modelled
and is assumed to be configured by the FSBL if required, and not
changeable at runtime. The ID of this clock is introduced in this patch.
- CLK_GEM0_TX models clock with only a gate that is controlled via
bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is
CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID
value of CLK_GEM0_REF. This is done in order to fix the clock models
and incorrect binding without requiring to change device-tree (binding
of clock IDs to GEM interface).
- CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT
bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced
from external RGMII PHY (via MIO or EMIO). We do not model the whole
clock path to the Rx gate, since this is configured by the FSBL and
never changed at runtime (and there is no mechanism to change the
path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the
previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX
were swapped in device tree, so by fixing the IDs this way there is no
need for device tree fix.
Rates of the external RX/TX clocks can be specified in device tree if
needed. Right now, that's not necessary because Tx clock is sourced
from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas
the Rx clock is sourced from external reference and the driver never
attempts to get/get clock rate (only to enable it). If this changes in
future, ATF clock model doesn't need to be changed. Instead, the clock
rates for gem0_tx_ext and gem0_rx_ext have to be specified in device
tree.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <will.wong@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I6497d4309e92205c527bd81b3aa932f4474f5b79
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| fa8ae3c8 | 09-Jan-2019 |
Mounika Grace Akula <mounika.grace.akula@xilinx.com> |
zynqmp: pm: Rename FPD WDT clock ID
This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT.
Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Jolly Shah <j
zynqmp: pm: Rename FPD WDT clock ID
This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT.
Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I4d00a59b1dc54920115a2da55e8a06347fe2231c
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| 65501a7c | 17-Apr-2019 |
Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
plat: xilinx: zynqmp: Correct syscnt freq for QEMU
Correct the syscnt frequency for ZynqMP QEMU to 65Mhz.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jolly Shah <jol
plat: xilinx: zynqmp: Correct syscnt freq for QEMU
Correct the syscnt frequency for ZynqMP QEMU to 65Mhz.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ie0137feb9b7e24ed4e5d6cbf81c58ac77bb69214
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| c613a660 | 30-Jul-2019 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR
Add support for zu48dr and zu49dr to the list of zynqmp devices. The
zu48dr and zu49dr are the new RFSoC silicons with id values o
arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR
Add support for zu48dr and zu49dr to the list of zynqmp devices. The
zu48dr and zu49dr are the new RFSoC silicons with id values of 0x7b
and 0x7e.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I2978f16bb663853951ef8059bf0327f909447f34
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| 5bd029bc | 07-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
xilinx: pm_service: Rename macros to use generic macro names
ZynqMP pm_service ipi file uses platform specific macros names.
pm_service ipi functions can be used by other Xilinx platforms
also. Make
xilinx: pm_service: Rename macros to use generic macro names
ZynqMP pm_service ipi file uses platform specific macros names.
pm_service ipi functions can be used by other Xilinx platforms
also. Make rename macros to use generic names so that it can be
used by common file.
pm_service ipi functions will be moved to common file in next patch.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
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| 28e4d370 | 07-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
xilinx: zynqmp: Rename pm_api members to use generic name
Use generic name for pm_api structure member, so that pm_api
structure can be used other Xilinx platforms.
Structure definition will be mov
xilinx: zynqmp: Rename pm_api members to use generic name
Use generic name for pm_api structure member, so that pm_api
structure can be used other Xilinx platforms.
Structure definition will be moved to common file in upcoming
patch.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
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| b8e39f49 | 08-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
xilinx: Remove platform specific dependency from IPI function
ipi_mb function uses platform specific ipi configuration table.
These ipi_mb functions can be used for other Xilinx platform.
So, instea
xilinx: Remove platform specific dependency from IPI function
ipi_mb function uses platform specific ipi configuration table.
These ipi_mb functions can be used for other Xilinx platform.
So, instead of using direct data structure, initialize IPI
configuration data by passing platform specific ipi table.
Macros are updated accordingly for this ipi table change.
This change is done so that ipi_mb functions can be moved to
common file without major changes. All common functions now would
be moved to common file in next patch.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
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| 703a5aac | 08-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
xilinx: Move ipi configuration structure definition to header file
Move ipi configuration structure definition to common header file
and rename it to common name, so it can be used for Xilinx specif
xilinx: Move ipi configuration structure definition to header file
Move ipi configuration structure definition to common header file
and rename it to common name, so it can be used for Xilinx specific
other platforms in upcoming changes.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
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| 1611ef2b | 08-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
xilinx: zynqmp: Move zynqmp_ipi.h to include directory
Move zynqmp_ipi.h to platform specific include directory.
Rename it to plat_ipi.h instead of platform name. So, it can
be used to common source
xilinx: zynqmp: Move zynqmp_ipi.h to include directory
Move zynqmp_ipi.h to platform specific include directory.
Rename it to plat_ipi.h instead of platform name. So, it can
be used to common source files which needs platform specific
data.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
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