fix(versal-net): remove client-side code of PM_ABORT_SUSPEND

PM_ABORT_SUSPEND API is removed; client-side implementation is no
longer needed.

Change-Id: If2559ca106dbb60d761d0f8c7deeb86c1f30af16
Si

fix(versal-net): remove client-side code of PM_ABORT_SUSPEND

PM_ABORT_SUSPEND API is removed; client-side implementation is no
longer needed.

Change-Id: If2559ca106dbb60d761d0f8c7deeb86c1f30af16
Signed-off-by: Madhav Bhatt <madhav.bhatt@amd.com>

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feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE acr

feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE across all AMD-Xilinx platforms.

Change-Id: I95465e29ac8a9370da135c2113203c3206ecfec0
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(xilinx): incorrect usage of SECURE_FLAG for psci

As per the PSCI specification, the PSCI SMC call always expects from
the NON_SECURE world. However, in the platform specific file SECURE
flag was

fix(xilinx): incorrect usage of SECURE_FLAG for psci

As per the PSCI specification, the PSCI SMC call always expects from
the NON_SECURE world. However, in the platform specific file SECURE
flag was passed to the firmware which is incorrect. Pass NON_SECURE
flag from the platform specific file to the firmware in order to
align with the PSCI specification.

Change-Id: Iabe2cb45467cf63fe36626d323513ff05548eb3b
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(versal-net): fix coverity violation prevent buffer overrun

Coverity reported potential memory corruption issues in
bl31_early_platform_setup2() (CIDs 487973 and 487972):

- CID 487973 (ARRAY_VS_

fix(versal-net): fix coverity violation prevent buffer overrun

Coverity reported potential memory corruption issues in
bl31_early_platform_setup2() (CIDs 487973 and 487972):

- CID 487973 (ARRAY_VS_SINGLETON): "&boot_mode" was passed to
get_boot_mode(), which treats the argument as an array. This could
lead to misinterpretation of adjacent memory.
- CID 487972 (OVERRUN): Passing "&boot_mode" (a single 4-byte element)
allowed get_boot_mode() to access out-of-bounds indices, resulting in
a possible buffer overrun.

Changed boot_mode from a single variable to an array sized according
to the return payload, preventing singleton pointer violation.

Change-Id: I53944db10b694d1599da0e5b1fbd30a97e83803c
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(xilinx): fix missing security flag in suspend path

Suspend flow was always programming wakeup sources with a fixed
secure flag, regardless of whether the caller was secure or
non-secure. This ma

fix(xilinx): fix missing security flag in suspend path

Suspend flow was always programming wakeup sources with a fixed
secure flag, regardless of whether the caller was secure or
non-secure. This may cause incorrect behavior for non-secure
suspend requests.

Fix this by passing the caller's security state (flag) through
pm_client_suspend() and pm_client_set_wakeup_sources() to ensure
that wakeup sources are set with the correct context.

Fixes: <4697164a3fa8> ("plat: xilinx: versal: Mark IPI calls secure/non-secure")

Change-Id: I5fcf65788a54010b4759b0d08e4f54c6e5037e47
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(versal-net): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined
in C. When BL31 is compiled with Armclang, a call to
plat_core_pos_by_mpidr() f

fix(versal-net): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined
in C. When BL31 is compiled with Armclang, a call to
plat_core_pos_by_mpidr() from plat_my_core_pos() results in the
return address stored in register x30 becoming invalid and register
x9 (used later) ends up with the value 0x0. Consequently, the CPU
branches to address 0x0, triggering a synchronous exception. TF-A
then invokes the BHB flush code before resuming execution. However,
since the stack is not properly initialized at this stage, the system
eventually enters plat_panic_handler(). In the updated implementation,
the platform_get_core_pos() function is redefined in assembly to
provide tighter control during early boot stages. The MPIDR_EL1
register contains three affinity levels: Aff0 (bits [0:7]), Aff1
(bits [8:15]), and Aff2 (bits [16:23]). In this assembly function,
the core ID is extracted from Aff1 (MPIDR_AFF1_SHIFT), and the cluster
ID from Aff2 (MPIDR_AFF2_SHIFT). The macro PLATFORM_MPIDR_AFFINITY_MASK
introduced to mask MPIDR_EL1 register.

Change-Id: I090ea107c27dfa643431a97d15556c98f721b2e4
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge changes from topic "xlnx_runtime_console" into integration

* changes:
fix(versal2): runtime console in debug mode
fix(versal-net): runtime console in debug mode
fix(versal): runtime cons

Merge changes from topic "xlnx_runtime_console" into integration

* changes:
fix(versal2): runtime console in debug mode
fix(versal-net): runtime console in debug mode
fix(versal): runtime console in debug mode
fix(zynqmp): runtime console in debug mode

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fix(versal-net): runtime console in debug mode

Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to
pl011, regardless of the user-specified VERSAL_NET_CONSOLE value.
This causes a buil

fix(versal-net): runtime console in debug mode

Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to
pl011, regardless of the user-specified VERSAL_NET_CONSOLE value.
This causes a build requested with VERSAL_NET_CONSOLE=pl011_1 to
register both pl011_1 and pl011 as boot and runtime consoles. If the
hardware is connected only to UART1, this causes TF-A to hang when
UART0 is selected as the runtime console, since it waits indefinitely
on the transmit FIFO. The fix ensures that, in a DEBUG build,
CONSOLE_RUNTIME defaults to the same value as VERSAL_NET_CONSOLE.

Change-Id: Icad043a61f9d90480a8aceab701a5791d26e3d70
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(versal-net): add fallback on handoff failure

On the Versal-Net platform, booting can fail during ELF loading due to
the absence of a PLM handoff, preventing the system from booting
further.

To

fix(versal-net): add fallback on handoff failure

On the Versal-Net platform, booting can fail during ELF loading due to
the absence of a PLM handoff, preventing the system from booting
further.

To address this, a fallback mechanism has been introduced that allows
the boot process to continue even if the PLM handoff is not provided
only in debug builds with jtag boot mode.

Change-Id: Ib8d92ab8400b7a63b05ae8c77b40b30fe7abaab8
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes

refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes all GICR frames are
contiguous. This is the original method.

b) via gicv3_rdistif_probe() - called from platform code and requires
gicr_base == 0. It relaxes the requirement for frames to be
contiguous, like in a multichip configuration, and defers the
discovery to core bringup. This was introduced later.

Configurations possible with option a) are also possible with option b)
with only slightly different behaviour. USE_GIC_DRIVER=3 inherited
option b) from plat_gicv3_base.c and as such option a) is unusable.
However, it is unclear from code how this should be used. Clarify this
by requiring platforms initialise with gic_set_gicr_frames() and
adding relevant comments.

Also rename plat_arm_override_gicr_frames() to gic_set_gicr_frames() as
this is not plat arm specific and a part of the generic GIC driver.

Change-Id: I61d77211f8e65dc54cf9904069b500d26a06b5a5
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(versal-net): use the generic GIC driver

With the introduction of USE_GIC_DRIVER, platforms no longer have to do
their own GIC management for basic PSCI-related operations. Previously a
half

refactor(versal-net): use the generic GIC driver

With the introduction of USE_GIC_DRIVER, platforms no longer have to do
their own GIC management for basic PSCI-related operations. Previously a
half-measure was possible by using plat_gicv3_base.c to get semi-generic
helpers which versal_net uses.

Since USE_GIC_DRIVER is based on plat_gicv3_base.c, convert the platform
to use that so its code is more generic. Expected benefits are slightly
better performance around calling the gic hooks on cpu suspend and less
platform code.

Change-Id: I8e8a92fd4111e4a83c7a34bc5255d924bc54e769
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(arm): unify SPSR retrieval logic

Consolidate platform-specific SPSR setup logic into a single
arm_get_spsr() function that accepts an image_id to select between BL32
and BL33. This reduces

refactor(arm): unify SPSR retrieval logic

Consolidate platform-specific SPSR setup logic into a single
arm_get_spsr() function that accepts an image_id to select between BL32
and BL33. This reduces duplication and simplifies control over SPSR
generation for later stages, particularly BL33.

The SPD remains responsible for setting the SPSR for BL32.

Change-Id: Ibbba708d607e7676989f5c7ceffe33d7bb2195f1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(xilinx): add API to get powerdown request status

The pwrdwn_req_received variable is used across multiple platforms
through extern keyword. Instead of using the extern, add getter
API to access

fix(xilinx): add API to get powerdown request status

The pwrdwn_req_received variable is used across multiple platforms
through extern keyword. Instead of using the extern, add getter
API to access this variable across the platforms, and restrict the
scope of variable to the particular file by defining it as static
variable. This prevents unintended access of variable from other
files and increase safety.

Change-Id: I758466ea7f6be2a90ec249dc3e4fa56cdbe11e57
Signed-off-by: Devanshi Chauhan <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 4.5 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.4.5:
- Identifiers in the same name space with overlapping visibility should
be ty

fix(xilinx): resolve misra rule 4.5 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.4.5:
- Identifiers in the same name space with overlapping visibility should
be typographically unambiguous.
- Fix:
- Renamed PM_RET_ERROR_NOFEATURE to PM_RET_ERROR_IOCTL_NOT_SUPPORTED
and removed unnecessary macro definitions.

Change-Id: I6f03e619979685df7418fbccad7b0934d136776e
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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feat(versal-net): add SDEI support

Add basic SDEI support with following configuration settings:
- SGI 8 as the source IRQ.
- Special Private event 0.
- One private and shared dynamic event used in

feat(versal-net): add SDEI support

Add basic SDEI support with following configuration settings:
- SGI 8 as the source IRQ.
- Special Private event 0.
- One private and shared dynamic event used in tftf verification
for SDEI support.
- SDEI support is off by default.

Change-Id: I7cfafb84c3fc053ec67258698cf749e63486fe18
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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Merge changes I86959e67,I0b0d1d36,I5b5267f4,I056c8710,I3474aa97 into integration

* changes:
chore: fix preprocessor checks
refactor: convert arm platforms to use the generic GIC driver
refacto

Merge changes I86959e67,I0b0d1d36,I5b5267f4,I056c8710,I3474aa97 into integration

* changes:
chore: fix preprocessor checks
refactor: convert arm platforms to use the generic GIC driver
refactor(gic): promote most of the GIC driver to common code
refactor: make arm_gicv2.c and arm_gicv3.c common
refactor(fvp): use more arm generic code for gicv3

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refactor: make arm_gicv2.c and arm_gicv3.c common

These files were meant to be platform specific, but they are generic
enough that a range of platforms find them useful. However, refactoring
them is

refactor: make arm_gicv2.c and arm_gicv3.c common

These files were meant to be platform specific, but they are generic
enough that a range of platforms find them useful. However, refactoring
them is difficult as their use is platform specific. So copy them to a
generic place and redirect platforms to them.

The new copies will remain for compatibility for platforms that don't
want to or can't take up upcoming refactors and the old copies can be
drastically refactored to make them more widely applicable.

Change-Id: I056c8710cdda4d8a81b324d392762c29e02cdae1
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(versal-net): enable PSCI reset2 interface

Enable the PSCI reset2 interface for Versal NET. Since warm/soft reset
functionality is not supported in the Versal NET system, the reset2
implementatio

fix(versal-net): enable PSCI reset2 interface

Enable the PSCI reset2 interface for Versal NET. Since warm/soft reset
functionality is not supported in the Versal NET system, the reset2
implementation is aligned with the existing PSCI reset interface.

This implementation allows the external users to define
platform-specific actions for warm/soft reset within the reset2
handler if needed.

Change-Id: Ibb937e4c0994a29b45b9b19f8addad56fe7e7e23
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

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fix(versal-net): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I153d26bd92ea26efcd7f236e2f1d89c3e5442ba4
Signed-off-

fix(versal-net): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I153d26bd92ea26efcd7f236e2f1d89c3e5442ba4
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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refactor(xilinx): refactor console to support transfer list

Refactor console to support DTB console in case of transfer list.
Simplify logic where SOC specific macros are moved to platform headers
o

refactor(xilinx): refactor console to support transfer list

Refactor console to support DTB console in case of transfer list.
Simplify logic where SOC specific macros are moved to platform headers
or makefile where XLNX_DT_CFG macro describe if system is DT driven or not.

Change-Id: Id45c03a950b62e83e91a50e0485eacdb233ba745
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge "fix(versal-net): remove_redundant_lock_defs" into integration

Merge changes from topic "xlnx_fix_plat_single_ret" into integration

* changes:
fix(versal2): modify function to have single return
fix(versal-net): modify function to have single return
fix(v

Merge changes from topic "xlnx_fix_plat_single_ret" into integration

* changes:
fix(versal2): modify function to have single return
fix(versal-net): modify function to have single return
fix(versal): modify function to have single return
fix(xilinx): modify function to have single return
fix(zynqmp): modify function to have single return
fix(versal-net): add unsigned suffix to match data type
fix(versal): add unsigned suffix to match data type
fix(versal2): add missing curly braces
fix(versal-net): add missing curly braces
fix(zynqmp): add missing curly braces

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fix(versal-net): modify function to have single return

This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to stor

fix(versal-net): modify function to have single return

This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.

Change-Id: Ib8b3339f32031a3657f6c349763a20a99fd828e7
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(xilinx): dcc console tests failing

The commit a6485b2b3b2c ("refactor(delay-timer): add timer
callback functions") is breaking DCC console due to uninitialized
timer ops structure. Fix it by mov

fix(xilinx): dcc console tests failing

The commit a6485b2b3b2c ("refactor(delay-timer): add timer
callback functions") is breaking DCC console due to uninitialized
timer ops structure. Fix it by moving generic delay timer init
prior to console setup to make sure that time is setup before DCC
console setup.

Fixes: a6485b2b3b2c ("refactor(delay-timer): add timer callback
functions")

Change-Id: I67910332773741c0b08f02feb232efab6356db12
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(versal-net): add unsigned suffix to match data type

This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned

fix(versal-net): add unsigned suffix to match data type

This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned type.
Appended "u" suffix to integer constant to represent it as
unsigned type.

Change-Id: I08b055134d6bd0380cca1e5b6ee527d6045a76c5
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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