1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/cpus/cpu_ops.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <plat/common/platform.h> 22 #include <plat_arm.h> 23 #include <plat_console.h> 24 #include <scmi.h> 25 26 #include <def.h> 27 #include <plat_fdt.h> 28 #include <plat_private.h> 29 #include <plat_startup.h> 30 #include <plat_xfer_list.h> 31 #include <pm_api_sys.h> 32 #include <pm_client.h> 33 34 static entry_point_info_t bl32_image_ep_info; 35 static entry_point_info_t bl33_image_ep_info; 36 37 /* 38 * Return a pointer to the 'entry_point_info' structure of the next image for 39 * the security state specified. BL33 corresponds to the non-secure image type 40 * while BL32 corresponds to the secure image type. A NULL pointer is returned 41 * if the image does not exist. 42 */ 43 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 44 { 45 assert(sec_state_is_valid(type)); 46 47 if (type == NON_SECURE) { 48 return &bl33_image_ep_info; 49 } 50 51 return &bl32_image_ep_info; 52 } 53 54 /* 55 * Set the build time defaults,if we can't find any config data. 56 */ 57 static inline void bl31_set_default_config(void) 58 { 59 bl32_image_ep_info.pc = BL32_BASE; 60 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 61 #if defined(SPD_opteed) 62 /* NS dtb addr passed to optee_os */ 63 bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR; 64 #endif 65 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 66 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 67 DISABLE_ALL_EXCEPTIONS); 68 } 69 70 /* 71 * Perform any BL31 specific platform actions. Here is an opportunity to copy 72 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 73 * are lost (potentially). This needs to be done before the MMU is initialized 74 * so that the memory layout can be used while creating page tables. 75 */ 76 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 77 u_register_t arg2, u_register_t arg3) 78 { 79 (void)arg0; 80 (void)arg1; 81 (void)arg2; 82 (void)arg3; 83 uint32_t uart_clock; 84 #if (TRANSFER_LIST == 1) 85 int32_t rc; 86 bool tl_status = false; 87 #endif 88 89 board_detection(); 90 91 /* FIXME */ 92 switch (platform_id) { 93 case SPP: 94 switch (platform_version) { 95 case SPP_PSXC_MMI_V2_0: 96 cpu_clock = 770000; 97 break; 98 case SPP_PSXC_MMI_V3_0: 99 cpu_clock = 908000; 100 break; 101 default: 102 panic(); 103 } 104 break; 105 case SPP_MMD: 106 switch (platform_version) { 107 case SPP_PSXC_ISP_AIE_V2_0: 108 case SPP_PSXC_MMD_AIE_FRZ_EA: 109 case SPP_PSXC_MMD_AIE_V3_0: 110 cpu_clock = 760000; 111 break; 112 default: 113 panic(); 114 } 115 break; 116 case EMU: 117 case EMU_MMD: 118 cpu_clock = 112203; 119 break; 120 case QEMU: 121 /* Random values now */ 122 cpu_clock = 3333333; 123 break; 124 case SILICON: 125 cpu_clock = 100000000; 126 break; 127 default: 128 panic(); 129 } 130 #if (TRANSFER_LIST == 1) 131 tl_status = populate_data_from_xfer_list(); 132 if (tl_status != true) { 133 WARN("Invalid transfer list\n"); 134 } 135 #endif 136 137 uart_clock = get_uart_clk(); 138 139 /* Initialize the platform config for future decision making */ 140 config_setup(); 141 142 setup_console(); 143 144 NOTICE("TF-A running on %s v%d.%d, RTL v%d.%d, PS v%d.%d, PMC v%d.%d\n", 145 board_name_decode(), 146 (platform_version >> 1), platform_version % 10U, 147 (rtlversion >> 1), rtlversion % 10U, 148 (psversion >> 1), psversion % 10U, 149 (pmcversion >> 1), pmcversion % 10U); 150 151 /* 152 * Do initial security configuration to allow DRAM/device access. On 153 * Base only DRAM security is programmable (via TrustZone), but 154 * other platforms might have more programmable security devices 155 * present. 156 */ 157 158 /* Populate common information for BL32 and BL33 */ 159 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 160 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 161 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 162 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 163 164 #if (TRANSFER_LIST == 1) 165 rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info); 166 if (rc == TL_OPS_NON || rc == TL_OPS_CUS) { 167 NOTICE("BL31: TL not found, using default config\n"); 168 bl31_set_default_config(); 169 } 170 #else 171 bl31_set_default_config(); 172 #endif 173 174 long rev_var = cpu_get_rev_var(); 175 176 INFO("CPU Revision = 0x%lx\n", rev_var); 177 INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock); 178 NOTICE("BL31: Executing from 0x%x\n", BL31_BASE); 179 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 180 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 181 182 } 183 184 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 185 186 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 187 { 188 static uint32_t index; 189 uint32_t i; 190 int32_t ret = 0; 191 192 /* Validate 'handler' and 'id' parameters */ 193 if ((handler == NULL) || (index >= MAX_INTR_EL3)) { 194 ret = -EINVAL; 195 goto exit_label; 196 } 197 198 /* Check if a handler has already been registered */ 199 for (i = 0; i < index; i++) { 200 if (id == type_el3_interrupt_table[i].id) { 201 ret = -EALREADY; 202 goto exit_label; 203 } 204 } 205 206 type_el3_interrupt_table[index].id = id; 207 type_el3_interrupt_table[index].handler = handler; 208 209 index++; 210 211 exit_label: 212 return ret; 213 } 214 215 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 216 void *handle, void *cookie) 217 { 218 (void)id; 219 uint32_t intr_id; 220 uint32_t i; 221 interrupt_type_handler_t handler = NULL; 222 223 intr_id = plat_ic_get_pending_interrupt_id(); 224 225 for (i = 0; i < MAX_INTR_EL3; i++) { 226 if (intr_id == type_el3_interrupt_table[i].id) { 227 handler = type_el3_interrupt_table[i].handler; 228 } 229 } 230 231 if (handler != NULL) { 232 (void)handler(intr_id, flags, handle, cookie); 233 } 234 235 return 0; 236 } 237 238 void bl31_platform_setup(void) 239 { 240 prepare_dtb(); 241 242 /* Initialize the gic cpu and distributor interfaces */ 243 plat_gic_driver_init(); 244 plat_gic_init(); 245 246 if (platform_id != EMU) { 247 init_scmi_server(); 248 } 249 } 250 251 void bl31_plat_runtime_setup(void) 252 { 253 uint32_t flags = 0; 254 int32_t rc; 255 256 set_interrupt_rm_flag(flags, NON_SECURE); 257 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 258 rdo_el3_interrupt_handler, flags); 259 if (rc != 0) { 260 panic(); 261 } 262 263 console_switch_state(CONSOLE_FLAG_RUNTIME); 264 } 265 266 /* 267 * Perform the very early platform specific architectural setup here. 268 */ 269 void bl31_plat_arch_setup(void) 270 { 271 const mmap_region_t bl_regions[] = { 272 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 273 MT_MEMORY | MT_RW | MT_SECURE), 274 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 275 MT_CODE | MT_SECURE), 276 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 277 MT_RO_DATA | MT_SECURE), 278 MAP_REGION_FLAT(SMT_BUFFER_BASE, 0x1000, 279 MT_DEVICE | MT_RW | MT_NON_CACHEABLE | MT_EXECUTE_NEVER | MT_NS), 280 {0} 281 }; 282 283 setup_page_tables(bl_regions, plat_get_mmap()); 284 enable_mmu(0); 285 } 286