fix(xilinx): remove unused mailbox macros

All these macro are unused that's why remove them.

Change-Id: I843cc7c1a592c47376a01c52f45b6d59da80772b
Signed-off-by: Michal Simek <michal.simek@amd.com>

chore(xilinx): update print information

Remove company name from the console messages while printing only
relevant information for the platform.

Change-Id: Id8171326e0267eb6f3a26de4eb66143970de2dbd

chore(xilinx): update print information

Remove company name from the console messages while printing only
relevant information for the platform.

Change-Id: Id8171326e0267eb6f3a26de4eb66143970de2dbd
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

show more ...

fix(versal): print proper atf handoff source

Versal uses PLM in the boot flow and printing FSBL in the log for
handoff parameters is misleading. Print proper source of TF-A
handoff parameters.

Chan

fix(versal): print proper atf handoff source

Versal uses PLM in the boot flow and printing FSBL in the log for
handoff parameters is misleading. Print proper source of TF-A
handoff parameters.

Change-Id: I331e2eac2f5d30beed8573940ae02094254a759b
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

show more ...

fix: remove old-style declarations

TF-A wants to eventually enable -Wold-style-definition globally. Convert
the rare few instances where this is still the case.

Signed-off-by: Boyan Karatotev <boya

fix: remove old-style declarations

TF-A wants to eventually enable -Wold-style-definition globally. Convert
the rare few instances where this is still the case.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I9c450fc875cf097e6de2ed577ea3b085821c9f5e

show more ...

fix(versal): initialize the variable with value 0 in pm code

Remove zeromem function as the array is already initialized
with value 0.

MISRA Violation: MISRA C-2012 Rule 9.1
- Initialize the array/

fix(versal): initialize the variable with value 0 in pm code

Remove zeromem function as the array is already initialized
with value 0.

MISRA Violation: MISRA C-2012 Rule 9.1
- Initialize the array/variable with a value 0 to resolve
the misra warnings in pm_service component.

Signed-off-by: Naman Patel <naman.patel@amd.com>
Change-Id: I1a3d44a7ae4088a3034eb0119d82b99cd4617ccd

show more ...

fix(zynqmp): resolve coverity warnings

Fix for coverity issues in pm_service component.
Fixed compilation error for versal platform.

Change-Id: I948f01807e67ad1e41021557e040dcbfb7b3a39e
Signed-off-

fix(zynqmp): resolve coverity warnings

Fix for coverity issues in pm_service component.
Fixed compilation error for versal platform.

Change-Id: I948f01807e67ad1e41021557e040dcbfb7b3a39e
Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>
Signed-off-by: Naman Patel <naman.patel@amd.com>

show more ...

fix(versal): enable a72 erratum 859971 and 1319367

TF-A is reporting that above two erratum are missing to be enabled that's
why enable them by default.

For futher information please refer to
https

fix(versal): enable a72 erratum 859971 and 1319367

TF-A is reporting that above two erratum are missing to be enabled that's
why enable them by default.

For futher information please refer to
https://developer.arm.com/documentation/epm012079/11/

where
859971 is "Speculative instruction prefetch to Execute-never (XN) memory
could cause deadlock or data integrity issue" and
1319367 is "Speculative AT instruction using out-of-context translation
regime could cause subsequent request to generate an incorrect
translation".

Change-Id: I408706713a169e53db63ac5657751b0b003e646d
Signed-off-by: Michal Simek <michal.simek@amd.com>

show more ...

Merge "feat(versal): update macro name to generic and move to common place" into integration

Merge "fix(versal): route GIC IPI interrupts during setup" into integration

fix(versal): route GIC IPI interrupts during setup

If primary core is down, then IPI interrupt should be
routed to another core for processing.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Chan

fix(versal): route GIC IPI interrupts during setup

If primary core is down, then IPI interrupt should be
routed to another core for processing.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I01d7c4232a18c0c3b3f3f9ddadfa6ff5bd2f2471

show more ...

chore(versal): add missing dot at the end of sentence

Add missing dot at the end of sentence.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I356e65fd8c572c12795e3492dd02d73f48cb4b67

fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main

Fix some Misra-C violations. The similar fixes were done by commit
eb0d2b17722c ("fix(zynqmp): resolve misra R15.6 warnings") and co

fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main

Fix some Misra-C violations. The similar fixes were done by commit
eb0d2b17722c ("fix(zynqmp): resolve misra R15.6 warnings") and commit
dd1fe7178b57 ("fix(zynqmp): resolve misra R14.4 warnings").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I3ffa92724a09871f7f99c9ac6c326994c165e9bd

show more ...

feat(versal): update macro name to generic and move to common place

Update TZ_VERSION macro name to generic macro name and move to
common header file so that it can be used for keystoneb.

Signed-of

feat(versal): update macro name to generic and move to common place

Update TZ_VERSION macro name to generic macro name and move to
common header file so that it can be used for keystoneb.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Acked-by: Tanmay Shah <tanmay.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic3819eea78b6c7b51ffaa13081026dd191b76125

show more ...

feat(versal): add infrastructure to handle multiple interrupts

Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infras

feat(versal): add infrastructure to handle multiple interrupts

Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e

show more ...

fix(versal): add SGI register call version check

PM_FEATURE_CHECK is supported only for platform
management API. PM_LOAD_PDI command is not intended
for platform management. This patch removes versi

fix(versal): add SGI register call version check

PM_FEATURE_CHECK is supported only for platform
management API. PM_LOAD_PDI command is not intended
for platform management. This patch removes version
check of PM_LOAD_PDI and adds version check of command
that is used for SGI registartion.

Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
Change-Id: I353163109b639acab73120f405a811770e8831a0

show more ...

Merge "fix(versal): use only one space for indentation" into integration

fix(versal): use only one space for indentation

Trivial patch to remove additional space.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ifa33dee81243c0b21ca0f13b8e4d575646818162

fix(versal): fix code indentation issues

Next line should be aligned with the previous code.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I20d82ba5fa70fa252341b62e57fac265241f3391

fix(versal): fix macro coding style issues

Use only one space between #define and macro name.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ieb9bdd5bcfa56bd265df72692a09c7340fe132cb

fix(versal): resolve misra 10.1 warnings

MISRA Violation: MISRA-C: 2012 R.10.1
-The operand to the operator does not have an essentially
unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <venk

fix(versal): resolve misra 10.1 warnings

MISRA Violation: MISRA-C: 2012 R.10.1
-The operand to the operator does not have an essentially
unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4873a620086dfd6f636fe730165a9d13a29e9652

show more ...

fix(versal): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Signed-off-by:

fix(versal): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ieff90b5311a3bde8a2cb302ca81c23eeee6d235a

show more ...

fix(xilinx): miscellaneous fixes for xilinx platforms

This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.

Signed-off-by: Michal S

fix(xilinx): miscellaneous fixes for xilinx platforms

This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4cdb89ffec7d5abc64e065ed5b5e5d10b30ab9f9

show more ...

fix(versal): remove clock related macros

TF-A doesn't configure clock on Versal. Setup is done by previous
bootloader (called PLM) that's why there is no need to have macro listed in
headers. Also p

fix(versal): remove clock related macros

TF-A doesn't configure clock on Versal. Setup is done by previous
bootloader (called PLM) that's why there is no need to have macro listed in
headers. Also previous phase can disable access to these registers that's
why better to remove them.

Change-Id: I53ba344ad932c532b0babdce9d2b26e4c2c1b846
Signed-off-by: Michal Simek <michal.simek@amd.com>

show more ...

feat(versal): resolve the misra 10.1 warnings

MISRA Violation: MISRA-C:2012 R.10.1
-The operand to the operator does not have an essentially unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <

feat(versal): resolve the misra 10.1 warnings

MISRA Violation: MISRA-C:2012 R.10.1
-The operand to the operator does not have an essentially unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I9cde2f1ebceaad8a41c69489ef1d2e6f21f04ed1

show more ...

feat(versal): get the handoff params using IPI

Use the IPI command GET_HANDOFF_PARAM to get the TF-A handoff
params, rather than using the PLM's PPU RAM area. With this
approach this resolves the is

feat(versal): get the handoff params using IPI

Use the IPI command GET_HANDOFF_PARAM to get the TF-A handoff
params, rather than using the PLM's PPU RAM area. With this
approach this resolves the issue when XPPU is enabled.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Change-Id: I6828c391ad696d2d36e994684aa21b023711ba2d

show more ...