| 86d9b35f | 02-Oct-2025 |
Madhav Bhatt <madhav.bhatt@amd.com> |
fix(versal): remove client-side implementation of PM_ABORT_SUSPEND
PM_ABORT_SUSPEND API is removed; client-side implementation is no longer needed.
Change-Id: I34ac563b88b98e484cf33993545c0151db936
fix(versal): remove client-side implementation of PM_ABORT_SUSPEND
PM_ABORT_SUSPEND API is removed; client-side implementation is no longer needed.
Change-Id: I34ac563b88b98e484cf33993545c0151db9362e0 Signed-off-by: Madhav Bhatt <madhav.bhatt@amd.com>
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| c96f838a | 01-Oct-2025 |
Devanshi Chauhan <devanshi.chauhan@amd.com> |
fix(versal): modify IPI4 and IPI5 trigger bit definitions
The IPI4 and IPI5 trigger bit definitions are incorrect according to the register database specification. This discrepancy can cause IPI com
fix(versal): modify IPI4 and IPI5 trigger bit definitions
The IPI4 and IPI5 trigger bit definitions are incorrect according to the register database specification. This discrepancy can cause IPI communication failures between processing units in Versal SoCs. So, modified the trigger bits to align the software definitions with the hardware register specification as documented in the register database.
Change-Id: I1e32961124daf8e5635906fb615e98a650130f27 Signed-off-by: Devanshi Chauhan <devanshi.chauhan@amd.com>
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| 4fd510e0 | 02-Sep-2025 |
Ronak Jain <ronak.jain@amd.com> |
feat(xilinx): use common SECURE/NON_SECURE macro
Remove platform-specific macro definitions such as SECURE_FLAG and NON_SECURE_FLAG, and replace them with the common macros SECURE and NON_SECURE acr
feat(xilinx): use common SECURE/NON_SECURE macro
Remove platform-specific macro definitions such as SECURE_FLAG and NON_SECURE_FLAG, and replace them with the common macros SECURE and NON_SECURE across all AMD-Xilinx platforms.
Change-Id: I95465e29ac8a9370da135c2113203c3206ecfec0 Signed-off-by: Ronak Jain <ronak.jain@amd.com>
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| 3e3cdf26 | 29-Aug-2025 |
Ronak Jain <ronak.jain@amd.com> |
fix(xilinx): incorrect usage of SECURE_FLAG for psci
As per the PSCI specification, the PSCI SMC call always expects from the NON_SECURE world. However, in the platform specific file SECURE flag was
fix(xilinx): incorrect usage of SECURE_FLAG for psci
As per the PSCI specification, the PSCI SMC call always expects from the NON_SECURE world. However, in the platform specific file SECURE flag was passed to the firmware which is incorrect. Pass NON_SECURE flag from the platform specific file to the firmware in order to align with the PSCI specification.
Change-Id: Iabe2cb45467cf63fe36626d323513ff05548eb3b Signed-off-by: Ronak Jain <ronak.jain@amd.com>
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| 5cac1d85 | 20-Aug-2025 |
Ronak Jain <ronak.jain@amd.com> |
fix(xilinx): fix missing security flag in suspend path
Suspend flow was always programming wakeup sources with a fixed secure flag, regardless of whether the caller was secure or non-secure. This ma
fix(xilinx): fix missing security flag in suspend path
Suspend flow was always programming wakeup sources with a fixed secure flag, regardless of whether the caller was secure or non-secure. This may cause incorrect behavior for non-secure suspend requests.
Fix this by passing the caller's security state (flag) through pm_client_suspend() and pm_client_set_wakeup_sources() to ensure that wakeup sources are set with the correct context.
Fixes: <4697164a3fa8> ("plat: xilinx: versal: Mark IPI calls secure/non-secure")
Change-Id: I5fcf65788a54010b4759b0d08e4f54c6e5037e47 Signed-off-by: Ronak Jain <ronak.jain@amd.com>
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| 5c06747a | 26-Aug-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes from topic "xlnx_misra_fix_gen_arm" into integration
* changes: fix(arm-drivers): add missing curly braces fix(arm): typecast operands to match data type fix(arm-drivers): declar
Merge changes from topic "xlnx_misra_fix_gen_arm" into integration
* changes: fix(arm-drivers): add missing curly braces fix(arm): typecast operands to match data type fix(arm-drivers): declare unused parameters as void
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| 1cbf6c4a | 22-Aug-2025 |
Saivardhan Thatikonda <saivardhan.thatikonda@amd.com> |
fix(versal): update integer const with suffix U
Versal: standardize unsigned integer constants to use suffix. Updated all unsigned integer constants in the Versal platform to use the unsigned suffix
fix(versal): update integer const with suffix U
Versal: standardize unsigned integer constants to use suffix. Updated all unsigned integer constants in the Versal platform to use the unsigned suffix (e.g., `10U`) instead of the prefix style (e.g., `U(10)`) for consistency.
Change-Id: Ie4d20c18cccede20062d6189c1024acfb3a3dce0 Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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| 0701792f | 12-Aug-2025 |
Prasad Kummari <prasad.kummari@amd.com> |
fix(versal): runtime console in debug mode
Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to pl011, regardless of the user-specified VERSAL_CONSOLE value. This causes a build reques
fix(versal): runtime console in debug mode
Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to pl011, regardless of the user-specified VERSAL_CONSOLE value. This causes a build requested with VERSAL_CONSOLE=pl011_1 to register both pl011_1 and pl011 as boot and runtime consoles. If the hardware is connected only to UART1, this causes TF-A to hang when UART0 is selected as the runtime console, since it waits indefinitely on the transmit FIFO. The fix ensures that, in a DEBUG build, CONSOLE_RUNTIME defaults to the same value as VERSAL_CONSOLE.
Change-Id: I7aeedb04040ea4ab4b8aecde98af5cc39df09c1a Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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| 4e89096a | 30-Jun-2025 |
Saivardhan Thatikonda <saivardhan.thatikonda@amd.com> |
fix(versal): match function type as its declared
This corrects the MISRA violation C2012-8.3: matching the type of function definition as per its declaration.
Change-Id: Ibeaee37a30d02e9a7638c94705
fix(versal): match function type as its declared
This corrects the MISRA violation C2012-8.3: matching the type of function definition as per its declaration.
Change-Id: Ibeaee37a30d02e9a7638c94705dfa4b433a35bf6 Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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| 5d8831c2 | 06-Feb-2025 |
Saivardhan Thatikonda <saivardhan.thatikonda@amd.com> |
fix(versal): typecast operands to match data type
This corrects the MISRA violation C2012-10.3: The value of an expression shall not be assigned to an object with a narrower essential type or of a d
fix(versal): typecast operands to match data type
This corrects the MISRA violation C2012-10.3: The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category
Change-Id: I83294b6a74378a927a639777ac7261a1375e13a1 Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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| f7092652 | 28-Jan-2025 |
Saivardhan Thatikonda <saivardhan.thatikonda@amd.com> |
fix(versal): replace ull with ULL to fix misra violation
This corrects the MISRA violation C2012-7.3: The issue is because the numeric literal "1ull" uses a lowercase 'l' to specify its type. 'l' ca
fix(versal): replace ull with ULL to fix misra violation
This corrects the MISRA violation C2012-7.3: The issue is because the numeric literal "1ull" uses a lowercase 'l' to specify its type. 'l' can be visually ambiguous when placed next to digits, especially with '1', Replacing "ull" with "ULL" is avoids the confusion and fixes the issue.
Change-Id: I204d90316ea3bfec314c284284a423618274c87b Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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| c1b0a52b | 27-Jan-2025 |
Saivardhan Thatikonda <saivardhan.thatikonda@amd.com> |
fix(versal): typecast operands to match data type
This corrects the MISRA violation C2012-10.3: The value/data/return type of a variable/function in an expression shall not be assigned to an object
fix(versal): typecast operands to match data type
This corrects the MISRA violation C2012-10.3: The value/data/return type of a variable/function in an expression shall not be assigned to an object with a narrower essential type or of a different essential type category.
Change-Id: I28b41e74d4c32829faaf786234c12207b5b32f29 Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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| 5b51d4de | 27-Jan-2025 |
Saivardhan Thatikonda <saivardhan.thatikonda@amd.com> |
fix(versal): match function declaration with its definition
This corrects the MISRA violation C2012-4.6: The function declaration shall be match with whose definition. In this case, 'int32_t' needs
fix(versal): match function declaration with its definition
This corrects the MISRA violation C2012-4.6: The function declaration shall be match with whose definition. In this case, 'int32_t' needs to be replaced with 'int' in the function declaration.
Change-Id: I15f1f5f93a904c057af86da4c22d4fd2b9c7a7eb Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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| 33a264cb | 27-Jan-2025 |
Saivardhan Thatikonda <saivardhan.thatikonda@amd.com> |
fix(versal): add external declaration
This corrects the MISRA violation C2012-8.4: A compatible declaration shall be visible when an object or function with external linkage is defined. In this case
fix(versal): add external declaration
This corrects the MISRA violation C2012-8.4: A compatible declaration shall be visible when an object or function with external linkage is defined. In this case function declaration is available in "platform.h".
Change-Id: Ia493b18e563f4d89dc3cbde791aece3c101360ba Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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| 01907f3f | 04-Jul-2025 |
Harrison Mutai <harrison.mutai@arm.com> |
refactor(arm): unify SPSR retrieval logic
Consolidate platform-specific SPSR setup logic into a single arm_get_spsr() function that accepts an image_id to select between BL32 and BL33. This reduces
refactor(arm): unify SPSR retrieval logic
Consolidate platform-specific SPSR setup logic into a single arm_get_spsr() function that accepts an image_id to select between BL32 and BL33. This reduces duplication and simplifies control over SPSR generation for later stages, particularly BL33.
The SPD remains responsible for setting the SPSR for BL32.
Change-Id: Ibbba708d607e7676989f5c7ceffe33d7bb2195f1 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| 8a131571 | 09-Apr-2025 |
Saivardhan Thatikonda <saivardhan.thatikonda@amd.com> |
fix(arm): typecast operands to match data type
This corrects the MISRA violation C2012-10.3: The value of an expression shall not be assigned to an object with a narrower essential type or of a diff
fix(arm): typecast operands to match data type
This corrects the MISRA violation C2012-10.3: The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison.
Change-Id: I04089721d124a2701e10d3f6e0ed8f82e3f6e0b3 Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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| c0719d21 | 16-May-2025 |
Devanshi Chauhan <devanshi.chauhanalpeshbhai@amd.com> |
fix(xilinx): add API to get powerdown request status
The pwrdwn_req_received variable is used across multiple platforms through extern keyword. Instead of using the extern, add getter API to access
fix(xilinx): add API to get powerdown request status
The pwrdwn_req_received variable is used across multiple platforms through extern keyword. Instead of using the extern, add getter API to access this variable across the platforms, and restrict the scope of variable to the particular file by defining it as static variable. This prevents unintended access of variable from other files and increase safety.
Change-Id: I758466ea7f6be2a90ec249dc3e4fa56cdbe11e57 Signed-off-by: Devanshi Chauhan <devanshi.chauhanalpeshbhai@amd.com>
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| adbcd85e | 29-May-2025 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_versal_custom_sip" into integration
* changes: feat(versal): add hooks for mmap and early setup refactor(zynqmp): refactor custom sip service |
| 72b9f52d | 10-Apr-2025 |
Prasad Kummari <prasad.kummari@amd.com> |
feat(versal): add hooks for mmap and early setup
Add early setup hooks through custom_early_setup() and provide a mechanism to support custom memory mapping, including the extension of the memory ma
feat(versal): add hooks for mmap and early setup
Add early setup hooks through custom_early_setup() and provide a mechanism to support custom memory mapping, including the extension of the memory map via custom_mmap_add(). This change may also require alignment of the MAX_XLAT_TABLE and MAX_XLAT_TABLES macros. These can be defined within the custom_pkg.mk makefile as follows:
MAX_MMAP_REGIONS := XY $(eval $(call add_define,MAX_MMAP_REGIONS)) MAX_XLAT_TABLES := XZ $(eval $(call add_define,MAX_XLAT_TABLES))
If PLATFORM_STACK_SIZE is not already defined, a default value should be used. This allows for configurability of the stack size across different interfaces, such as custom packages. The custom_early_setup() function enables early low-level operations to bring the system into a correct state. Support for a custom SiP service is also added. A basic implementation of custom_smc_handler() is provided by the platform, while the actual definition is expected to be supplied by the custom package. This feature is designed for use by external libraries, such as those that require status checking. This code introduces a generic framework for integrating custom logic via the $(CUSTOM_PKG_PATH)/custom_pkg.mk makefile, including optional support for custom SMC functionality, which is determined by the custom package.
Change-Id: If9107b32c8c1ca4026d0a2980901e841fc6e03f7 Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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| c429afa2 | 02-May-2025 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_versal_misra_fixes" into integration
* changes: fix(xilinx): resolve misra rule 2.3 violations fix(xilinx): resolve misra rule 2.7 violations fix(xilinx): resolv
Merge changes from topic "xlnx_versal_misra_fixes" into integration
* changes: fix(xilinx): resolve misra rule 2.3 violations fix(xilinx): resolve misra rule 2.7 violations fix(xilinx): resolve misra rule 8.6 violations fix(xilinx): resolve misra rule 11.3 violations fix(xilinx): resolve misra rule 2.2 violations fix(xilinx): resolve misra rule 15.7 violations
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| d87b0ce3 | 24-Mar-2025 |
Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com> |
fix(xilinx): resolve misra rule 2.7 violations
Fixed below MISRA violation: - MISRA Violation: MISRA-C:2012 R.2.7: - There should be no unused parameters in functions. - Fix: - Type casted unuse
fix(xilinx): resolve misra rule 2.7 violations
Fixed below MISRA violation: - MISRA Violation: MISRA-C:2012 R.2.7: - There should be no unused parameters in functions. - Fix: - Type casted unused parameters to void.
Change-Id: I940109631dbabfbd960c1bc7b183cf865ff312c9 Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>
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| 4b4080d7 | 18-Mar-2025 |
Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com> |
fix(xilinx): resolve misra rule 8.4 violations
Fixed below MISRA violation: - MISRA Violation: MISRA-C:2012 R.8.4: - A compatible declaration shall be visible when an object or function with e
fix(xilinx): resolve misra rule 8.4 violations
Fixed below MISRA violation: - MISRA Violation: MISRA-C:2012 R.8.4: - A compatible declaration shall be visible when an object or function with external linkage is defined. - Fix: - Declared variable as static.
Change-Id: I44a022de3d5a62d255e2481dc1f4d1e8df2c7eb0 Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>
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| 3df32f85 | 18-Mar-2025 |
Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com> |
fix(xilinx): resolve misra rule 8.3 violations
Fixed below MISRA violation: - MISRA Violation: MISRA-C:2012 R.8.3: - All declarations of an object or function shall use the same names and type
fix(xilinx): resolve misra rule 8.3 violations
Fixed below MISRA violation: - MISRA Violation: MISRA-C:2012 R.8.3: - All declarations of an object or function shall use the same names and type qualifiers. - Fix: - Made same name parameters and type qualifiers in function declaration and definition.
Change-Id: Idb4f986cec957102bb4ba1ef22f2e7937aaeb54d Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>
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| bdba3c84 | 26-Mar-2025 |
Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com> |
fix(xilinx): resolve misra rule 10.4 violations
Fixed below MISRA violation: - MISRA Violation: MISRA-C:2012 R.10.4: - Both operands of an operator in which the usual arithmetic conversions ar
fix(xilinx): resolve misra rule 10.4 violations
Fixed below MISRA violation: - MISRA Violation: MISRA-C:2012 R.10.4: - Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category. - Fix: - Made data type same for both the operands.
Change-Id: I0cea19477f3c10265d95ea1d5d2ea151dbf174bb Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>
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| 72eb16b7 | 26-Mar-2025 |
Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com> |
fix(xilinx): resolve misra rule 10.3 violations
Fixed below MISRA violation: - MISRA Violation: MISRA-C:2012 R.10.3: - The value of an expression shall not be assigned to an object with a narr
fix(xilinx): resolve misra rule 10.3 violations
Fixed below MISRA violation: - MISRA Violation: MISRA-C:2012 R.10.3: - The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. - Fix: - Explicitly type casted to narrower essential type or of a different essential type category.
Change-Id: Ia4258d2d0655f7847f832804a13d182ac0a2a29b Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>
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