xref: /rk3399_ARM-atf/plat/st/stm32mp1/stm32mp1_dbgmcu.c (revision 73680c230f8503a8e0f625834bc987b90e065b03)
1 /*
2  * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <errno.h>
8 
9 #include <platform_def.h>
10 
11 #include <common/debug.h>
12 #include <drivers/st/bsec.h>
13 #include <drivers/st/stm32mp1_rcc.h>
14 #include <lib/mmio.h>
15 #include <lib/utils_def.h>
16 
17 #include <stm32mp1_dbgmcu.h>
18 
19 #define DBGMCU_APB4FZ1		U(0x2C)
20 #define DBGMCU_APB4FZ1_IWDG2	BIT(2)
21 
22 static uintptr_t get_rcc_base(void)
23 {
24 	/* This is called before stm32mp_rcc_base() is available */
25 	return RCC_BASE;
26 }
27 
28 static int stm32mp1_dbgmcu_init(void)
29 {
30 	uint32_t dbg_conf;
31 	uintptr_t rcc_base = get_rcc_base();
32 
33 	dbg_conf = bsec_read_debug_conf();
34 
35 	if ((dbg_conf & BSEC_DBGSWGEN) == 0U) {
36 		uint32_t result = bsec_write_debug_conf(dbg_conf |
37 							BSEC_DBGSWGEN);
38 
39 		if (result != BSEC_OK) {
40 			ERROR("Error enabling DBGSWGEN\n");
41 			return -1;
42 		}
43 	}
44 
45 	mmio_setbits_32(rcc_base + RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
46 
47 	return 0;
48 }
49 
50 int stm32mp1_dbgmcu_freeze_iwdg2(void)
51 {
52 	uint32_t dbg_conf;
53 
54 	if (stm32mp1_dbgmcu_init() != 0) {
55 		return -EPERM;
56 	}
57 
58 	dbg_conf = bsec_read_debug_conf();
59 
60 	if ((dbg_conf & (BSEC_SPIDEN | BSEC_SPINDEN)) != 0U) {
61 		mmio_setbits_32(DBGMCU_BASE + DBGMCU_APB4FZ1,
62 				DBGMCU_APB4FZ1_IWDG2);
63 	}
64 
65 	return 0;
66 }
67