| #
03baf340 |
| 08-Nov-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "docs(qemu): mention a55 in list of v8.2 cores" into integration
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| #
c41b16ea |
| 08-Nov-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
docs(qemu): mention a55 in list of v8.2 cores
Change-Id: Ib3a1711be323023cf111373111f39038fa23fb6f
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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| #
78b3792a |
| 19-Sep-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(qemu): add "neoverse-n2" cpu support" into integration
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| #
408f9cb4 |
| 15-Sep-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
feat(qemu): add "neoverse-n2" cpu support
Add support to qemu "neoverse-n2" cpu for "qemu" platform.
This one has 2^48 address space so will be used by both systems.
Signed-off-by: Marcin Juszkiewi
feat(qemu): add "neoverse-n2" cpu support
Add support to qemu "neoverse-n2" cpu for "qemu" platform.
This one has 2^48 address space so will be used by both systems.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I9f0fa23a4934d9464379495225e08adc121325b4
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| #
d4635e99 |
| 15-Sep-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(qemu): add A55 cpu support for virt" into integration
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| #
512e0be0 |
| 13-Sep-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(qemu): add "cortex-a710" cpu support" into integration
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| #
409c20c8 |
| 13-Sep-2023 |
Mark-PK Tsai <mark-pk.tsai@mediatek.com> |
feat(qemu): add A55 cpu support for virt
Add support to "cortex-a55" cpu for "qemu" ('virt') platform.
Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Change-Id: I2693892be735eda91494b76732
feat(qemu): add A55 cpu support for virt
Add support to "cortex-a55" cpu for "qemu" ('virt') platform.
Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Change-Id: I2693892be735eda91494b767322935ddb63c9f48
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| #
4734a62d |
| 12-Sep-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
feat(qemu): add "cortex-a710" cpu support
Add support to qemu "cortex-a710" cpu for "qemu" platform.
CPU is supported by qemu/virt only as qemu/sbsa-ref memory starts at
2^40 which is limit for Cor
feat(qemu): add "cortex-a710" cpu support
Add support to qemu "cortex-a710" cpu for "qemu" platform.
CPU is supported by qemu/virt only as qemu/sbsa-ref memory starts at
2^40 which is limit for Cortex-A710.
Switched 'qemu' platform to be built as armv8.5 to cover features of
new cpu core.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I035790eac41b2caf7f13167e53f48c16f0827754
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| #
9e14faac |
| 23-Aug-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "refactor(qemu): handle pointer authentication" into integration
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| #
51ce1f34 |
| 21-Aug-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): handle pointer authentication
Pointer authentication requires CTX_INCLUDE_PAUTH_REGS to be defined.
Change-Id: I4ca95d6d9e619e7a7296a2c3ecb799683bf70575
Signed-off-by: Marcin Juszki
refactor(qemu): handle pointer authentication
Pointer authentication requires CTX_INCLUDE_PAUTH_REGS to be defined.
Change-Id: I4ca95d6d9e619e7a7296a2c3ecb799683bf70575
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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| #
f56da5d3 |
| 22-Aug-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "unify-qemu-machines" into integration
* changes:
refactor(qemu): move options to start of file
refactor(qemu): keep AArch64 cpu flags in one section
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| #
4993e8f5 |
| 22-Aug-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "unify-qemu-machines" into integration
* changes:
refactor(qemu): handle SPM_MM builds
refactor(qemu): handle AArch64 flags
refactor(qemu): common cpu features enablem
Merge changes from topic "unify-qemu-machines" into integration
* changes:
refactor(qemu): handle SPM_MM builds
refactor(qemu): handle AArch64 flags
refactor(qemu): common cpu features enablement
refactor(qemu): common BL31 sources
refactor(qemu): common BL1/2 sources
refactor(qemu): move CPU definitions into one place
refactor(qemu): move FDT stuff into one place
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| #
035c6da4 |
| 21-Aug-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): keep AArch64 cpu flags in one section
There is no need to have two "if" checks for same thing one after
another.
FGT, RNG, SVE, SME are aarch64 only flags.
Change-Id: I6e5850211c85
refactor(qemu): keep AArch64 cpu flags in one section
There is no need to have two "if" checks for same thing one after
another.
FGT, RNG, SVE, SME are aarch64 only flags.
Change-Id: I6e5850211c859dc7a4ccf6bc8dc6a8d600ffe692
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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| #
941fc383 |
| 24-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): handle SPM_MM builds
SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:
> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14
refactor(qemu): handle SPM_MM builds
SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:
> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14: *** "Error: SPM_MM is not compatible with ENABLE_SVE_FOR_NS". Stop.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Iabe181647fce00a432ae11dc4599b71619364c24
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| #
3b61457b |
| 24-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): handle AArch64 flags
Handle coherency in one place for AArch64 mode.
Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linar
refactor(qemu): handle AArch64 flags
Handle coherency in one place for AArch64 mode.
Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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| #
c1baf178 |
| 24-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): common cpu features enablement
Enable SVE, SME, RNG, FGT in one place.
qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG
Signed-off-by: Marcin Juszkiewicz <ma
refactor(qemu): common cpu features enablement
Enable SVE, SME, RNG, FGT in one place.
qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I2e8f971ef3e42d9ebe9f20641b288cc8c40f806a
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| #
18884750 |
| 24-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): common BL31 sources
Move BL31 source list into common file.
Change-Id: Iaa27cfd8f87b691728379c87a6ff6331e87951e1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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| #
71f5359b |
| 24-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): common BL1/2 sources
Move BL1 and BL2 source list into common file.
Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro
refactor(qemu): common BL1/2 sources
Move BL1 and BL2 source list into common file.
Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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| #
886688d1 |
| 24-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): move CPU definitions into one place
Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not
refactor(qemu): move CPU definitions into one place
Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not matter.
Change-Id: I5b8f7d18dc903e86e0cc7babbc2fb3f26a1bfdfa
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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| #
a63cdc74 |
| 24-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): move FDT stuff into one place
Move libfdt includes into common file and use definitions from them.
Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkie
refactor(qemu): move FDT stuff into one place
Move libfdt includes into common file and use definitions from them.
Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
show more ...
|