Merge changes I17523700,Ic05f3227,Id9c509a5 into integration

* changes:
feat(qemu): add support for FEAT_GCS
feat(qemu): add support for FEAT_SxPxE
feat(qemu): add support for FEAT_TCR2 and FE

Merge changes I17523700,Ic05f3227,Id9c509a5 into integration

* changes:
feat(qemu): add support for FEAT_GCS
feat(qemu): add support for FEAT_SxPxE
feat(qemu): add support for FEAT_TCR2 and FEAT_SCTLR2

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feat(qemu): add support for FEAT_GCS

Auto-detect FEAT_GCS and enable it when the platform supports it.
This is needed for Linux under QEMU 10.2

Change-Id: I175237006d3808bc058499a34357918674a0c561

feat(qemu): add support for FEAT_GCS

Auto-detect FEAT_GCS and enable it when the platform supports it.
This is needed for Linux under QEMU 10.2

Change-Id: I175237006d3808bc058499a34357918674a0c561
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): add support for FEAT_SxPxE

Auto-detect the POE and PIE features and enable them when the platform
supports them. This is needed for Linux under QEMU 10.2.

Change-Id: Ic05f3227e61386b06a

feat(qemu): add support for FEAT_SxPxE

Auto-detect the POE and PIE features and enable them when the platform
supports them. This is needed for Linux under QEMU 10.2.

Change-Id: Ic05f3227e61386b06a1deffce8678048aed456b1
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): add support for FEAT_TCR2 and FEAT_SCTLR2

QEMU supports this since 10.1.
ENABLE_FEAT_TCR2 is needed to boot a Linux guest.
ENABLE_FEAT_SCTLR2 is needed to boot a Linux nested guest.

Cha

feat(qemu): add support for FEAT_TCR2 and FEAT_SCTLR2

QEMU supports this since 10.1.
ENABLE_FEAT_TCR2 is needed to boot a Linux guest.
ENABLE_FEAT_SCTLR2 is needed to boot a Linux nested guest.

Change-Id: Id9c509a530fb5d0df9955f80ef26992d5bea1191
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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Merge changes Id942c20c,Idd286bea,I8917a26e,Iec8c3477,If3c25dcd, ... into integration

* changes:
feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED
perf(cpufeat): centralise PAuth key saving

Merge changes Id942c20c,Idd286bea,I8917a26e,Iec8c3477,If3c25dcd, ... into integration

* changes:
feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED
perf(cpufeat): centralise PAuth key saving
refactor(cpufeat): convert FEAT_PAuth setup to C
refactor(cpufeat): prepare FEAT_PAuth for FEATURE_DETECTION
chore(cpufeat): remove PAuth presence checks
feat(cpufeat): enable FEAT_BTI to FEAT_STATE_CHECKED

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feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED

FEAT_PAuth is the second to last feature to be a boolean choice - it's
either unconditionally compiled in and must be present in hardware or
it

feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED

FEAT_PAuth is the second to last feature to be a boolean choice - it's
either unconditionally compiled in and must be present in hardware or
it's not compiled in. FEAT_PAuth is architected to be backwards
compatible - a subset of the branch guarding instructions (pacia/autia)
execute as NOPs when PAuth is not present. That subset is used with
`-mbranch-protection=standard` and -march pre-8.3. This patch adds the
necessary logic to also check accesses of the non-backward compatible
registers and allow a fully checked implementation.

Note that a checked support requires -march to be pre 8.3, as otherwise
the compiler will include branch protection instructions that are not
NOPs without PAuth (eg retaa) which cannot be checked.

Change-Id: Id942c20cae9d15d25b3d72b8161333642574ddaa
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "bk/errata_speed" into integration

* changes:
refactor(cpus): declare runtime errata correctly
perf(cpus): make reset errata do fewer branches
perf(cpus): inline the i

Merge changes from topic "bk/errata_speed" into integration

* changes:
refactor(cpus): declare runtime errata correctly
perf(cpus): make reset errata do fewer branches
perf(cpus): inline the init_cpu_data_ptr function
perf(cpus): inline the reset function
perf(cpus): inline the cpu_get_rev_var call
perf(cpus): inline cpu_rev_var checks
refactor(cpus): register DSU errata with the errata framework's wrappers
refactor(cpus): convert checker functions to standard helpers
refactor(cpus): convert the Cortex-A65 to use the errata framework
fix(cpus): declare reset errata correctly

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refactor(cpus): register DSU errata with the errata framework's wrappers

The existing DSU errata workarounds hijack the errata framework's inner
workings to register with it. However, that is undesi

refactor(cpus): register DSU errata with the errata framework's wrappers

The existing DSU errata workarounds hijack the errata framework's inner
workings to register with it. However, that is undesirable as any change
to the framework may end up missing these workarounds. So convert the
checks and workarounds to macros and have them included with the
standard wrappers.

The only problem with this is the is_scu_present_in_dsu weak function.
Fortunately, it is only needed for 2 of the errata and only on 3 cores.
So drop it, assuming the default behaviour and have the callers handle
the exception.

Change-Id: Iefa36325804ea093e938f867b9a6f49a6984b8ae
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "feat(qemu): add hob support for qemu platforms" into integration

feat(qemu): add hob support for qemu platforms

This change introduces the hob support for both qemu platforms (virt and
sbsa).

As the hob list feature relies on transfer list, the transfer list
sup

feat(qemu): add hob support for qemu platforms

This change introduces the hob support for both qemu platforms (virt and
sbsa).

As the hob list feature relies on transfer list, the transfer list
support is promoted to common qemu build configuration. The platforms
specific definitions are updated accordingly.

Change-Id: I473d83388fe95408d34515bf7bcbdd64ce4e777d
Signed-off-by: Kun Qin <kuqin@microsoft.com>

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Merge changes I1f662f82,I59a3b297 into integration

* changes:
fix(build): include platform mk earlier
fix(arm): use EL3_PAS in MAP_BL2_TOTAL definition

fix(build): include platform mk earlier

Move platform.mk inclusion in top level Makefile to permit a platform
specifying BRANCH_PROTECTION option.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.

fix(build): include platform mk earlier

Move platform.mk inclusion in top level Makefile to permit a platform
specifying BRANCH_PROTECTION option.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I1f662f82cd949eedfdbb61b9f66de15c46fb3106

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Merge changes from topic "gerrit-master-v3" into integration

* changes:
feat(qemu-sbsa): add support for RME on SBSA machine
feat(qemu-sbsa): configure RMM manifest based on system RAM
feat(qe

Merge changes from topic "gerrit-master-v3" into integration

* changes:
feat(qemu-sbsa): add support for RME on SBSA machine
feat(qemu-sbsa): configure RMM manifest based on system RAM
feat(qemu-sbsa): configure GPT based on system RAM
feat(qemu-sbsa): adjust DT memory start address when supporting RME
feat(qemu-sbsa): relocate DT after the RMM when RME is enabled
feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE
feat(qemu-sbsa): increase maximum FIP size
refactor(qemu-sbsa): move all DT related functions to sbsa_platform.c
refactor(qemu-sbsa): create accessor functions for platform info
refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful
refactor(qemu-sbsa): move DT related structures to their own header
refactor(qemu-sbsa): rename struct dynamic_platform_info
refactor(qemu): make L0GPT size configurable
refactor(qemu): move GPT setup to BL31
fix(qemu-sbsa): fix compilation error when accessing DT functions

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feat(qemu-sbsa): relocate DT after the RMM when RME is enabled

When RME is enabled, (1) the RMM is installed at the base of system RAM,
(2) the base of the system RAM is shifted upward, after the RM

feat(qemu-sbsa): relocate DT after the RMM when RME is enabled

When RME is enabled, (1) the RMM is installed at the base of system RAM,
(2) the base of the system RAM is shifted upward, after the RMM and (3)
the device tree is relocated to the new system RAM base.

This patch relocates the device tree to the new system RAM base before
the RMM is installed in RAM. From there, other accesses to the device
tree are using the new location.

Change-Id: I0cb4e060ca33a11becd78fe48fab4dc76f0b484b
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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fix(qemu-sbsa): fix compilation error when accessing DT functions

When building SBSA, using DT functions from fdt_wrappers.c produces a
linker error. Adding:

BL2_SOURCES += ${FDT_WRAPPERS_SOURCES}

fix(qemu-sbsa): fix compilation error when accessing DT functions

When building SBSA, using DT functions from fdt_wrappers.c produces a
linker error. Adding:

BL2_SOURCES += ${FDT_WRAPPERS_SOURCES}

fixes the problem. Since the same inclusion would be present in both
qemu/platform.mk and qemu_sbsa/platform.mk, do the changes in
qemu/common/common.mk.

Change-Id: I775b06c1741f6618813c5e1d2c64cdc1888d8519
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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Merge "feat(qemu): allow ARM_ARCH_MAJOR/MINOR override" into integration

Merge "feat(qemu): enable FEAT_ECV when present" into integration

feat(qemu): allow ARM_ARCH_MAJOR/MINOR override

An upcoming change to the RME support code will use atomic instructions
introduced in Armv8.1 in order to implement bitlocks. In order to do
this, the

feat(qemu): allow ARM_ARCH_MAJOR/MINOR override

An upcoming change to the RME support code will use atomic instructions
introduced in Armv8.1 in order to implement bitlocks. In order to do
this, the code needs to be built with appropriate -march compiler flag
(otherwise the assembler complains about invalid instructions). One way
to do this is specifying ARM_ARCH_MAJOR/MINOR version greater than 8.0,
which is what the main Makefile does when ENABLE_RME is set.

Allow the main Makefile to override the ARM_ARCH_MAJOR/MINOR variables
on the QEMU platform, so that it can also build the bitlock functions.

This only affects firmware built with ENABLE_RME, which is an
experimental feature both in TF-A and QEMU. The QEMU platform code
doesn't support booting an ENABLE_RME firmware on non-RME CPUs at the
moment.

As a result of this change, when ENABLE_RME is set,
make_helpers/arch_features.mk sets ENABLE_TRF_FOR_NS to 1, which needs
to be overridden by the QEMU Makefile.

Change-Id: I695fc98b21d07f6c84003d9e36a57cad2a3c806e
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): enable FEAT_ECV when present

QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
auto-detecting the fe

feat(qemu): enable FEAT_ECV when present

QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
auto-detecting the feature on the QEMU platforms, in order to set
SCR.ECVEN. Without this, EL2 gets undefined instruction exceptions when
trying to access the new CNTPOFF register.

Change-Id: I555a5f9a9a84fd23e64ca85219ed1599204c6bb2
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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Merge "fix(qemu): disable FEAT_SB" into integration

fix(qemu): disable FEAT_SB

qemu/qemu_sbsa platforms support wide selection of cpu cores. From
Cortex-A57 (v8.0) to Neoverse-N2 (v9.0) one. Only the last one (and
'max' which supports everything poss

fix(qemu): disable FEAT_SB

qemu/qemu_sbsa platforms support wide selection of cpu cores. From
Cortex-A57 (v8.0) to Neoverse-N2 (v9.0) one. Only the last one (and
'max' which supports everything possible) supports FEAT_SB.

Runtime check for ENABLE_FEAT_SB does not work in our case and we want
to have working platform.

Change-Id: Ic27d5af20ad76ae44c4211d28694e91ec62bddc1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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Merge changes from topic "qemu-rme" into integration

* changes:
feat(qemu): support TRP for RME
feat(qemu): load and run RMM image
feat(qemu): setup Granule Protection Table
feat(qemu): setu

Merge changes from topic "qemu-rme" into integration

* changes:
feat(qemu): support TRP for RME
feat(qemu): load and run RMM image
feat(qemu): setup Granule Protection Table
feat(qemu): setup memory map for RME
feat(qemu): update mapping types for RME
feat(qemu): use mock attestation functions for RME
fix(qemu): increase max FIP size

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feat(qemu): use mock attestation functions for RME

Since QEMU doesn't yet emulate hardware attestation, provide hardcoded
key and token to demonstrate attestation for RME. They are copied from
the m

feat(qemu): use mock attestation functions for RME

Since QEMU doesn't yet emulate hardware attestation, provide hardcoded
key and token to demonstrate attestation for RME. They are copied from
the mock values for the FVP platform.

Change-Id: I9ce686955345854e9409af5c3aad2a648adea226
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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Merge "refactor(qemu): change way how we enable cpu features" into integration

refactor(qemu): change way how we enable cpu features

We have to handle wide selection of cpu cores in one TF-A binary:
- v8.0: a53, a57, a72
- v8.2: a55, a76, n1
- v8.4: v1
- v9.0: a710, n2

And th

refactor(qemu): change way how we enable cpu features

We have to handle wide selection of cpu cores in one TF-A binary:
- v8.0: a53, a57, a72
- v8.2: a55, a76, n1
- v8.4: v1
- v9.0: a710, n2

And then we have QEMU's hybrid: 'max' which has everything QEMU can
emulate.

TF-A for QEMU platforms was built for v8.5 architecture. But turned out
that 'max' has v8.7 flag now (HCX) which we need to have. And this
enabled set of mandatory features which made TF-A not-bootable on
v8.0/8.2 cpus.

So I decided to follow Arm FVP way and do build for v8.0 with set of
feature flags enabled. This way we have bare minimum to make v8.0 cpus
boot. And then all features from newer cores are enabled with runtime
check which makes them boot.

Tested with BSA/SBSA ACS and Debian Linux 6.5 kernel.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ib87bdab992536c65ce0747ce1520682eafc18d39
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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